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61. 发明授权

US06852652B1 Method of making relaxed silicon-germanium on glass via layer transfer 失效
标题翻译：通过层转移在玻璃上制备松弛的硅 - 锗的方法
公开(公告)号：US06852652B1
公开(公告)日：2005-02-08
申请号：US10674369
申请日：2003-09-29
申请人： Jer-Shen Maa , Jong-Jan Lee , Douglas J. Tweet , Steve Roy Droes
发明人： Jer-Shen Maa , Jong-Jan Lee , Douglas J. Tweet , Steve Roy Droes
IPC分类号： C23C14/48 , H01L21/00 , H01L21/02 , H01L21/20 , H01L21/336 , H01L21/762 , H01L27/12 , H01L29/786
CPC分类号： H01L21/76254 , Y10S438/933
摘要： A method of forming a silicon-germanium layer on an insulator includes preparing a silicon substrate; depositing a layer of silicon-germanium on the silicon substrate to form a silicon/silicon-germanium portion; implanting hydrogen ions in the silicon-germanium layer; preparing an insulator substrate; bonding the silicon/silicon-germanium portion to the insulator substrate with the silicon-germanium layer in contact with the insulator substrate to form a bonded entity; curing the bonded entity; and thermally annealing the bonded entity to split the bonded entity into a silicon/silicon germanium portion and a silicon-germanium-on-insulator portion and to relax the silicon germanium layers.
摘要翻译：在绝缘体上形成硅 - 锗层的方法包括制备硅衬底; 在硅衬底上沉积一层硅 - 锗以形成硅/硅 - 锗部分; 在硅 - 锗层中注入氢离子; 制备绝缘体基板; 将硅/锗锗部分接合到绝缘体衬底，硅 - 锗层与绝缘体衬底接触以形成键合实体; 养护保税实体; 以及对所述结合的实体进行热退火以将所述结合的实体分裂成硅/硅锗部分和绝缘体上的硅 - 锗部分并使所述硅锗层松弛。

62. 发明授权

US07800148B2 CMOS active pixel sensor 有权
标题翻译： CMOS有源像素传感器
公开(公告)号：US07800148B2
公开(公告)日：2010-09-21
申请号：US12178169
申请日：2008-07-23
申请人： Jong-Jan Lee , Sheng Teng Hsu , Douglas James Tweet , Jer-Shen Maa
发明人： Jong-Jan Lee , Sheng Teng Hsu , Douglas James Tweet , Jer-Shen Maa
IPC分类号： H01L31/062
CPC分类号： H01L27/14647
摘要： A CMOS active pixel sensor includes a silicon-on-insulator substrate having a silicon substrate with an insulator layer formed thereon and a top silicon layer formed on the insulator layer. A stacked pixel sensor cell includes a bottom photodiode fabricated on the silicon substrate, for sensing light of a longest wavelength; a middle photodiode fabricated on the silicon substrate, for sensing light of a medium wavelength, which is stacked above the bottom photodiode; and a top photodiode fabricated on the top silicon layer, for sensing light of a shorter wavelength, which is stacked above the middle and bottom photodiodes. Pixel transistor sets are fabricated on the top silicon layer and are associated with each pixel sensor cell by electrical connections which extend between each of the photodiodes and respective pixel transistor(s). CMOS control circuitry is fabricated adjacent to an array of active pixel sensor cells and electrically connected thereto.
摘要翻译： CMOS有源像素传感器包括具有在其上形成有绝缘体层的硅衬底和形成在绝缘体层上的顶部硅层的绝缘体上硅衬底。层叠像素传感器单元包括：制造在硅衬底上的底部光电二极管，用于感测最长波长的光; 制造在硅衬底上的中间光电二极管，用于感测中等波长的光; 和制造在顶部硅层上的顶部光电二极管，用于感测较短波长的光，该光被层叠在中间和底部光电二极管的上方。像素晶体管组被制造在顶部硅层上，并且通过在每个光电二极管和相应的像素晶体管之间延伸的电连接与每个像素传感器单元相关联。 CMOS控制电路与有源像素传感器单元的阵列相邻并且与其电连接。

63. 发明申请

US20080164577A1 Patterned silicon submicron tubes 失效
标题翻译：图案硅亚微米管
公开(公告)号：US20080164577A1
公开(公告)日：2008-07-10
申请号：US11649634
申请日：2007-01-04
申请人： Tingkai Li , Jong-Jan Lee , Jer-Shen Maa , Sheng Teng Hsu
发明人： Tingkai Li , Jong-Jan Lee , Jer-Shen Maa , Sheng Teng Hsu
IPC分类号： H01L21/3065 , H01L29/06
CPC分类号： H01L29/0665 , B82Y10/00 , H01L21/306 , H01L29/0669 , H01L29/0673 , Y10S977/743
摘要： An array of submicron silicon (Si) tubes is provided with a method for patterning submicron Si tubes. The method provides a Si substrate, and forms a silicon dioxide film overlying the Si substrate. An array of silicon dioxide rods is formed from the silicon dioxide film, and Si3N4 tubes are formed surrounding the silicon dioxide rods. The silicon dioxide rods are etched away. Then, exposed regions of the Si substrate are etched, forming Si tubes underlying the Si3N4 tubes. Finally, the Si3N4 tubes are removed.
摘要翻译：亚微米硅（Si）管的阵列具有用于构图亚微米Si管的方法。该方法提供Si衬底，并形成覆盖Si衬底的二氧化硅膜。由二氧化硅膜形成二氧化硅棒的阵列，并且在二氧化硅棒周围形成Si 3 N 4 N 4管。二氧化硅棒被蚀刻掉。然后，蚀刻Si衬底的暴露区域，形成Si 3 N 4 N 4管子下面的Si管。最后，去除Si 3 N 4 N 4管。

64. 发明申请

US20060246606A1 Self-aligned cross point resistor memory array 有权
标题翻译：自对准交叉点电阻存储器阵列
公开(公告)号：US20060246606A1
公开(公告)日：2006-11-02
申请号：US11120385
申请日：2005-05-02
申请人： Sheng Hsu , Jong-Jan Lee , Jer-Shen Maa , Douglas Tweet , Wei-Wei Zhuang
发明人： Sheng Hsu , Jong-Jan Lee , Jer-Shen Maa , Douglas Tweet , Wei-Wei Zhuang
IPC分类号： H01L21/8234
CPC分类号： H01L27/101 , H01L27/2409 , H01L27/2481 , H01L45/04 , H01L45/1233 , H01L45/147 , H01L45/1683
摘要： A method of fabricating resistor memory array includes preparing a silicon substrate; depositing a bottom electrode, a sacrificial layer, and a hard mask layer on a substrate P+ layer; masking, patterning and etching to remove, in a first direction, a portion of the hard mask, the sacrificial material, the bottom electrode; depositing a layer of silicon oxide; masking, patterning and etching to remove, in a second direction perpendicular to the first direction, a portion of the hard mask, the sacrificial material, the bottom electrode;, and over etching to an N+ layer and at least 100 nm of the silicon substrate; depositing of a layer of silicon oxide; etching to remove any remaining hard mask and any remaining sacrificial material; depositing a layer of CMR material; depositing a top electrode; applying photoresist, patterning the photoresist and etching the top electrode; and incorporating the memory array into an integrated circuit.
摘要翻译：制造电阻器存储器阵列的方法包括制备硅衬底; 在衬底P +层上沉积底部电极，牺牲层和硬掩模层; 掩模，图案化和蚀刻以在第一方向上去除硬掩模，牺牲材料，底部电极的一部分; 沉积一层氧化硅; 掩模，图案化和蚀刻以在垂直于第一方向的第二方向上去除硬掩模，牺牲材料，底部电极的一部分，并且对N +层和至少100nm的硅衬底进行过蚀刻 ; 沉积一层氧化硅; 蚀刻以除去任何剩余的硬掩模和任何剩余的牺牲材料; 沉积一层CMR材料; 沉积顶部电极; 施加光致抗蚀剂，图案化光致抗蚀剂并蚀刻顶部电极; 并将存储器阵列并入集成电路中。

65. 发明授权

US07405098B2 Smooth surface liquid phase epitaxial germanium 有权
标题翻译：光滑表面液相外延锗
公开(公告)号：US07405098B2
公开(公告)日：2008-07-29
申请号：US11339017
申请日：2006-01-25
申请人： Jong-Jan Lee , Jer-Shen Maa , Douglas J. Tweet , David R. Evans , Allen Burmaster
发明人： Jong-Jan Lee , Jer-Shen Maa , Douglas J. Tweet , David R. Evans , Allen Burmaster
IPC分类号： H01L21/00 , H01L21/84 , H01L21/331 , H01L21/76 , H01L21/20 , H01L21/36
CPC分类号： C30B19/00 , C30B29/08 , H01L21/02381 , H01L21/02488 , H01L21/02532 , H01L21/02623 , H01L21/02639 , H01L21/30625 , H01L21/7624 , H01L27/14683 , H01L27/14689 , H01L29/16 , H01L29/78 , H01L31/028 , H01L31/105 , H01L31/1126 , H01L31/1136 , H01L31/1804 , H01L31/1808 , Y02E10/547 , Y02P70/521
摘要： A method is provided for forming a liquid phase epitaxial (LPE) germanium (Ge)-on-insulator (GOI) thin-film with a smooth surface. The method provides a silicon (Si) wafer, forms a silicon nitride insulator layer overlying the Si wafer, and selectively etches the silicon nitride insulator layer, forming a Si seed access region. Then, the method conformally deposits Ge overlying the silicon nitride insulator layer and Si seed access region, forming a Ge layer with a first surface roughness, and smoothes the Ge layer using a chemical-mechanical polish (CMP) process. Typically, the method encapsulates the Ge layer and anneals the Ge layer to form a LPE Ge layer. A Ge layer is formed with a second surface roughness, less than the first surface roughness. In some aspects, the method forms an active device in the LPE Ge layer.
摘要翻译：提供一种形成具有光滑表面的液相外延（LPE）锗（Ge） - 绝缘体（GOI）薄膜的方法。该方法提供硅（Si）晶片，形成覆盖Si晶片的氮化硅绝缘体层，并且选择性地蚀刻氮化硅绝缘体层，形成Si种子接入区域。然后，该方法共同沉积覆盖氮化硅绝缘体层和Si种子访问区域的Ge，形成具有第一表面粗糙度的Ge层，并且使用化学机械抛光（CMP）工艺平滑Ge层。通常，该方法封装Ge层并退火Ge层以形成LPE Ge层。 Ge层形成有小于第一表面粗糙度的第二表面粗糙度。在某些方面，该方法在LPE Ge层中形成有源器件。

66. 发明授权

US07030002B2 Low temperature anneal to reduce defects in hydrogen-implanted, relaxed SiGe layer 有权
标题翻译：低温退火以减少氢注入，弛豫SiGe层的缺陷
公开(公告)号：US07030002B2
公开(公告)日：2006-04-18
申请号：US10780929
申请日：2004-02-17
申请人： Douglas J. Tweet , Jong-Jan Lee , Jer-Shen Maa
发明人： Douglas J. Tweet , Jong-Jan Lee , Jer-Shen Maa
IPC分类号： H01L21/28 , H01L21/13205 , H01L21/00 , H01L21/84 , H01L21/36
CPC分类号： H01L21/02381 , H01L21/0245 , H01L21/02502 , H01L21/02532 , H01L21/02694 , H01L21/324 , H01L21/3247
摘要： A method of forming a SiGe layer having a relatively high Ge content includes preparing a silicon substrate; depositing a layer of SiGe to a thickness of between about 100 nm to 500 nm, wherein the Ge content of the SiGe layer is equal to or greater than 10%, implanting H2+ ions through the SiGe layer into the substrate at a dose of between about 2×1014 cm−2 to 2×1016 cm−2, at an energy of between about 20 keV to 100+ keV; low temperature thermal annealing at a temperature of between about 200° C. to 400° C. for between about ten minutes and ten hours; high temperature thermal annealing the substrate and SiGe layer, to relax the SiGe layer, in an inert atmosphere at a temperature of between about 650° C. to 1000° C. for between about 30 seconds and 30 minutes; and depositing a layer of silicon-based material on the relaxed SiGe layer to a thickness of between about 5 nm to 30 nm.
摘要翻译：形成Ge含量较高的SiGe层的方法包括制备硅衬底; 将SiGe层沉积至约100nm至500nm的厚度，其中SiGe层的Ge含量等于或大于10％，注入H 2 O + SUP +离子通过SiGe层以约2×10 14 cm -2至2×10 16 cm -3的剂量进入衬底，在约20keV至100eKeV之间的能量; 在约200℃至400℃的温度下进行约10分钟至10小时的低温热退火; 在惰性气氛中，在约650℃至1000℃的温度下，在约30秒至30分钟之间，使衬底和SiGe层进行高温热退火以使SiGe层松弛; 以及在松弛的SiGe层上沉积一层硅基材料至约5nm至30nm的厚度。

67. 发明授权

US06746902B2 Method to form relaxed sige layer with high ge content 有权
标题翻译：形成具有高Ge含量的轻松精神层的方法
公开(公告)号：US06746902B2
公开(公告)日：2004-06-08
申请号：US10062319
申请日：2002-01-31
申请人： Jer-Shen Maa , Douglas James Tweet , Sheng Teng Hsu
发明人： Jer-Shen Maa , Douglas James Tweet , Sheng Teng Hsu
IPC分类号： H01L2100
CPC分类号： H01L21/322 , H01L21/02381 , H01L21/0245 , H01L21/02532 , H01L21/02694 , Y10S438/933
摘要： A method of forming a SiGe layer having a relatively high Ge content includes preparing a silicon substrate; depositing a layer of SiGe to a thickness of between about 100 nm to 500 nm, wherein the Ge content of the SiGe layer is equal to or greater than 22%, by molecular weight; implanting H+ ions into the SiGe layer at a dose of between about 1·1016 cm−2 to 5·1016 cm−2, at an energy of between about 20 keV to 45 keV; thermal annealing the substrate and SiGe layer, to relax the SiGe layer, in an inert atmosphere at a temperature of between about 650° C. to 950° C. for between about 30 seconds and 30 minutes; and depositing a layer of tensile-strained silicon on the relaxed SiGe layer to a thickness of between about 5 nm to 30 nm.
摘要翻译：形成Ge含量较高的SiGe层的方法包括制备硅衬底; 将SiGe层沉积至约100nm至500nm的厚度，其中SiGe层的Ge含量通过分子量等于或大于22％; 以约20keV至45keV之间的能量以约1.10 16 cm -2至5.10 16 cm -2的剂量将H +离子注入SiGe层; 热处理基板和SiGe层，以在约650℃至950℃的温度的惰性气氛中放松SiGe层约30秒至30分钟; 以及在弛豫的SiGe层上沉积拉伸应变硅层至约5nm至30nm的厚度。

68. 发明授权

US06339245B1 Nitride overhang structure for the silicidation of transistor electrodes with shallow junctions 有权
标题翻译：用于具有浅结的晶体管电极的硅化的氮化物突出结构
公开(公告)号：US06339245B1
公开(公告)日：2002-01-15
申请号：US09378653
申请日：1999-08-20
申请人： Jer-Shen Maa , Sheng Teng Hsu , Chien-Hsiung Peng
发明人： Jer-Shen Maa , Sheng Teng Hsu , Chien-Hsiung Peng
IPC分类号： H01L2976
CPC分类号： H01L29/6659 , H01L21/28052 , H01L21/28518 , H01L29/665 , H01L29/6656
摘要： A method of forming a temporary overhang structure to shield the source/drain edges near the gate electrode from the deposition of silicidation metal is provided. The growth of silicide on the source/drain regions remains controlled, without the presence of silicidation metal on the gate electrode sidewalls near the source/drain edges. The resulting silicide layer does not have edge growths interfering with the source/drain junction areas. The overhang structure is formed by covering the gate electrode with two insulators having differing etch selectivities. The top insulator is anisotropically etched so that only the top insulator covering the gate electrode vertical sidewalls remains. The exposed bottom insulator is isotropically etched to form a gap between the top insulator and the source/drain region surfaces. When silicidation metal is deposited, the gap prevents the deposition of metal between the gate electrode and the source/drain region surfaces. A transistor, with an overhang structure, fabricated by the above-mentioned procedure is also provided.
摘要翻译：提供了形成临时突出结构以屏蔽栅电极附近的源/漏边缘与沉积硅化金属的方法。源极/漏极区域上的硅化物的生长保持受控，而在源极/漏极边缘附近的栅电极侧壁上不存在硅化金属。所得到的硅化物层不具有干扰源极/漏极结区域的边缘增长。通过用具有不同蚀刻选择性的两个绝缘体覆盖栅电极来形成突出结构。顶绝缘体被各向异性地蚀刻，使得仅覆盖覆盖栅电极垂直侧壁的顶绝缘体保留。暴露的底部绝缘体被各向同性地蚀刻以在顶部绝缘体和源极/漏极区域表面之间形成间隙。当沉积硅化金属时，间隙防止金属沉积在栅电极和源/漏区表面之间。还提供了通过上述程序制造的具有突出结构的晶体管。

69. 发明授权

US06218249B1 MOS transistor having shallow source/drain junctions and low leakage current 失效
标题翻译： MOS晶体管具有较浅的源/漏结和低漏电流
公开(公告)号：US06218249B1
公开(公告)日：2001-04-17
申请号：US09455588
申请日：1999-12-06
申请人： Jer-Shen Maa , Sheng Teng Hsu , Chien-Hsiung Peng
发明人： Jer-Shen Maa , Sheng Teng Hsu , Chien-Hsiung Peng
IPC分类号： H01L21336
CPC分类号： H01L21/28518 , H01L21/28052 , H01L29/665 , H01L29/6659
摘要： A process of forming silicide at uniform rates across the entire source/drain region is provided. A two-step annealing method permits the thickness of the silicide formed on the edge of a silicon electrode to be substantially the same as it is in the center of the electrode. A first, low temperature anneal begins the salicidation process across the source/drain electrode surface. The time and temperature are controlled so that the metal is only partially consumed. The annealing is interrupted to remove excess silicidation metal, especially the unreacted metal overlying oxide areas neighboring the silicon electrode. Then, the silicidation is completed at a higher temperature anneal. Because the excess metal has been removed, the resulting silicide layer is uniformly flat, permitting the transistor to be fabricated with shallow junction areas and low leakage currents. In one embodiment of the invention, the crystalline structure of source and drain surfaces is annihilated before the deposition of metal, to lower annealing temperatures and add precise control to the silicidation process. A transistor having a uniformly thick silicide layer, fabricated in accordance with the above-mentioned method, is also provided.
摘要翻译：提供了在整个源极/漏极区域以均匀的速率形成硅化物的工艺。两步退火方法允许形成在硅电极边缘上的硅化物的厚度与电极中心基本相同。首先，低温退火开始跨越源/漏电极表面的盐析过程。控制时间和温度，使得金属仅被部分消耗。中断退火以去除过量的硅化金属，特别是覆盖与硅电极相邻的氧化物区域的未反应的金属。然后，在较高温度的退火下完成硅化。由于去除了多余的金属，所得到的硅化物层是均匀平坦的，从而允许晶体管被制造成具有浅结的区域和低的漏电流。在本发明的一个实施例中，源极和漏极表面的晶体结构在金属沉积之前被消除，以降低退火温度并且增加对硅化工艺的精确控制。还提供了具有根据上述方法制造的均匀厚的硅化物层的晶体管。

70. 发明授权

US06368960B1 Double sidewall raised silicided source/drain CMOS transistor 失效
标题翻译：双侧壁提升硅化源/漏极CMOS晶体管
公开(公告)号：US06368960B1
公开(公告)日：2002-04-09
申请号：US09113667
申请日：1998-07-10
申请人： Sheng Teng Hsu , Jer-Shen Maa
发明人： Sheng Teng Hsu , Jer-Shen Maa
IPC分类号： H01L21336
CPC分类号： H01L29/66757 , H01L21/84 , H01L27/1203 , H01L29/665
摘要： A method of forming a silicided device includes preparing a substrate by forming device areas thereon; providing structures that are located between the substrate and any silicide layers; forming a first layer of a first reactive material over the formed structures; providing insulating regions in selected portions of the structure; forming a second layer of a second reactive material over the insulating regions and the first layer of first reactive material; reacting the first and second reactive materials to form silicide layers; removing any un-reacted reactive material; forming structures that are located on the silicide layers; and metallizing the device.
摘要翻译：一种形成硅化器件的方法包括通过在其上形成器件区域来制备衬底; 提供位于衬底和任何硅化物层之间的结构; 在所形成的结构上形成第一反应性材料的第一层; 在结构的选定部分提供绝缘区域; 在所述绝缘区域和所述第一反应性材料层上形成第二反应性材料层; 使第一和第二反应性材料反应形成硅化物层; 去除任何未反应的反应性材料; 形成位于硅化物层上的结构; 并对该装置进行金属化。

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