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61. 发明申请

US20080062807A1 MULTI-COLUMN ADDRESSING MODE MEMORY SYSTEM INCLUDING AN INTEGRATED CIRCUIT MEMORY DEVICE 有权
标题翻译：包括集成电路存储器件的多字段寻址模式存储器系统
公开(公告)号：US20080062807A1
公开(公告)日：2008-03-13
申请号：US11853708
申请日：2007-09-11
申请人： Frederick Ware , Lawrence Lai , Chad Bellows , Wayne Richardson
发明人： Frederick Ware , Lawrence Lai , Chad Bellows , Wayne Richardson
IPC分类号： G11C8/00
CPC分类号： G11C8/10 , G11C8/12 , G11C8/16
摘要： A memory system includes a master device, such as a graphics controller or processor, and an integrated circuit memory device operable in a dual column addressing mode. The integrated circuit memory device includes an interface and column decoder to access a row of storage cells or a page in a memory bank. During a first mode of operation, a first row of storage cells in a first memory bank is accessible in response to a first column address. During a second mode of operation, a first plurality of storage cells in the first row of storage cells is accessible in response to a second column address during a column cycle time interval. A second plurality of storage cells in the first row of storage cells is accessible in response to a third column address during the column cycle time interval. The first and second pluralities of storage cells are concurrently accessible from the interface.
摘要翻译：存储器系统包括主设备，诸如图形控制器或处理器，以及以双列寻址模式可操作的集成电路存储器件。集成电路存储器件包括一个接口和列解码器，以访问一行存储单元或存储体中的一页。在第一操作模式期间，响应于第一列地址可访问第一存储体中的第一行存储单元。在第二操作模式期间，响应于列周期时间间隔期间的第二列地址，可访问第一行存储单元中的第一多个存储单元。响应于列周期时间间隔期间的第三列地址，可访问第一行存储单元中的第二多个存储单元。第一和第二多个存储单元可以从该接口同时访问。

62. 发明申请

US20060004955A1 Dynamic memory supporting simultaneous refresh and data-access transactions 有权
公开(公告)号：US20060004955A1
公开(公告)日：2006-01-05
申请号：US11215339
申请日：2005-08-29
申请人： Frederick Ware , Richard Perego
发明人： Frederick Ware , Richard Perego
IPC分类号： G06F12/00
CPC分类号： G11C11/406 , G06F12/00 , G06F13/1605 , G11C11/40603
摘要： Described are dynamic memory systems that perform overlapping refresh and data-access (read or write) transactions that minimize the impact of the refresh transaction on memory performance. The memory systems support independent and simultaneous activate and precharge operations directed to different banks. Two sets of address registers enable the system to simultaneously specify different banks for refresh and data-access transactions.

63. 发明申请

US20050005056A1 Method and apparatus for controlling a read valid window of a synchronous memory device 有权
标题翻译：用于控制同步存储器件的读取有效窗口的方法和装置
公开(公告)号：US20050005056A1
公开(公告)日：2005-01-06
申请号：US10893206
申请日：2004-07-16
申请人： Frederick Ware
发明人： Frederick Ware
IPC分类号： G11C7/10 , G11C11/4076 , G11C11/4093 , G11C11/4096 , H04L7/00
CPC分类号： G11C7/1066 , G11C7/1051 , G11C7/1072 , G11C11/4076 , G11C11/4093 , G11C11/4096
摘要： A method and apparatus are shown for increasing a propagation delay that may be tolerated between a memory controller and a memory device. The present invention provides for selection between two data paths for each word, where a first data path latches the data word from a DQS domain on a falling edge of a CLK0 domain and a second data patch latches the data word from the DQS domain on a rising edge of the CLK0 domain. Selection of the first data path permits larger relative propagation delays between the controller and memory to be accommodated without loss of data. Further, multi-cycle source synchronous timing logic may be employed that provides for the capture of data words on rising and falling edges of successive cycles of the DQS domain and storage for an additional cycle of the DQS domain to extend the period of time that each data word from the DQS domain is available and valid for the CLK0 domain. Selection of the first data path may also be used to accommodate shorter relative propagation delays between the controller and memory without loss of data when the propagation delay is short enough that the data from the memory is valid in advance of a first falling edge of the CLK0 domain by a margin that is at least a set-up time interval for the controller.
摘要翻译：示出了用于增加可在存储器控制器和存储器件之间容许的传播延迟的方法和装置。本发明提供了用于每个字的两个数据路径之间的选择，其中第一数据路径在CLK0域的下降沿上锁存来自DQS域的数据字，而第二数据块在第一数据路径上将来自DQS域的数据字锁存在 CLK0域的上升沿。选择第一数据路径允许在不损失数据的情况下容纳控制器和存储器之间较大的相对传播延迟。此外，可以采用多周期源同步定时逻辑，其提供在DQS域的连续周期的上升沿和下降沿上的数据字的捕获以及用于DQS域的附加周期的存储以延长每个来自DQS域的数据字可用于CLK0域。当传播延迟足够短使得来自存储器的数据在CLK0的第一下降沿之前有效时，第一数据路径的选择也可用于适应控制器和存储器之间较短的相对传播延迟，而不会丢失数据域至少为控制器的设置时间间隔。

64. 发明授权

US08649460B2 Techniques for multi-wire encoding with an embedded clock 有权
标题翻译：使用嵌入式时钟进行多线编码的技术
公开(公告)号：US08649460B2
公开(公告)日：2014-02-11
申请号：US12663230
申请日：2008-06-04
申请人： Frederick Ware , Jade Kizer
发明人： Frederick Ware , Jade Kizer
IPC分类号： H04L27/00
CPC分类号： H03M5/16 , G11C7/1066 , G11C7/1093 , G11C7/222 , H03K3/356026 , H03K19/01855 , H03M5/20 , H04L25/0272 , H04L25/4906 , H04L25/4917
摘要： Techniques for multi-wire encoding with an embedded clock are disclosed. In one particular exemplary embodiment, the techniques may be realized as a transmitter component. The transmitter component may comprise at least one encoder module to generate a set of symbols, each symbol being represented by a combination of signal levels on a set of wires. The transmitter component may also comprise at least one signaling module to transmit one or more of the symbols over the set of wires according to a transmit clock. The transmitter component may additionally comprise control logic to restrict transmission of first and second subsets of the set of symbols to respective first and second portions of a clock cycle of the transmit clock, such that a signal differential among at least two of the set of wires exhibits a switching behavior that has a same frequency as the transmit clock.
摘要翻译：公开了一种具有嵌入式时钟的多线编码技术。在一个特定的示例性实施例中，这些技术可以被实现为发射器部件。发射机组件可以包括至少一个编码器模块以产生一组符号，每个符号由一组线路上的信号电平的组合表示。发射机组件还可以包括至少一个信令模块，用于根据传输时钟在一组线路上传输一个或多个符号。发射机组件可以另外包括控制逻辑，以将该组符号的第一和第二子集的发射限制到发射时钟的时钟周期的相应第一和第二部分，使得在该组线中的至少两个之间的信号差分表现出与发送时钟频率相同的开关行为。

65. 发明授权

US08497544B2 Repairing defects in a nonvolatile semiconductor memory module utilizing a heating element 失效
标题翻译：利用加热元件修复非易失性半导体存储器模块中的缺陷
公开(公告)号：US08497544B2
公开(公告)日：2013-07-30
申请号：US13486977
申请日：2012-06-01
申请人： Gary B. Bronner , Ming Li , Donald R. Mullen , Frederick Ware , Kevin S. Donnelly
发明人： Gary B. Bronner , Ming Li , Donald R. Mullen , Frederick Ware , Kevin S. Donnelly
IPC分类号： H01L29/76 , H01L21/8238
CPC分类号： G11C16/349 , G11C16/3418 , H01L23/3128 , H01L23/345 , H01L24/73 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/48145 , H01L2224/48227 , H01L2224/73253 , H01L2224/73265 , H01L2225/0651 , H01L2225/06517 , H01L2225/06562 , H01L2225/06589 , H01L2924/15311 , H01L2924/19107 , H01L2924/00012 , H01L2924/00
摘要： A memory module includes multiple memory devices mounted to a substrate and one or more discrete heating elements disposed in thermal contact with the memory devices. Each of the memory devices includes charge-storing memory cells subject to operation-induced defects that degrade ability of the memory cells to store data. The discrete heating elements, or single discrete heating element, heats the memory devices to a temperature that anneals the defects.
摘要翻译：存储器模块包括安装到基板的多个存储器件和与存储器件热接触地设置的一个或多个分立加热元件。每个存储器件包括经受操作引起的缺陷的电荷存储存储单元，其使存储器单元存储数据的能力降低。离散加热元件或单独的分立加热元件将存储器件加热到退火缺陷的温度。

66. 发明申请

US20100309964A1 ASYMMETRIC COMMUNICATION ON SHARED LINKS 有权
标题翻译：共享链路上的不对称通信
公开(公告)号：US20100309964A1
公开(公告)日：2010-12-09
申请号：US12809000
申请日：2008-12-19
申请人： Kyung Suk Oh , John Wilson , Frederick Ware , WooPoung Kim , Jade M. Kizer , Brian S. Leibowitz , Lei Luo , John Cronan Eble
发明人： Kyung Suk Oh , John Wilson , Frederick Ware , WooPoung Kim , Jade M. Kizer , Brian S. Leibowitz , Lei Luo , John Cronan Eble
IPC分类号： H04B1/38
CPC分类号： G06F13/4243 , H04L25/4906 , Y02D10/14 , Y02D10/151
摘要： Embodiments of a system that communicates bidirectional data between two devices via shared links is described. In this system, data is transmitted on the shared links by one of the devices using single-ended drivers, and corresponding symbols are received on the shared links by the other device using differential comparison circuits. The data may be encoded as a series of parallel codewords prior to transmission. Each shared link may communicate a respective symbol in each codeword, which can have one of two possible logical values (e.g., a logic 0 or a logic 1). The corresponding symbols received by the other device may comprise a parallel symbol set, and each of the differential comparison circuits may compare symbols received on pairs of the shared links. A decoder in the other device may decode a respective parallel symbol set from the outputs of the differential comparison circuits to recover the encoded data.
摘要翻译：描述通过共享链路在两个设备之间传送双向数据的系统的实施例。在该系统中，使用单端驱动器的设备之一在共享链路上发送数据，并且使用差分比较电路由另一设备在共享链路上接收对应的符号。数据可以在传输之前被编码为一系列并行码字。每个共享链路可以在可以具有两个可能的逻辑值中的一个（例如，逻辑0或逻辑1）的每个码字中传送相应的符号。由另一设备接收的对应符号可以包括并行符号集合，并且每个差分比较电路可以比较在共享链路对上接收到的符号。另一设备中的解码器可以从差分比较电路的输出解码相应的并行符号集合，以恢复编码数据。

67. 发明申请

US20070206429A1 MEMORY COMPONENT WITH MULTIPLE DELAYED TIMING SIGNALS 有权
标题翻译：具有多个延迟时间信号的存储器组件
公开(公告)号：US20070206429A1
公开(公告)日：2007-09-06
申请号：US11746007
申请日：2007-05-08
申请人： Frederick Ware
发明人： Frederick Ware
IPC分类号： G11C7/00
CPC分类号： G11C11/4076 , G06F1/10 , G06F13/1689 , G06F13/4243 , G11C7/1072 , G11C7/22 , G11C8/18 , G11C11/409 , G11C2207/2254
摘要： A memory component having multiple delayed timing signals. Control information specifying a write operation and write data corresponding to the write operation are each received via a separate external signal path. A timing signal is received indicating that the write data is valid write data. Signals corresponding to multiple delayed versions of the timing signal are output for use in determining a propagation delay time between the control information and the write data.
摘要翻译：具有多个延迟定时信号的存储器组件。指定与写入操作相对应的写入操作和写入数据的控制信息各自经由单独的外部信号路径接收。接收到指示写入数据是有效写入数据的定时信号。输出对应于定时信号的多个延迟版本的信号，以用于确定控制信息和写入数据之间的传播延迟时间。

68. 发明申请

US20060203532A1 Early read after write operation memory device, system and method 有权
公开(公告)号：US20060203532A1
公开(公告)日：2006-09-14
申请号：US11434695
申请日：2006-05-16
申请人： Richard Perego , Frederick Ware
发明人： Richard Perego , Frederick Ware
IPC分类号： G11C5/06
CPC分类号： G11C7/22 , G11C7/1051 , G11C7/106 , G11C7/1066 , G11C7/1078 , G11C7/1087 , G11C2207/2281 , G11C2207/229
摘要： A memory device, system and method for allowing an early read operation after one or more write operations is provided according to an embodiment of the present invention. The memory device comprises an interface for providing a first write address, a first write data, and a read address. A memory core is coupled to the interface and includes a first memory section having a first data path and a first address path and a second memory section having a second data path and a second address path. In an embodiment of the present invention, the first data and first address path is independent of the second data and second address path. The first write data is provided on the first data path responsive to the first write address being provided on the first address path while a read data is provided on the second data path responsive to the read address being provided on the second address path.

69. 发明申请

US20060072366A1 Multi-column addressing mode memory system including an integrated circuit memory device 有权
标题翻译：多列寻址模式存储器系统，包括集成电路存储器件
公开(公告)号：US20060072366A1
公开(公告)日：2006-04-06
申请号：US10955193
申请日：2004-09-30
申请人： Frederick Ware , Lawrence Lai , Chad Bellows , Wayne Richardson
发明人： Frederick Ware , Lawrence Lai , Chad Bellows , Wayne Richardson
IPC分类号： G11C8/00
CPC分类号： G11C8/10 , G11C8/12 , G11C8/16
摘要： A memory system includes a master device, such as a graphics controller or processor, and an integrated circuit memory device operable in a dual column addressing mode. The integrated circuit memory device includes an interface and column decoder to access a row of storage cells or a page in a memory bank. During a first mode of operation, a first row of storage cells in a first memory bank is accessible in response to a first column address. During a second mode of operation, a first plurality of storage cells in the first row of storage cells is accessible in response to a second column address during a column cycle time interval. A second plurality of storage cells in the first row of storage cells is accessible in response to a third column address during the column cycle time interval. During a third mode of operation, a first plurality of storage cells in a first row of storage cells in a first memory bank is accessible in response to a first column address. A second plurality of storage cells in a second row of storage cells in a second bank is accessible in response to a second column address. A third plurality of storage cells in the first row of storage cells is accessible in response to a third column address and a fourth plurality of storage cells in the second row of storage cells is accessible in response to a fourth column address. The first and second column addresses are in a first request packet and the third and fourth column addresses are in a second request packet provided by the master device.
摘要翻译：存储器系统包括主设备，诸如图形控制器或处理器，以及以双列寻址模式可操作的集成电路存储器件。集成电路存储器件包括一个接口和列解码器，以访问一行存储单元或存储体中的一页。在第一操作模式期间，响应于第一列地址可访问第一存储体中的第一行存储单元。在第二操作模式期间，响应于列周期时间间隔期间的第二列地址，可访问第一行存储单元中的第一多个存储单元。响应于列周期时间间隔期间的第三列地址，可访问第一行存储单元中的第二多个存储单元。在第三操作模式期间，响应于第一列地址可访问第一存储体中的第一行存储单元中的第一多个存储单元。响应于第二列地址，可访问第二存储体中第二行存储单元中的第二多个存储单元。第一行存储单元中的第三多个存储单元响应于第三列地址而可访问，并且第二行存储单元中的第四多个存储单元响应于第四列地址而可访问。第一列地址和第二列地址在第一请求分组中，并且第三和第四列地址在由主设备提供的第二请求分组中。

70. 发明申请

US20050157579A1 Memory device supporting a dynamically configurable core organization 审中-公开
标题翻译：内存设备支持动态配置的核心组织
公开(公告)号：US20050157579A1
公开(公告)日：2005-07-21
申请号：US11078872
申请日：2005-03-12
申请人： Richard Perego , Donald Stark , Frederick Ware
发明人： Richard Perego , Donald Stark , Frederick Ware
IPC分类号： G06F12/04 , G06F12/06 , G11C5/00 , G11C5/04 , G11C7/10 , G11C8/00 , G11C11/408 , G11C11/4097 , H05K1/11 , H05K1/14
CPC分类号： G06F13/1678 , G06F12/04 , G06F12/06 , G06F12/0646 , G06F13/1657 , G06F13/4022 , G11C5/02 , G11C5/025 , G11C5/04 , G11C5/06 , G11C5/063 , G11C7/1006 , G11C7/1045 , G11C7/1048 , G11C7/106 , G11C7/1072 , G11C7/1087 , G11C8/06 , G11C11/4087 , G11C11/4097 , G11C2207/105 , G11C2207/108 , H05K1/117 , H05K1/14 , H05K2201/09954 , H05K2201/10189 , Y02D10/14 , Y02D10/151
摘要： Described is a memory system in which the memory core organization changes with device width. The number of physical memory banks accessed reduces with device width, resulting in reduced power usage for relatively narrow memory configurations. Increasing the number of logic memory banks for narrow memory widths reduces the likelihood of bank conflicts, and consequently improves speed performance.
摘要翻译：描述了存储器系统，其中存储器核心组织随设备宽度而变化。所访问的物理存储器组的数量随着器件宽度而减少，导致相对较窄的存储器配置的功率消耗减少。增加用于窄内存宽度的逻辑内存库的数量可以减少存储体冲突的可能性，从而提高速度性能。

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