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1. 发明申请

US20100309964A1 ASYMMETRIC COMMUNICATION ON SHARED LINKS 有权
标题翻译：共享链路上的不对称通信
公开(公告)号：US20100309964A1
公开(公告)日：2010-12-09
申请号：US12809000
申请日：2008-12-19
申请人： Kyung Suk Oh , John Wilson , Frederick Ware , WooPoung Kim , Jade M. Kizer , Brian S. Leibowitz , Lei Luo , John Cronan Eble
发明人： Kyung Suk Oh , John Wilson , Frederick Ware , WooPoung Kim , Jade M. Kizer , Brian S. Leibowitz , Lei Luo , John Cronan Eble
IPC分类号： H04B1/38
CPC分类号： G06F13/4243 , H04L25/4906 , Y02D10/14 , Y02D10/151
摘要： Embodiments of a system that communicates bidirectional data between two devices via shared links is described. In this system, data is transmitted on the shared links by one of the devices using single-ended drivers, and corresponding symbols are received on the shared links by the other device using differential comparison circuits. The data may be encoded as a series of parallel codewords prior to transmission. Each shared link may communicate a respective symbol in each codeword, which can have one of two possible logical values (e.g., a logic 0 or a logic 1). The corresponding symbols received by the other device may comprise a parallel symbol set, and each of the differential comparison circuits may compare symbols received on pairs of the shared links. A decoder in the other device may decode a respective parallel symbol set from the outputs of the differential comparison circuits to recover the encoded data.
摘要翻译：描述通过共享链路在两个设备之间传送双向数据的系统的实施例。在该系统中，使用单端驱动器的设备之一在共享链路上发送数据，并且使用差分比较电路由另一设备在共享链路上接收对应的符号。数据可以在传输之前被编码为一系列并行码字。每个共享链路可以在可以具有两个可能的逻辑值中的一个（例如，逻辑0或逻辑1）的每个码字中传送相应的符号。由另一设备接收的对应符号可以包括并行符号集合，并且每个差分比较电路可以比较在共享链路对上接收到的符号。另一设备中的解码器可以从差分比较电路的输出解码相应的并行符号集合，以恢复编码数据。

2. 发明授权

US08588280B2 Asymmetric communication on shared links 有权
标题翻译：共享链路上的不对称通信
公开(公告)号：US08588280B2
公开(公告)日：2013-11-19
申请号：US12809000
申请日：2008-12-19
申请人： Kyung Suk Oh , John Wilson , Frederick A. Ware , WooPoung Kim , Jade M. Kizer , Brian S. Leibowitz , Lei Luo , John Cronan Eble
发明人： Kyung Suk Oh , John Wilson , Frederick A. Ware , WooPoung Kim , Jade M. Kizer , Brian S. Leibowitz , Lei Luo , John Cronan Eble
IPC分类号： H04B1/38 , H04L5/16
CPC分类号： G06F13/4243 , H04L25/4906 , Y02D10/14 , Y02D10/151
摘要： Embodiments of a system that communicates bidirectional data between two devices via shared links is described. In this system, data is transmitted on the shared links by one of the devices using single-ended drivers, and corresponding symbols are received on the shared links by the other device using differential comparison circuits. The data may be encoded as a series of parallel codewords prior to transmission. Each shared link may communicate a respective symbol in each codeword, which can have one of two possible logical values (e.g., a logic 0 or a logic 1). The corresponding symbols received by the other device may comprise a parallel symbol set, and each of the differential comparison circuits may compare symbols received on pairs of the shared links. A decoder in the other device may decode a respective parallel symbol set from the outputs of the differential comparison circuits to recover the encoded data.
摘要翻译：描述通过共享链路在两个设备之间传送双向数据的系统的实施例。在该系统中，使用单端驱动器的设备之一在共享链路上发送数据，并且使用差分比较电路由另一设备在共享链路上接收对应的符号。数据可以在传输之前被编码为一系列并行码字。每个共享链路可以在可以具有两个可能的逻辑值中的一个（例如，逻辑0或逻辑1）的每个码字中传送相应的符号。由另一设备接收的对应符号可以包括并行符号集合，并且每个差分比较电路可以比较在共享链路对上接收到的符号。另一设备中的解码器可以从差分比较电路的输出解码相应的并行符号集合，以恢复编码数据。

3. 发明授权

US08836394B2 Method and apparatus for source-synchronous signaling 有权
标题翻译：源同步信令的方法和装置
公开(公告)号：US08836394B2
公开(公告)日：2014-09-16
申请号：US13523631
申请日：2012-06-14
申请人： Jared L. Zerbe , Brian S. Leibowitz , Hsuan-Jung Su , John Cronan Eble, III , Barry William Daly , Lei Luo , Teva J. Stone , John Wilson , Jihong Ren , Wayne D. Dettloff
发明人： Jared L. Zerbe , Brian S. Leibowitz , Hsuan-Jung Su , John Cronan Eble, III , Barry William Daly , Lei Luo , Teva J. Stone , John Wilson , Jihong Ren , Wayne D. Dettloff
IPC分类号： H03L7/00 , H04L7/00 , H04L7/033 , G11C7/10
CPC分类号： H03L7/091 , G11C7/04 , G11C7/1066 , G11C7/1093 , G11C7/222 , H03L7/00 , H03L7/0802 , H03L7/099 , H04L7/0008 , H04L7/0037 , H04L7/0079 , H04L7/0087 , H04L7/033
摘要： A low-power, high-performance source-synchronous chip interface which provides rapid turn-on and facilitates high signaling rates between a transmitter and a receiver located on different chips is described in various embodiments. Some embodiments of the chip interface include, among others: a segmented “fast turn-on” bias circuit to reduce power supply ringing during the rapid power-on process; current mode logic clock buffers in a clock path of the chip interface to further reduce the effect of power supply ringing; a multiplying injection-locked oscillator (MILO) clock generator to generate higher frequency clock signals from a reference clock; a digitally controlled delay line which can be inserted in the clock path to mitigate deterministic jitter caused by the MILO clock generator; and circuits for periodically re-evaluating whether it is safe to retime transmit data signals in the reference clock domain directly with the faster clock signals.
摘要翻译：在各种实施例中描述了低功率，高性能的源同步芯片接口，其提供快速开启并且促进位于不同芯片上的发射机和接收机之间的高信令速率。芯片接口的一些实施例包括：分段的“快速接通”偏置电路，以减少快速上电过程期间的电源振铃; 电流模式逻辑时钟缓冲器在芯片接口的时钟路径中进一步降低电源振铃的影响; 乘法注入锁定振荡器（MILO）时钟发生器，用于从参考时钟产生更高频率的时钟信号; 一个数字控制延时线，可以插入到时钟通路中，以减轻由MILO时钟发生器引起的确定性抖动; 以及用于周期性地重新评估是否安全地重新计算参考时钟域中的数据信号的电路直接用较快的时钟信号。

4. 发明申请

US20130249612A1 METHOD AND APPARATUS FOR SOURCE-SYNCHRONOUS SIGNALING 有权
标题翻译：用于同源信号的方法和装置
公开(公告)号：US20130249612A1
公开(公告)日：2013-09-26
申请号：US13523631
申请日：2012-06-14
申请人： Jared L. Zerbe , Brian S. Leibowitz , Hsuan-Jung Su , John Cronan Eble, III , Barry William Daly , Lei Luo , Teva J. Stone , John Wilson , Jihong Ren , Wayne D. Dettloff
发明人： Jared L. Zerbe , Brian S. Leibowitz , Hsuan-Jung Su , John Cronan Eble, III , Barry William Daly , Lei Luo , Teva J. Stone , John Wilson , Jihong Ren , Wayne D. Dettloff
IPC分类号： H03L7/00
CPC分类号： H03L7/091 , G11C7/04 , G11C7/1066 , G11C7/1093 , G11C7/222 , H03L7/00 , H03L7/0802 , H03L7/099 , H04L7/0008 , H04L7/0037 , H04L7/0079 , H04L7/0087 , H04L7/033
摘要： A low-power, high-performance source-synchronous chip interface which provides rapid turn-on and facilitates high signaling rates between a transmitter and a receiver located on different chips is described in various embodiments. Some embodiments of the chip interface include, among others: a segmented “fast turn-on” bias circuit to reduce power supply ringing during the rapid power-on process; current mode logic clock buffers in a clock path of the chip interface to further reduce the effect of power supply ringing; a multiplying injection-locked oscillator (MILO) clock generator to generate higher frequency clock signals from a reference clock; a digitally controlled delay line which can be inserted in the clock path to mitigate deterministic jitter caused by the MILO clock generator; and circuits for periodically re-evaluating whether it is safe to retime transmit data signals in the reference clock domain directly with the faster clock signals.
摘要翻译：在各种实施例中描述了低功率，高性能的源同步芯片接口，其提供快速开启并且促进位于不同芯片上的发射机和接收机之间的高信令速率。芯片接口的一些实施例包括：分段的“快速接通”偏置电路，以减少快速上电过程期间的电源振铃; 电流模式逻辑时钟缓冲器在芯片接口的时钟路径中进一步降低电源振铃的影响; 乘法注入锁定振荡器（MILO）时钟发生器，用于从参考时钟产生更高频率的时钟信号; 一个数字控制延时线，可以插入到时钟通路中，以减轻由MILO时钟发生器引起的确定性抖动; 以及用于周期性地重新评估是否安全地重新计算参考时钟域中的数据信号的电路直接用较快的时钟信号。

5. 发明授权

US08462891B2 Error detection and offset cancellation during multi-wire communication 有权
标题翻译：多线通讯期间的错误检测和偏移消除
公开(公告)号：US08462891B2
公开(公告)日：2013-06-11
申请号：US12920806
申请日：2009-02-19
申请人： Jade M. Kizer , John Wilson , Lei Luo , Frederick Ware , Jared L. Zerbe
发明人： Jade M. Kizer , John Wilson , Lei Luo , Frederick Ware , Jared L. Zerbe
IPC分类号： H04L27/06
CPC分类号： H03M13/47 , H04L25/4919
摘要： Embodiments of a circuit are described. In this circuit, a receive circuit includes M input nodes that receive a set of M symbols on M links during a time interval, where the set of M symbols are associated with a codeword. Moreover, the receive circuit includes a decoder, coupled to the M input nodes, that determines the codeword in a code space based on the set of M symbols and that decodes the codeword to a corresponding set of N decoded symbols. Additionally, the receive circuit may include a detector that detects an imbalance in a number of instances of a first value in the set of M symbols and a number of instances of a second value in the set of M symbols, and, if an imbalance is detected, that asserts an error condition.
摘要翻译：描述电路的实施例。在该电路中，接收电路包括M个输入节点，该输入节点在时间间隔期间在M个链路上接收一组M个符号，其中该M个符号集合与码字相关联。此外，接收电路包括耦合到M个输入节点的解码器，其基于该M个符号集来确定码空间中的码字，并且将码字解码为相应的一组N个解码符号。此外，接收电路可以包括检测器，其检测M个符号集合中的第一值的多个实例中的不平衡以及M个符号集合中的第二值的实例的数量，并且如果不平衡是检测到，这会导致错误条件。

6. 发明授权

US08068357B2 Memory controller with multi-modal reference pad 有权
标题翻译：内存控制器，具有多模参考焊盘
公开(公告)号：US08068357B2
公开(公告)日：2011-11-29
申请号：US12204728
申请日：2008-09-04
申请人： Frederick Ware , John Wilson , John C. Eble, III , Jade M. Kizer , Lei Luo , John W. Poulton , Ian Shaeffer
发明人： Frederick Ware , John Wilson , John C. Eble, III , Jade M. Kizer , Lei Luo , John W. Poulton , Ian Shaeffer
IPC分类号： G11C5/06
CPC分类号： G11C5/063 , G11C5/147
摘要： A memory controller operates in two modes to support different types of memory devices. In a first mode, the memory controller distributes a dedicated reference voltage with each of a plurality of signal bundles to a corresponding plurality of memory devices. The reference voltages are conveyed using pads that are alternatively used for e.g. timing-reference signals in a second mode, so the provision for bundle-specific reference voltages need not increase the number of pads on the memory controller.
摘要翻译：存储器控制器以两种模式操作以支持不同类型的存储器件。在第一模式中，存储器控制器将具有多个信号束中的每一个的专用参考电压分配给相应的多个存储器件。参考电压使用可替换地用于例如电极的焊盘传送。定时参考信号处于第二模式，因此针对束特定参考电压的提供不需要增加存储器控制器上的焊盘数量。

7. 发明申请

US20110051854A1 ERROR DETECTION AND OFFSET CANCELLATION DURING MULTI-WIRE COMMUNICATION 有权
标题翻译：多线通信期间的错误检测和偏移消除
公开(公告)号：US20110051854A1
公开(公告)日：2011-03-03
申请号：US12920806
申请日：2009-02-19
申请人： Jade M. Kizer , John Wilson , Lei Luo , Frederick Ware , Jared L. Zerbe
发明人： Jade M. Kizer , John Wilson , Lei Luo , Frederick Ware , Jared L. Zerbe
IPC分类号： H04L27/06
CPC分类号： H03M13/47 , H04L25/4919
摘要： Embodiments of a circuit are described. In this circuit, a receive circuit includes M input nodes that receive a set of M symbols on M links during a time interval, where the set of M symbols are associated with a codeword. Moreover, the receive circuit includes a decoder, coupled to the M input nodes, that determines the codeword in a code space based on the set of M symbols and that decodes the codeword to a corresponding set of N decoded symbols. Additionally, the receive circuit may include a detector that detects an imbalance in a number of instances of a first value in the set of M symbols, and a number of instances of a second value in the set of M symbols, and, if an imbalance is detected, that asserts an error condition.
摘要翻译：描述电路的实施例。在该电路中，接收电路包括M个输入节点，该输入节点在时间间隔期间在M个链路上接收一组M个符号，其中该M个符号集合与码字相关联。此外，接收电路包括耦合到M个输入节点的解码器，其基于该M个符号集来确定码空间中的码字，并且将码字解码为相应的一组N个解码符号。另外，接收电路可以包括检测器，其检测M个符号集合中的第一值的多个实例中的不平衡，以及M个符号集合中的第二值的多个实例，以及如果不平衡被检测到，它确定了错误条件。

8. 发明申请

US20090059642A1 Memory Controller With Multi-Modal Reference Pad 有权
标题翻译：具有多模态参考电压的存储控制器
公开(公告)号：US20090059642A1
公开(公告)日：2009-03-05
申请号：US12204728
申请日：2008-09-04
申请人： Frederick Ware , John Wilson , John C. Eble, III , Jade M. Kizer , Lei Luo , John W. Poulton , Ian Shaeffer
发明人： Frederick Ware , John Wilson , John C. Eble, III , Jade M. Kizer , Lei Luo , John W. Poulton , Ian Shaeffer
IPC分类号： G11C5/06 , G11C7/00 , G11C8/00
CPC分类号： G11C5/063 , G11C5/147
摘要： A memory controller operates in two modes to support different types of memory devices. In a first mode, the memory controller distributes a dedicated reference voltage with each of a plurality of signal bundles to a corresponding plurality of memory devices. The reference voltages are conveyed using pads that are alternatively used for e.g. timing-reference signals in a second mode, so the provision for bundle-specific reference voltages need not increase the number of pads on the memory controller.
摘要翻译：存储器控制器以两种模式操作以支持不同类型的存储器件。在第一模式中，存储器控制器将具有多个信号束中的每一个的专用参考电压分配给相应的多个存储器件。参考电压使用可替换地用于例如电极的焊盘传送。定时参考信号处于第二模式，因此针对束特定参考电压的提供不需要增加存储器控制器上的焊盘数量。

9. 发明授权

US08581920B2 Utilizing masked data bits during accesses to a memory 有权
标题翻译：在访问存储器期间利用屏蔽的数据位
公开(公告)号：US08581920B2
公开(公告)日：2013-11-12
申请号：US12210104
申请日：2008-09-12
申请人： Lei Luo , Frederick A. Ware , John Wilson , Jade M. Kizer
发明人： Lei Luo , Frederick A. Ware , John Wilson , Jade M. Kizer
IPC分类号： G09G5/37 , G06T1/60
CPC分类号： G06F9/30018 , G09G5/363 , G09G5/393 , G09G2330/021 , G09G2330/06
摘要： Embodiments of an apparatus that uses unused masked data bits during an access to a memory are described. This apparatus includes a selection circuit, which selects data bits to be driven on data lines during the access to the memory. This selection circuit includes a control input that receives a data mask signal, which indicates whether a set of data bits is to be masked during the access to the memory. During the access to the memory, the selection circuit selects either the set of data bits to be driven when the data mask signal is not asserted, or an alternative set of values to be driven when the data mask signal is asserted.
摘要翻译：描述在访问存储器期间使用未使用的被屏蔽的数据位的装置的实施例。该装置包括选择电路，其选择在访问存储器期间在数据线上驱动的数据位。该选择电路包括接收数据屏蔽信号的控制输入，该数据屏蔽信号指示在访问存储器期间是否要屏蔽一组数据位。在访问存储器期间，当数据屏蔽信号未被置位时，选择电路选择要驱动的一组数据位，或者当数据屏蔽信号被断言时要选择要驱动的一组值。

10. 发明申请

US20090089557A1 UTILIZING MASKED DATA BITS DURING ACCESSES TO A MEMORY 有权
标题翻译：在存储器访问期间使用被屏蔽的数据位
公开(公告)号：US20090089557A1
公开(公告)日：2009-04-02
申请号：US12210104
申请日：2008-09-12
申请人： Lei Luo , Frederick A. Ware , John Wilson , Jade M. Kizer
发明人： Lei Luo , Frederick A. Ware , John Wilson , Jade M. Kizer
IPC分类号： G06F9/22
CPC分类号： G06F9/30018 , G09G5/363 , G09G5/393 , G09G2330/021 , G09G2330/06
摘要： Embodiments of an apparatus that uses unused masked data bits during an access to a memory are described. This apparatus includes a selection circuit, which selects data bits to be driven on data lines during the access to the memory. This selection circuit includes a control input that receives a data mask signal, which indicates whether a set of data bits is to be masked during the access to the memory. During the access to the memory, the selection circuit selects either the set of data bits to be driven when the data mask signal is not asserted, or an alternative set of values to be driven when the data mask signal is asserted.
摘要翻译：描述在访问存储器期间使用未使用的被屏蔽的数据位的装置的实施例。该装置包括选择电路，其选择在访问存储器期间在数据线上驱动的数据位。该选择电路包括接收数据屏蔽信号的控制输入，该数据屏蔽信号指示在访问存储器期间是否要屏蔽一组数据位。在访问存储器期间，当数据屏蔽信号未被置位时，选择电路选择要驱动的一组数据位，或者当数据屏蔽信号被断言时要选择要驱动的一组值。

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