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61. 发明授权

US07777306B2 Defect-free hybrid orientation technology for semiconductor devices 失效
标题翻译：半导体器件的无缺陷混合取向技术
公开(公告)号：US07777306B2
公开(公告)日：2010-08-17
申请号：US11682403
申请日：2007-03-06
申请人： Louis C. Hsu , Rajiv V. Joshi , Xu Ouyang
发明人： Louis C. Hsu , Rajiv V. Joshi , Xu Ouyang
IPC分类号： H01L29/04
CPC分类号： H01L29/045 , H01L21/823807 , H01L21/84 , H01L27/0922 , H01L27/1203 , H01L29/78 , H01L29/785 , Y10T428/12528
摘要： A semiconductor device includes a semiconductor material having two crystal orientations. The semiconductor material forms an active area of the device. A device channel is formed on the two crystal orientations, which include a first region formed in a first crystal orientation surface of the semiconductor material, and a second region formed in a second crystal orientation surface of the semiconductor material wherein the first crystal orientation surface forms an angle with the second crystal orientation surface and the device channel covers at least an intersection of the angle.
摘要翻译：半导体器件包括具有两个晶体取向的半导体材料。半导体材料形成该器件的有效区域。在两个晶体取向上形成器件沟道，其包括形成在半导体材料的第一晶体取向表面中的第一区域和形成在半导体材料的第二晶体取向表面中的第二区域，其中第一晶体取向表面形成与第二晶体取向表面和器件通道的角度至少覆盖角度的交点。

62. 发明申请

US20100201403A1 MULTI-LEVEL POWER SUPPLY SYSTEM FOR A COMPLEMENTARY METAL OXIDE SEMICONDUCTOR 审中-公开
标题翻译：用于补充金属氧化物半导体的多级电源系统
公开(公告)号：US20100201403A1
公开(公告)日：2010-08-12
申请号：US12761872
申请日：2010-04-16
申请人： Rajiv V. Joshi , Louis L. Hsu
发明人： Rajiv V. Joshi , Louis L. Hsu
IPC分类号： H03L5/00 , H02J1/10
CPC分类号： G11C11/4074 , G06F1/26 , G11C5/14 , Y10T307/305
摘要： There is provided a method that includes comparing a voltage level (Vs1) of a lower voltage supply bus to a voltage level (Vs2) of a higher voltage supply bus, and routing current from the lower voltage supply bus to the higher voltage supply bus if Vs2
摘要翻译：提供了一种方法，其包括将较低电压供应总线的电压电平（Vs1）与较高电压电源总线的电压电平（Vs2）进行比较，以及将电流从较低电压供应总线路由到较高电压供应总线，如果 Vs2

63. 发明授权

US07746709B2 Memory circuit with decoupled read and write bit lines and improved write stability 失效
标题翻译：具有解耦读和写位线的存储器电路，并提高写入稳定性
公开(公告)号：US07746709B2
公开(公告)日：2010-06-29
申请号：US12329133
申请日：2008-12-05
申请人： Rajiv V. Joshi , Jae-Joon Kim , Rahul M. Rao
发明人： Rajiv V. Joshi , Jae-Joon Kim , Rahul M. Rao
IPC分类号： G11C7/00
CPC分类号： G11C7/22 , G11C7/1045 , G11C7/12 , G11C7/18 , G11C11/412 , G11C11/413
摘要： In a memory circuit, data from all cells along a selected word line is read. Then, the read data is written back to half-selected cells and new data is written to the selected cells in the next cycle. In cases where a READ bit line (RBL) and WRITE bit line (WBL) are decoupled, RBL and WBL can be accessed simultaneously. Hence, the WRITE in the n-th cycle can be delayed to the n+1-th cycle as far as there is no data hazard such as reading data from memory before correct data are actually written to memory. As a result, there is no bandwidth loss, although the latency of the WRITE operation increases. WRITE stability issues in previous configurations with decoupled RBL and WBL are thus addressed.
摘要翻译：在存储器电路中，读取沿着所选字线的所有单元的数据。然后，将读取的数据写回到半选择的单元，并且在下一个周期中将新数据写入所选择的单元。在读取位线（RBL）和写入位线（WBL）解耦的情况下，可以同时访问RBL和WBL。因此，第n个周期中的写入可以延迟到第n + 1个周期，只要没有数据危险，例如在正确数据实际写入存储器之前从存储器读取数据。因此，尽管WRITE操作的延迟增加，但是没有带宽损失。因此，解决了具有去耦RBL和WBL的以前配置中的写稳定性问题。

64. 发明申请

US20100131259A1 IN-SITU DESIGN METHOD AND SYSTEM FOR IMPROVED MEMORY YIELD 有权
标题翻译：改进的存储器的现场设计方法和系统
公开(公告)号：US20100131259A1
公开(公告)日：2010-05-27
申请号：US12324170
申请日：2008-11-26
申请人： Rajiv V. Joshi , Rouwaida Kanj
发明人： Rajiv V. Joshi , Rouwaida Kanj
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F17/5022 , G06F2217/10 , G06F2217/12 , G11C11/412 , Y02P90/265
摘要： A system and method for designing integrated circuits includes determining a target memory module for evaluation and improvement by evaluating performance variables of the memory module. The performance variables are statistically simulated over subset combinations of variables based on pin information for the module. Sensitivities of performance on yield to the variables in the subset combinations are determined. It is then determined whether yield of the target module is acceptable, and if the yield is not acceptable, a design which includes the target module is adjusted in accordance with the sensitivities to adjust the yield.
摘要翻译：用于设计集成电路的系统和方法包括通过评估存储器模块的性能变量来确定用于评估和改进的目标存储器模块。基于模块的引脚信息，对变量的子集组合对性能变量进行统计学模拟。确定在子集合中变量对产量的收益的敏感度。然后确定目标模块的产量是否可接受，并且如果产量不可接受，则根据敏感度调整包括目标模块的设计以调整产量。

65. 发明授权

US07681628B2 Dynamic control of back gate bias in a FinFET SRAM cell 失效
标题翻译： FinFET SRAM单元中背栅极偏置的动态控制
公开(公告)号：US07681628B2
公开(公告)日：2010-03-23
申请号：US11402400
申请日：2006-04-12
申请人： Rajiv V. Joshi , Keunwoo Kim , Edward J. Nowak , Richard Q. Williams
发明人： Rajiv V. Joshi , Keunwoo Kim , Edward J. Nowak , Richard Q. Williams
IPC分类号： G11C11/00
CPC分类号： G11C11/412
摘要： The present invention provides dynamic control of back gate bias on pull-up pFETs in a FinFET SRAM cell. A method according to the present invention includes providing a bias voltage to a back gate of at least one transistor in the SRAM cell, and dynamically controlling the bias voltage based on an operational mode (e.g., Read, Half-Select, Write, Standby) of the SRAM cell.
摘要翻译：本发明提供对FinFET SRAM单元中的上拉pFET的背栅极偏置的动态控制。根据本发明的方法包括向SRAM单元中的至少一个晶体管的背栅提供偏置电压，并且基于操作模式（例如，读取，半选择，写入，待机）动态地控制偏置电压，的SRAM单元。

66. 发明申请

US20090305472A1 DEFECT-FREE HYBRID ORIENTATION TECHNOLOGY FOR SEMICONDUCTOR DEVICES 失效
标题翻译：用于半导体器件的无缺陷混合方向技术
公开(公告)号：US20090305472A1
公开(公告)日：2009-12-10
申请号：US12543630
申请日：2009-08-19
申请人： Louis C. Hsu , Rajiv V. Joshi , Xu Ouyang
发明人： Louis C. Hsu , Rajiv V. Joshi , Xu Ouyang
IPC分类号： H01L21/762
CPC分类号： H01L29/045 , H01L21/823807 , H01L21/84 , H01L27/0922 , H01L27/1203 , H01L29/78 , H01L29/785 , Y10T428/12528
摘要： A semiconductor device includes a semiconductor material having two crystal orientations. The semiconductor material forms an active area of the device. A device channel is formed on the two crystal orientations, which include a first region formed in a first crystal orientation surface of the semiconductor material, and a second region formed in a second crystal orientation surface of the semiconductor material wherein the first crystal orientation surface forms an angle with the second crystal orientation surface and the device channel covers at least an intersection of the angle.
摘要翻译：半导体器件包括具有两个晶体取向的半导体材料。半导体材料形成该器件的有效区域。在两个晶体取向上形成器件沟道，其包括形成在半导体材料的第一晶体取向表面中的第一区域和形成在半导体材料的第二晶体取向表面中的第二区域，其中第一晶体取向表面形成与第二晶体取向表面和器件通道的角度至少覆盖角度的交点。

67. 发明授权

US07551508B2 Energy efficient storage device using per-element selectable power supply voltages 失效
标题翻译：使用每元件可选电源电压的节能存储设备
公开(公告)号：US07551508B2
公开(公告)日：2009-06-23
申请号：US11941168
申请日：2007-11-16
申请人： Rajiv V. Joshi , Jente B Kuang , Rouwaida N. Kanj , Sani R. Nassif , Hung Cai Ngo
发明人： Rajiv V. Joshi , Jente B Kuang , Rouwaida N. Kanj , Sani R. Nassif , Hung Cai Ngo
IPC分类号： G11C5/14
CPC分类号： G11C11/417 , G11C5/14
摘要： An energy efficient storage device using per-element selectable power supply voltages provides energy conservation in storage devices while maintaining a particular performance level. The storage device is partitioned into multiple elements, which may be sub-arrays, rows, columns or individual storage cells. Each element has a corresponding virtual power supply rail that is provided with a selectable power supply voltage. The power supply voltage provided to the virtual power supply rail for an element is set to the minimum power supply voltage unless a higher power supply voltage is required for the element to meet performance requirements. A control cell may be provided within each element that provides a control signal that selects the power supply voltage supplied to the corresponding virtual power supply rail. The state of the cell may be set via a fuse or mask, or values may be loaded into the control cells at initialization of the storage device.
摘要翻译：使用每元件可选择的电源电压的节能存储装置在保持特定的性能水平的同时在存储装置中提供节能。存储设备被划分成多个元素，其可以是子阵列，行，列或单独的存储单元。每个元件具有相应的虚拟电源轨，其具有可选择的电源电压。提供给用于元件的虚拟电源轨的电源电压被设置为最小电源电压，除非元件满足性能要求需要更高的电源电压。可以在每个元件内提供控制单元，其提供选择提供给相应的虚拟电源轨的电源电压的控制信号。可以通过熔丝或掩模设置单元的状态，或者可以在存储设备初始化时将值加载到控制单元中。

68. 发明授权

US07515491B2 Method for evaluating leakage effects on static memory cell access time 失效
标题翻译：评估对静态存储单元访问时间的泄漏影响的方法
公开(公告)号：US07515491B2
公开(公告)日：2009-04-07
申请号：US11685905
申请日：2007-03-14
申请人： Rajiv V. Joshi , Qiuyi Ye , Anirudh Devgan
发明人： Rajiv V. Joshi , Qiuyi Ye , Anirudh Devgan
IPC分类号： G11C7/00 , G11C29/00
CPC分类号： G11C29/50 , G11C11/41 , G11C29/006 , G11C29/12005 , G11C29/24 , G11C2029/5002
摘要： A method for evaluating leakage effects on static memory cell access time provides a mechanism for raising the performance of memory arrays beyond present levels/yields. By altering the states of other static memory cells connected to the same bitline as a static memory cell under test, the effect of leakage on the access time of the cell can be observed. The leakage effects can further be observed while varying the internal symmetry of the memory cell, operating the cell and observing changes in performance caused by the asymmetric operation. The asymmetry can be introduced by splitting one or both power supply rail inputs to the cell and providing differing power supply voltages or currents to each cross-coupled stage.
摘要翻译：用于评估对静态存储器单元访问时间的泄漏影响的方法提供了一种用于提高存储器阵列的性能超过现有水平/产量的机制。通过改变与被测试的静态存储器单元连接到同一位线的其它静态存储单元的状态，可以观察到泄漏对单元访问时间的影响。可以进一步观察泄漏效应，同时改变存储器单元的内部对称性，操作电池并观察不对称操作引起的性能变化。可以通过将一个或两个电源轨输入分成单元并且向每个交叉耦合级提供不同的电源电压或电流来引入不对称性。

69. 发明授权

US07483322B2 Ring oscillator row circuit for evaluating memory cell performance 失效
标题翻译：用于评估存储单元性能的环形振荡器行电路
公开(公告)号：US07483322B2
公开(公告)日：2009-01-27
申请号：US11963794
申请日：2007-12-22
申请人： Rajiv V. Joshi , Qiuyi Ye , Yuen H. Chan , Anirudh Devgan
发明人： Rajiv V. Joshi , Qiuyi Ye , Yuen H. Chan , Anirudh Devgan
IPC分类号： G11C29/00
CPC分类号： G11C29/50 , G11C29/50012
摘要： A ring oscillator row circuit for evaluating memory cell performance provides for circuit delay and performance measurements in an actual memory circuit environment. A ring oscillator is implemented with a row of memory cells and has outputs connected to one or more bitlines along with other memory cells that are substantially identical to the ring oscillator cells. Logic may be included for providing a fully functional memory array, so that the cells other than the ring oscillator cells can be used for storage when the ring oscillator row wordlines are disabled. One or both power supply rails of individual cross-coupled inverter stages forming static memory cells used in the ring oscillator circuit may be isolated from each other in order to introduce a voltage asymmetry so that circuit asymmetry effects on delay can be evaluated.
摘要翻译：用于评估存储单元性能的环形振荡器行电路在实际的存储器电路环境中提供电路延迟和性能测量。环形振荡器用一行存储器单元实现，并且具有连接到一个或多个位线以及与环形振荡器单元基本相同的其它存储器单元的输出。可以包括用于提供完全功能的存储器阵列的逻辑，使得当环形振荡器行字线被禁用时，除了环形振荡器单元之外的单元可以用于存储。形成环形振荡器电路中使用的静态存储单元的各个交叉耦合的逆变器级的一个或两个电源轨可以彼此隔离，以引入电压不对称，从而可以评估电路不对称对延迟的影响。

70. 发明申请

US20080281570A1 Closed-Loop Modeling of Gate Leakage for Fast Simulators 有权
标题翻译：闸模泄漏闭环建模快速模拟器
公开(公告)号：US20080281570A1
公开(公告)日：2008-11-13
申请号：US11746976
申请日：2007-05-10
申请人： Rajiv V. Joshi , Rouwaida N. Kanj , Ying Liu , Sani R. Nassif , Jayakumaran Sivagnaname
发明人： Rajiv V. Joshi , Rouwaida N. Kanj , Ying Liu , Sani R. Nassif , Jayakumaran Sivagnaname
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： A method for circuit simulation using a netlist in which a first device having an unmodeled, nonlinear behavior is modified by inserting a second device which has a nonlinear response approximating the unmodeled nonlinear behavior. The first device may be for example a first transistor and the second device may be a variable current source, in particular one whose current is modeled after a floating transistor template which represents gate leakage current of the first transistor (gate-to-source or gate-to-drain). During simulation of the circuit a parameter such as a gate-to-source voltage of the second transistor is controlled to model gate leakage. The model parameters can be a function of an effective quantum mechanical oxide thickness value of a gate of the first transistor technology.
摘要翻译：一种使用网表的电路仿真方法，其中具有未建模的非线性行为的第一器件通过插入具有接近未建模的非线性行为的非线性响应的第二器件而被修改。第一器件可以是例如第一晶体管，并且第二器件可以是可变电流源，特别是其中电流在表示第一晶体管（栅极至源极或栅极 -排水）。在仿真电路期间，控制诸如第二晶体管的栅极至源极电压的参数来模拟栅极泄漏。模型参数可以是第一晶体管技术的栅极的有效量子机械氧化物厚度值的函数。

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