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1. 发明授权

US07495969B2 Techniques for improving write stability of memory with decoupled read and write bit lines 失效
标题翻译：提供具有解耦读和写位线的存储器的写入稳定性的技术
公开(公告)号：US07495969B2
公开(公告)日：2009-02-24
申请号：US11668545
申请日：2007-01-30
申请人： Rajiv V. Joshi , Jae-Joon Kim , Rahul M. Rao
发明人： Rajiv V. Joshi , Jae-Joon Kim , Rahul M. Rao
IPC分类号： G11C7/00
CPC分类号： G11C7/22 , G11C7/1045 , G11C7/12 , G11C7/18 , G11C11/412 , G11C11/413
摘要： In a memory circuit, data from all cells along a selected word line is read. Then, the read data is written back to half-selected cells and new data is written to the selected cells in the next cycle. In cases where a READ bit line (RBL) and WRITE bit line (WBL) are decoupled, RBL and WBL can be accessed simultaneously. Hence, the WRITE in the n-th cycle can be delayed to the n+1-th cycle as far as there is no data hazard such as reading data from memory before correct data are actually written to memory. As a result, there is no bandwidth loss, although the latency of the WRITE operation increases. WRITE stability issues in previous configurations with decoupled RBL and WBL are thus addressed.
摘要翻译：在存储器电路中，读取沿着所选字线的所有单元的数据。然后，将读取的数据写回到半选择的单元，并且在下一个周期中将新数据写入所选择的单元。在读取位线（RBL）和写入位线（WBL）解耦的情况下，可以同时访问RBL和WBL。因此，第n个周期中的写入可以延迟到第n + 1个周期，只要没有数据危险，例如在正确数据实际写入存储器之前从存储器读取数据。因此，尽管WRITE操作的延迟增加，但是没有带宽损失。因此，解决了具有去耦RBL和WBL的以前配置中的写稳定性问题。

2. 发明授权

US07746709B2 Memory circuit with decoupled read and write bit lines and improved write stability 失效
标题翻译：具有解耦读和写位线的存储器电路，并提高写入稳定性
公开(公告)号：US07746709B2
公开(公告)日：2010-06-29
申请号：US12329133
申请日：2008-12-05
申请人： Rajiv V. Joshi , Jae-Joon Kim , Rahul M. Rao
发明人： Rajiv V. Joshi , Jae-Joon Kim , Rahul M. Rao
IPC分类号： G11C7/00
CPC分类号： G11C7/22 , G11C7/1045 , G11C7/12 , G11C7/18 , G11C11/412 , G11C11/413
摘要： In a memory circuit, data from all cells along a selected word line is read. Then, the read data is written back to half-selected cells and new data is written to the selected cells in the next cycle. In cases where a READ bit line (RBL) and WRITE bit line (WBL) are decoupled, RBL and WBL can be accessed simultaneously. Hence, the WRITE in the n-th cycle can be delayed to the n+1-th cycle as far as there is no data hazard such as reading data from memory before correct data are actually written to memory. As a result, there is no bandwidth loss, although the latency of the WRITE operation increases. WRITE stability issues in previous configurations with decoupled RBL and WBL are thus addressed.
摘要翻译：在存储器电路中，读取沿着所选字线的所有单元的数据。然后，将读取的数据写回到半选择的单元，并且在下一个周期中将新数据写入所选择的单元。在读取位线（RBL）和写入位线（WBL）解耦的情况下，可以同时访问RBL和WBL。因此，第n个周期中的写入可以延迟到第n + 1个周期，只要没有数据危险，例如在正确数据实际写入存储器之前从存储器读取数据。因此，尽管WRITE操作的延迟增加，但是没有带宽损失。因此，解决了具有去耦RBL和WBL的以前配置中的写稳定性问题。

3. 发明申请

US20080181029A1 Techniques For Improving Write Stability Of Memory With Decoupled Read And Write Bit Lines 失效
标题翻译：提高存储器写入稳定性的技术，解耦读和写位线
公开(公告)号：US20080181029A1
公开(公告)日：2008-07-31
申请号：US11668545
申请日：2007-01-30
申请人： Rajiv V. Joshi , Jae-Joon Kim , Rahul M. Rao
发明人： Rajiv V. Joshi , Jae-Joon Kim , Rahul M. Rao
IPC分类号： G11C7/00 , G11C11/416
CPC分类号： G11C7/22 , G11C7/1045 , G11C7/12 , G11C7/18 , G11C11/412 , G11C11/413
摘要： In a memory circuit, data from all cells along a selected word line is read. Then, the read data is written back to half-selected cells and new data is written to the selected cells in the next cycle. In cases where a READ bit line (RBL) and WRITE bit line (WBL) are decoupled, RBL and WBL can be accessed simultaneously. Hence, the WRITE in the n-th cycle can be delayed to the n+1-th cycle as far as there is no data hazard such as reading data from memory before correct data are actually written to memory. As a result, there is no bandwidth loss, although the latency of the WRITE operation increases. WRITE stability issues in previous configurations with decoupled RBL and WBL are thus addressed.
摘要翻译：在存储器电路中，读取沿着所选字线的所有单元的数据。然后，将读取的数据写回到半选择的单元，并且在下一个周期中将新数据写入所选择的单元。在读取位线（RBL）和写入位线（WBL）解耦的情况下，可以同时访问RBL和WBL。因此，第n个周期中的写入可以延迟到第n + 1个周期，只要没有数据危险，例如在正确数据实际写入存储器之前从存储器读取数据。因此，尽管WRITE操作的延迟增加，但是没有带宽损失。因此，解决了具有去耦RBL和WBL的以前配置中的写稳定性问题。

4. 发明申请

US20090147592A1 Memory Circuit with Decoupled Read and Write Bit Lines and Improved Write Stability 失效
标题翻译：具有解耦读和写位线的存储器电路和改进的写稳定性
公开(公告)号：US20090147592A1
公开(公告)日：2009-06-11
申请号：US12329133
申请日：2008-12-05
申请人： Rajiv V. Joshi , Jae-Joon Kim , Rahul M. Rao
发明人： Rajiv V. Joshi , Jae-Joon Kim , Rahul M. Rao
IPC分类号： G11C7/00
CPC分类号： G11C7/22 , G11C7/1045 , G11C7/12 , G11C7/18 , G11C11/412 , G11C11/413
摘要： In a memory circuit, data from all cells along a selected word line is read. Then, the read data is written back to half-selected cells and new data is written to the selected cells in the next cycle. In cases where a READ bit line (RBL) and WRITE bit line (WBL) are decoupled, RBL and WBL can be accessed simultaneously. Hence, the WRITE in the n-th cycle can be delayed to the n+1-th cycle as far as there is no data hazard such as reading data from memory before correct data are actually written to memory. As a result, there is no bandwidth loss, although the latency of the WRITE operation increases. WRITE stability issues in previous configurations with decoupled RBL and WBL are thus addressed.
摘要翻译：在存储器电路中，读取沿着所选字线的所有单元的数据。然后，将读取的数据写回到半选择的单元，并且在下一个周期中将新数据写入所选择的单元。在读取位线（RBL）和写入位线（WBL）解耦的情况下，可以同时访问RBL和WBL。因此，第n个周期中的写入可以延迟到第n + 1个周期，只要没有数据危险，例如在正确数据实际写入存储器之前从存储器读取数据。因此，尽管WRITE操作的延迟增加，但是没有带宽损失。因此，解决了具有去耦RBL和WBL的以前配置中的写稳定性问题。

5. 发明授权

US06789099B2 Sense-amp based adder with source follower evaluation tree 有权
公开(公告)号：US06789099B2
公开(公告)日：2004-09-07
申请号：US10167170
申请日：2002-06-10
申请人： Jae-Joon Kim , Ching-Te K. Chuang , Rajiv V. Joshi , Kaushik Roy
发明人： Jae-Joon Kim , Ching-Te K. Chuang , Rajiv V. Joshi , Kaushik Roy
IPC分类号： G06F750
CPC分类号： G06F7/508 , G06F7/503 , G06F7/507 , G06F2207/3872 , G06F2207/4814
摘要： A 64-bit adder implemented in partially depleted silicon on insulator technology and having two levels of lookahead uses a dynamic eight-bit carry module containing a cascode evaluation tree employing a chain of source followers that feeds a sense amplifier, thereby obtaining benefits from high initial drive, low variation in body voltage, resulting in low variation in history-dependent delay, reduced noise sensitivity and noise-based delay.

6. 发明授权

US07085798B2 Sense-amp based adder with source follower pass gate evaluation tree 失效
公开(公告)号：US07085798B2
公开(公告)日：2006-08-01
申请号：US10167276
申请日：2002-06-10
申请人： Jae-Joon Kim , Ching-Te K. Chuang , Rajiv V. Joshi , Kaushik Roy
发明人： Jae-Joon Kim , Ching-Te K. Chuang , Rajiv V. Joshi , Kaushik Roy
IPC分类号： G06F7/50
CPC分类号： G06F7/508
摘要： A 64-bit adder implemented in partially depleted silicon on insulator technology and having two levels of lookahead uses a dynamic eight-bit carry module containing a differential pass-gate evaluation tree employing a chain of source followers that feeds a sense amplifier, thereby obtaining benefits from high initial drive, low variation in body voltage, resulting in low variation in history-dependent delay, reduced noise sensitivity and noise-based delay.

7. 发明授权

US08767501B2 Self-reconfigurable address decoder for associative index extended caches 有权
标题翻译：用于关联索引扩展缓存的自重配置地址解码器
公开(公告)号：US08767501B2
公开(公告)日：2014-07-01
申请号：US13550762
申请日：2012-07-17
申请人： Rajiv V. Joshi , Ajay N. Bhoj
发明人： Rajiv V. Joshi , Ajay N. Bhoj
IPC分类号： G11C8/10
CPC分类号： G06F12/0864 , G06F2212/1021 , G11C15/04
摘要： Associative index extended (AIX) caches can be functionally implemented through a reconfigurable decoder that employs programmable line decoding. The reconfigurable decoder features scalability in the number of lines, the number of index extension bits, and the number of banks. The reconfigurable decoder can switch between pure direct mapped (DM) mode and direct mapped-associative index extended (DM-AIX) mode of operation. For banked configurations, the reconfigurable decoder provides the ability to run some banks in DM mode and some other banks in DM-AIX mode. A cache employing this reconfigurable decoder can provide a comparable level of latency as a DM cache with minimal modifications to a DM cache circuitry of an additional logic circuit on a critical signal path, while providing low power operation at low area overhead with SA cache-like miss rates. Address masking and most-recently-used-save replacement policy can be employed with a single bit overhead per line.
摘要翻译：关联索引扩展（AIX）缓存可以通过采用可编程线解码的可重构解码器进行功能实现。可重配置解码器具有线路数量的可扩展性，索引扩展位的数量和存储体的数量。可重构解码器可以在纯直接映射（DM）模式和直接映射关联索引扩展（DM-AIX）操作模式之间切换。对于组合配置，可重构解码器能够以DM模式运行某些存储区，并以DM-AIX模式运行其他存储区。采用该可重构解码器的高速缓存器可以提供与DM高速缓存相当的延迟水平，对关键信号路径上的附加逻辑电路的DM高速缓存电路进行最小修改，同时在低区域开销提供具有SA缓存类似的低功率操作错过率。地址掩码和最近使用的保存替换策略可以采用每行一个位开销。

8. 发明授权

US08578316B1 Methodologies for automatic 3-D device structure synthesis from circuit layouts for device simulation 有权
公开(公告)号：US08578316B1
公开(公告)日：2013-11-05
申请号：US13607678
申请日：2012-09-08
申请人： Rajiv V. Joshi , Ajay N. Bhoj
发明人： Rajiv V. Joshi , Ajay N. Bhoj
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F17/5018
摘要： A method of automatically generating structure files employing a full structure generator automated program is provided. An annotated device layout file is generated from a design layout by annotating the codes for design shapes with additional text representing the functionality of a physical structure associated with each design shape. Functioning individual semiconductor devices are identified from the annotated device layout file, and a circuit area including multiple interconnected semiconductor devices are identified. A front-end-of-line (FEOL) device structure file and a back-end-of-line (BEOL) device structure file are generated from layer by layer analysis of the components of the annotated device layout within the circuit area. Finite element meshes (FEMs) are generated for the FEOL and BEOL structure files and merged to provide a structure file that can be employed for simulation of semiconductor devices therein.

9. 发明申请

US20130289965A1 FET-BOUNDING FOR FAST TCAD-BASED VARIATION MODELING 有权
公开(公告)号：US20130289965A1
公开(公告)日：2013-10-31
申请号：US13457722
申请日：2012-04-27
申请人： Rajiv V. Joshi , Rouwaida N. Kanj , Keunwoo Kim
发明人： Rajiv V. Joshi , Rouwaida N. Kanj , Keunwoo Kim
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/10
摘要： A method for analyzing circuits includes identifying one or more device zones in a full device structure. The device zones provide areas of interest to be analyzed. A partial device is generated that representatively includes the one or more device zones. Analytical meshes of the partial device are reduced by employing physical characteristics of the full device structure. The partial device is simulated, using a processor, to obtain device output information in the areas of interest that is representative of the full device structure. Systems are also disclosed.

10. 发明申请

US20130289948A1 FET-BOUNDING FOR FAST TCAD-BASED VARIATION MODELING 有权
标题翻译：基于快速TCAD变换建模的场效应晶体管
公开(公告)号：US20130289948A1
公开(公告)日：2013-10-31
申请号：US13611359
申请日：2012-09-12
申请人： Rajiv V. Joshi , Rouwaida N. Kanj , Keunwoo Kim
发明人： Rajiv V. Joshi , Rouwaida N. Kanj , Keunwoo Kim
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/10
摘要： A method for analyzing circuits includes identifying one or more device zones in a full device structure. The device zones provide areas of interest to be analyzed. A partial device is generated that representatively includes the one or more device zones. Analytical meshes of the partial device are reduced by employing physical characteristics of the full device structure. The partial device is simulated, using a processor, to obtain device output information in the areas of interest that is representative of the full device structure. Systems are also disclosed.
摘要翻译：一种用于分析电路的方法包括识别完整设备结构中的一个或多个设备区域。设备区域提供要分析的感兴趣区域。生成代表性地包括一个或多个设备区域的部分设备。通过采用整个装置结构的物理特性来减少部分装置的分析网格。使用处理器来模拟部分设备，以获得代表整个设备结构的感兴趣区域中的设备输出信息。还披露了系统。

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