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61. 发明授权

US08049224B2 Process for transferring a layer of strained semiconductor material 有权
标题翻译：用于转移应变半导体材料层的工艺
公开(公告)号：US08049224B2
公开(公告)日：2011-11-01
申请号：US12862471
申请日：2010-08-24
申请人： Bruno Ghyselen , Daniel Bensahel , Thomas Skotnicki
发明人： Bruno Ghyselen , Daniel Bensahel , Thomas Skotnicki
IPC分类号： H01L29/12
CPC分类号： H01L29/1054 , H01L21/76254 , H01L21/76259 , Y10S438/938
摘要： Semiconductor wafers having a thin layer of strained semiconductor material. These structures include a substrate; an oxide layer upon the substrate; a silicon carbide (SiC) layer upon the oxide layer, and a strained layer of a semiconductor material in a strained state upon the silicon carbide layer, or a matching layer upon the donor substrate that is made from a material that induces strain in subsequent epitaxially grown layers thereon; a strained layer of a semiconductor material of defined thickness in a strained state; and an insulating or semi-insulating layer upon the strained layer in a thickness that retains the strained state of the strained layer. The insulating or semi-insulating layers are made of silicon carbide or oxides and act to retain strain in the strained layer.
摘要翻译：半导体晶片具有应变半导体材料的薄层。这些结构包括底物; 基底上的氧化物层; 氧化物层上的碳化硅（SiC）层，以及在碳化硅层上处于应变状态的半导体材料的应变层，或者由施主衬底上的由随后的外延生长引起应变的材料制成的匹配层生长层; 在应变状态下具有规定厚度的半导体材料的应变层; 以及在应变层上的绝缘或半绝缘层，其厚度保持应变层的应变状态。绝缘层或半绝缘层由碳化硅或氧化物制成并用于将应变保留在应变层中。

62. 发明申请

US20110115237A1 THERMOELECTRIC GENERATOR 有权
标题翻译：热电发生器
公开(公告)号：US20110115237A1
公开(公告)日：2011-05-19
申请号：US12902355
申请日：2010-10-12
申请人： Thomas Skotnicki
发明人： Thomas Skotnicki
IPC分类号： H02K7/18
CPC分类号： F03G7/06 , H02N10/00 , Y02T10/166
摘要： A thermoelectric generator including a membrane maintained by lateral ends and capable of taking a first shape when its temperature reaches a first threshold and a second shape when its temperature reaches a second threshold greater than the first threshold; at least one electrically conductive element attached to with the membrane and connecting the lateral ends of the membrane; and circuitry capable of generating, at the level of the membrane, a magnetic field orthogonal to the membrane displacement direction, the lateral ends of the membrane being connected to output terminals of the generator.
摘要翻译：一种热电发电机，其包括由横向端部保持的膜，当其温度达到第一阈值时，当其温度达到大于第一阈值的第二阈值时能够获得第一形状; 至少一个导电元件与膜连接并连接膜的侧端; 以及能够在膜的水平处产生与膜移位方向正交的磁场的电路，膜的横向端部连接到发生器的输出端子。

63. 再颁专利

USRE41841E1 Method for making a silicon substrate comprising a buried thin silicon oxide film 有权
标题翻译：一种用于制造包含掩埋的薄氧化硅膜的硅衬底的方法
公开(公告)号：USRE41841E1
公开(公告)日：2010-10-19
申请号：US11208132
申请日：2000-06-08
申请人： Malgorzata Jurczak , Thomas Skotnicki
发明人： Malgorzata Jurczak , Thomas Skotnicki
IPC分类号： H01L21/30
CPC分类号： H01L21/76251
摘要： A method for making a silicon substrate having a buried thin silicon oxide film is described. The method consists of: a) producing a first element having a first silicon body whereof the main surface is coated, in succession, with a buffer layer of germanium, or of an alloy of germanium and silicon, and with a thin silicon film; b) producing a second element, having a silicon body whereof a main surface is coated with a thin silicon oxide film; c) linking the first element with the second element such that the thin silicon film of the first element is in contact with the thin silicon oxide film of the second element; and d) eliminating the buffer layer to recuperate the silicon substrate having a buried thin silicon oxide film and a reusable silicon substrate. The method may be useful in making microelectronic devices such as CMOS and MOSFET devices.
摘要翻译：描述了制造具有掩埋的薄氧化硅膜的硅衬底的方法。该方法包括：a）制备具有第一硅体的第一元件，该第一硅体的主表面依次用锗的缓冲层或锗和硅的合金以及薄的硅膜涂覆; b）制造具有硅主体的第二元件，主体表面涂覆有薄的氧化硅膜; c）将第一元件与第二元件连接，使得第一元件的薄硅膜与第二元件的薄氧化硅膜接触; 以及d）消除缓冲层以恢复具有掩埋的薄氧化硅膜和可重复使用的硅衬底的硅衬底。该方法可用于制造诸如CMOS和MOSFET器件的微电子器件。

64. 再颁专利

USRE41764E1 Semiconductor device with compensated threshold voltage and method for making same 有权
标题翻译：具有补偿阈值电压的半导体器件及其制造方法
公开(公告)号：USRE41764E1
公开(公告)日：2010-09-28
申请号：US11318397
申请日：2000-06-05
申请人： Thomas Skotnicki , Romain Gwoziecki
发明人： Thomas Skotnicki , Romain Gwoziecki
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/66575 , H01L21/2253 , H01L21/26586 , H01L29/1041
摘要： A semiconductor device may include a channel region formed between a source and a drain region. One or more first pockets may be formed in the channel region adjacent to junctions. The first pockets may be doped with a dopant of the first conductivity type. At least one second pocket may be formed adjacent to each of the junctions and stacked against each of the first pockets. The second pocket may be doped with a dopant of a second conductivity type such that the dopant concentration in the second pocket is less than the dopant concentration in the first pockets. The second pocket may reduce a local substrate concentration without changing the conductivity type of the channel region.
摘要翻译：半导体器件可以包括形成在源区和漏区之间的沟道区。一个或多个第一凹穴可以形成在邻近结的通道区域中。第一个袋可以掺杂有第一导电类型的掺杂剂。至少一个第二袋可以邻近每个接合点形成并且堆叠在每个第一袋上。第二袋可以掺杂有第二导电类型的掺杂剂，使得第二袋中的掺杂剂浓度小于第一袋中的掺杂剂浓度。第二个袋可以减少局部衬底浓度而不改变沟道区的导电类型。

65. 发明授权

US07608867B2 Vertical IMOS transistor having a PIN diode formed within 有权
标题翻译：具有PIN二极管形成的垂直IMOS晶体管
公开(公告)号：US07608867B2
公开(公告)日：2009-10-27
申请号：US11393616
申请日：2006-03-30
申请人： Clément Charbuillet , Thomas Skotnicki , Alexandre Villaret
发明人： Clément Charbuillet , Thomas Skotnicki , Alexandre Villaret
IPC分类号： H01L29/94 , H01L29/868
CPC分类号： H01L29/868 , H01L29/7391
摘要： A vertical IMOS-type transistor including: a stack of a first semiconductor portion doped with dopant elements of a first type, of a second substantially undoped intrinsic semiconductor portion, and of a third semiconductor portion doped with dopant elements of a second type forming a PIN-type diode; and a conductive gate placed against the stack with an interposed insulating layer.
摘要翻译：一种垂直IMOS型晶体管，包括：第一半导体部分的堆叠，掺杂有第一类型的掺杂元素，第二基本上未掺杂的本征半导体部分，以及掺杂有形成PIN的第二类型的掺杂元素的第三半导体部分型二极管; 以及通过插入的绝缘层抵靠堆叠放置的导电栅极。

66. 发明申请

US20080164492A1 PROCESS FOR TRANSFERRING A LAYER OF STRAINED SEMICONDUCTOR MATERIAL 有权
标题翻译：用于传输应变半导体材料层的方法
公开(公告)号：US20080164492A1
公开(公告)日：2008-07-10
申请号：US12040134
申请日：2008-02-29
申请人： Bruno Ghyselen , Daniel Bensahel , Thomas Skotnicki
发明人： Bruno Ghyselen , Daniel Bensahel , Thomas Skotnicki
IPC分类号： H01L29/04 , H01L21/18
CPC分类号： H01L29/1054 , H01L21/76254 , H01L21/76259 , Y10S438/938
摘要： A process for preparing a semiconductor wafer with a strained layer having an elevated critical thickness. A first wafer having a strained layer of a semiconductor material on a matching layer is provided, with the semiconductor material having a first lattice parameter corresponding to a relaxed state and a first critical thickness corresponding to the first strained state, and the first thickness is less than the first critical thickness, The matching layer has a matching lattice parameter that is sufficiently different than the first lattice parameter to retain the strained layer in the strained state, The strained layer is transferred to a receiving substrate selected to provide the transferred strained layer with a second critical thickness that is greater than the first critical thickness, and additional semiconductor material is grown on the transferred strained layer to provide a second thickness that is greater than the first critical thickness and less than the second critical thickness, The invention also relates to the semiconductor structures that can be produced by the process.
摘要翻译：一种制备具有临界厚度升高的应变层的半导体晶片的方法。提供了在匹配层上具有半导体材料应变层的第一晶片，半导体材料具有对应于松弛状态的第一晶格参数和对应于第一应变状态的第一临界厚度，并且第一厚度较小匹配层具有与第一晶格参数充分不同的匹配晶格参数，以将应变层保持在应变状态。应变层被转移到选择的接收衬底以提供转移的应变层，第二临界厚度大于第一临界厚度，并且附加的半导体材料在转移的应变层上生长以提供大于第一临界厚度并小于第二临界厚度的第二厚度。本发明还涉及可以通过该方法生产的半导体结构。

67. 发明授权

US06989570B2 Strained-channel isolated-gate field effect transistor, process for making same and resulting integrated circuit 有权
标题翻译：应变通道隔离栅场效应晶体管，制造相同的集成电路的过程
公开(公告)号：US06989570B2
公开(公告)日：2006-01-24
申请号：US10405075
申请日：2003-03-31
申请人： Thomas Skotnicki , Daniel Bensahel
发明人： Thomas Skotnicki , Daniel Bensahel
IPC分类号： H01L27/12
CPC分类号： H01L29/66651 , H01L29/0649 , H01L29/41783 , H01L29/66772 , H01L29/7842 , H01L29/78618 , H01L29/78639 , H01L29/78687
摘要： A transistor is located on a base layer 1 resting on a semiconductor substrate SB and formed from a relaxed silicon-germanium layer, and includes, under the isolated gate 7, a first strained silicon layer 2 resting on the base layer 1, surmounted by a buried insulating layer 10, surmounted by a second strained silicon layer 4 extending between the source S and drain D regions.
摘要翻译：晶体管位于沉积在半导体衬底SB上的基底层1上并由松弛的硅 - 锗层形成，并且在隔离栅极7下方包括搁置在基底层1上的第一应变硅层2，掩埋绝缘层10，其由在源极S和漏极D区域之间延伸的第二应变硅层4所覆盖。

68. 发明申请

US20060001113A1 Magnetic sensor of very high sensitivity 有权
标题翻译：磁传感器灵敏度非常高
公开(公告)号：US20060001113A1
公开(公告)日：2006-01-05
申请号：US11214248
申请日：2005-08-29
申请人： Herve Jaouen , Thomas Skotnicki , Malgorzata Jurczak
发明人： Herve Jaouen , Thomas Skotnicki , Malgorzata Jurczak
IPC分类号： H01L27/14 , H01L21/00
CPC分类号： G10K9/13 , G01D5/242 , G01L9/0042 , Y10T428/1157 , Y10T428/1171 , Y10T428/19
摘要： A magnetic sensor includes a thin deformable membrane made of a conductive material forming a first plate of a capacitor which conducts an electric current therethrough. A second capacitor plate of the capacitor includes a doped region of a semiconductor substrate. A layer of a gaseous dielectric separates the two plates. The membrane deforms due to the effect of the Lorentz force generated by a magnetic field lying in the plane of the membrane and perpendicular to the lines of current being conducted therethrough. In addition, a process for fabricating this magnetic sensor is also provided as well as a device for measuring a magnetic field using the magnetic sensor.
摘要翻译：磁传感器包括由导电材料制成的薄的可变形膜，该导电材料形成电容器的第一板，其导通电流。电容器的第二电容器板包括半导体衬底的掺杂区域。气体介质层分离两个板。由于由位于膜的平面中的磁场产生的洛伦兹力的作用并且垂直于通过其传导的电流线，膜变形。此外，还提供了用于制造该磁传感器的工艺以及使用该磁传感器来测量磁场的装置。

69. 发明申请

US20050079695A1 Process for fabricating a transistor with a metal gate, and corresponding transistor 审中-公开
标题翻译：用金属栅极制造晶体管的工艺及相应的晶体管
公开(公告)号：US20050079695A1
公开(公告)日：2005-04-14
申请号：US10809942
申请日：2004-03-25
申请人： Nicolas Carriere , Thomas Skotnicki , Brice Tavel
发明人： Nicolas Carriere , Thomas Skotnicki , Brice Tavel
IPC分类号： H01L21/28 , H01L21/336 , H01L29/49 , H01L21/3205
CPC分类号： H01L29/66507 , H01L21/28097 , H01L21/28123 , H01L29/4975 , H01L29/66545
摘要： A phase of siliciding a transistor includes formation, from a first metal (8), of a first metal silicide (80) on the drain and source regions, while the gate region (30) is protected by a layer of hard mask (40), removal of the hard mask, formation, from a second metal (9), of a second metal silicide (90) on the gate region, while the first metal silicide (80) is protected by the second metal (9), and removal of the second metal (9).
摘要翻译：晶体管的硅化阶段包括在漏极和源极区域上从第一金属（8）形成第一金属硅化物（80），而栅极区域（30）由硬掩模（40）层保护，在所述第一金属硅化物（80）被所述第二金属（9）保护的同时从所述栅极区域上的第二金属硅化物（90）的第二金属（9）去除所述硬掩模，以及去除的第二金属（9）。

70. 发明授权

US06861684B2 Method of fabricating a vertical insulated gate transistor with low overlap of the gate on the source and the drain, and an integrated circuit including this kind of transistor 有权
标题翻译：制造在源极和漏极上的栅极的低重叠的垂直绝缘栅极晶体管的方法，以及包括这种晶体管的集成电路
公开(公告)号：US06861684B2
公开(公告)日：2005-03-01
申请号：US10114329
申请日：2002-04-02
申请人： Thomas Skotnicki , Emmanuel Josse
发明人： Thomas Skotnicki , Emmanuel Josse
IPC分类号： H01L21/28 , H01L21/336 , H01L29/423 , H01L29/49 , H01L29/78 , H01L29/76
CPC分类号： H01L29/66666 , H01L21/2807 , H01L21/2815 , H01L29/42368 , H01L29/42376 , H01L29/49 , H01L29/7827
摘要： The vertical transistor includes, on a semiconductor substrate, a vertical pillar 5 having one of the source and drain regions at the top, the other of the source and drain regions being situated in the substrate at the periphery of the pillar, a gate dielectric layer 7 situated on the flanks of the pillar and on the top surface of the substrate, and a semiconductor gate resting on the gate dielectric layer. The gate includes a semiconductor block having a first region 800 resting on the gate dielectric layer 7 and a second region 90 facing at least portions of the source and drain regions and separated from those source and drain region portions by dielectric cavities 14S, 14D.
摘要翻译：垂直晶体管在半导体衬底上包括在顶部具有源极和漏极区中的一个的垂直柱5，源极和漏极区中的另一个位于柱的外围的衬底中，栅极介电层 7位于柱的侧面和基板的顶表面上，以及位于栅极介电层上的半导体栅极。栅极包括具有搁置在栅极电介质层7上的第一区域800的半导体块和面向源极和漏极区域的至少部分的第二区域90，并且通过电介质腔14S，14D与那些源极和漏极区域分离。

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