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1. 发明授权

US07224015B1 Method for making a stack of capacitors, in particular for dynamic random access memory [DRAM] 有权
标题翻译：制造电容器堆叠的方法，特别是用于动态随机存取存储器[DRAM]
公开(公告)号：US07224015B1
公开(公告)日：2007-05-29
申请号：US10129881
申请日：2000-11-10
申请人： Thomas Skotnicki , Malgorzata Jurczak , Catherine Mallardeau
发明人： Thomas Skotnicki , Malgorzata Jurczak , Catherine Mallardeau
IPC分类号： H01L27/108
CPC分类号： H01L27/10852 , H01L27/10817 , H01L28/60
摘要： The invention concerns a method which consists in forming on a substrate (1) coated with a dielectric material layer (3) provided with a window (3a), a stack of successive layers alternately of germanium or SiGe alloy (4, 6, 8) and polycrystalline silicon (5, 7, 9); selective partial elimination of the germanium or SiGe alloy layers, to form an tree-like structure; forming a thin layer of dielectric material (10) on the tree-like structure; and coating the tree-like structure with polycrystalline silicon (11). The invention is useful for making dynamic random-access memories.
摘要翻译：本发明涉及一种方法，该方法包括在涂覆有设置有窗口（3a）的介电材料层（3）的基底（1）上，交替地具有锗或SiGe合金（4,6,8 ）和多晶硅（5,7,9）; 选择性地部分消除锗或SiGe合金层，形成树状结构; 在树状结构上形成介电材料薄层（10）; 并用多晶硅（11）涂覆树状结构。本发明对于制作动态随机存取存储器是有用的。

2. 发明授权

US06727186B1 Method for lateral etching with holes for making semiconductor devices 失效
标题翻译：用于半导体器件的用于横向蚀刻孔的方法
公开(公告)号：US06727186B1
公开(公告)日：2004-04-27
申请号：US10019340
申请日：2002-04-15
申请人： Thomas Skotnicki , Malgorzata Jurczak
发明人： Thomas Skotnicki , Malgorzata Jurczak
IPC分类号： H01L2100
CPC分类号： H01L29/513 , H01L21/28167 , H01L21/7624 , H01L29/0649 , H01L29/515 , H01L29/66772 , H01L29/78603 , H01L29/78654
摘要： A method of fabricating an SON structure semiconductor device is described. There is formed, on a silicon substrate, a stack of layers comprising first and second successive combinations. Each successive combination has a bottom silicon-germanium alloy (Site) layer and a top silicon layer. In a conventional way, a gate dielectric layer, a gate, spacers, source and drain regions, and an external passivating layer are formed by ionic implantation. A vertical hole is formed in the gate as far as the bottom Site layer to etch a part of the Site layers to form tunnels. The walls of the hole and the tunnels are then internally passivated so that the tunnels can remain empty or be filled.
摘要翻译：描述了制造SON结构半导体器件的方法。在硅衬底上形成包括第一和第二连续组合的一叠层。每个连续组合具有底部硅 - 锗合金（场）层和顶部硅层。以常规方式，通过离子注入形成栅介电层，栅极，间隔物，源极和漏极区域以及外部钝化层。在栅极中形成垂直孔至底部位置层，以蚀刻部分位点层以形成隧道。然后将洞内的隧道和隧道内部钝化，以使隧道保持空闲或被填满。

3. 发明授权

US06607968B1 Method for making a silicon substrate comprising a buried thin silicon oxide film 有权
标题翻译：一种用于制造包含掩埋的薄氧化硅膜的硅衬底的方法
公开(公告)号：US06607968B1
公开(公告)日：2003-08-19
申请号：US10018680
申请日：2002-04-22
申请人： Malgorzata Jurczak , Thomas Skotnicki
发明人： Malgorzata Jurczak , Thomas Skotnicki
IPC分类号： H01L2130
CPC分类号： H01L21/76251
摘要： A method for making a silicon substrate having a buried thin silicon oxide film is described. The method consists of: a) producing a first element having a first silicon body whereof the main surface is coated, in succession, with a buffer layer of germanium, or of an alloy of germanium and silicon, and with a thin silicon film; b) producing a second element, having a silicon body whereof a main surface is coated with a thin silicon oxide film; c) linking the first element with the second element such that the thin silicon film of the first element is in contact with the thin silicon oxide film of the second element; and d) eliminating the buffer layer to recuperate the silicon substrate having a buried thin silicon oxide film and a reusable silicon substrate. The method may be useful in making microelectronic devices such as CMOS and MOSFET devices.
摘要翻译：描述了制造具有掩埋的薄氧化硅膜的硅衬底的方法。该方法包括：a）制备具有第一硅体的第一元件，该第一硅体的主表面依次用锗的缓冲层或锗和硅的合金以及薄的硅膜涂覆; b）制造具有硅主体的第二元件，主体表面涂覆有薄的氧化硅膜; c）将第一元件与第二元件连接，使得第一元件的薄硅膜与第二元件的薄氧化硅膜接触; 以及d）消除缓冲层以恢复具有掩埋的薄氧化硅膜和可重复使用的硅衬底的硅衬底。该方法可用于制造诸如CMOS和MOSFET器件的微电子器件。

4. 发明授权

US06583451B2 Process for fabricating a network of nanometric lines made of single-crystal silicon and device obtained 有权
标题翻译：制造由单晶硅制成的纳米线网络的方法和所获得的器件
公开(公告)号：US06583451B2
公开(公告)日：2003-06-24
申请号：US09738870
申请日：2000-12-15
申请人： Thomas Skotnicki , Malgorzata Jurczak , Didier Dutartre
发明人： Thomas Skotnicki , Malgorzata Jurczak , Didier Dutartre
IPC分类号： H01L3300
CPC分类号： H01L29/0665 , B82Y10/00 , H01L21/02381 , H01L21/02447 , H01L21/0245 , H01L21/02507 , H01L21/02529 , H01L21/02532 , H01L21/02639 , H01L21/02647 , H01L21/76262 , H01L29/0673 , H01L29/0676
摘要： The process for fabricating a network of nanometric lines made of single-crystal silicon on an isolating substrate includes the production of a substrate comprising a silicon body having a lateral isolation defining a central part in the body. A recess is formed in the central part having a bottom wall made of dielectric material, a first pair of opposed parallel sidewalls made of dielectric material, and a second pair of opposed parallel sidewalls. At least one of the opposed parallel sidewalls of the second pair being formed from single-crystal silicon. The method further includes the epitaxial growth in the recess, from the sidewall made of single-crystal silicon of the recess, of an alternating network of parallel lines made of single-crystal SiGe alloy and of single-crystal silicon. Also, the lines made of single-crystal SiGe alloy are etched to form in the recess a network of parallel lines made of single-crystal silicon insulated from each other.
摘要翻译：用于在隔离衬底上制造由单晶硅制成的纳米线网络的工艺包括制备包含限定主体中心部分的侧向隔离的硅体的衬底。在具有由电介质材料制成的底壁的中心部分形成凹部，由电介质材料制成的第一对相对的平行侧壁和第二对相对的平行侧壁。第二对的相对的平行侧壁中的至少一个由单晶硅形成。该方法还包括从由凹槽的单晶硅制成的侧壁，由单晶SiGe合金和单晶硅制成的平行线的交替网络的凹槽中的外延生长。此外，由单晶SiGe合金制成的线被蚀刻以在凹槽中形成由彼此绝缘的单晶硅硅制成的平行线的网络。

5. 发明授权

US07038285B2 Very high sensitivity magnetic sensor 有权
标题翻译：非常高灵敏度的磁传感器
公开(公告)号：US07038285B2
公开(公告)日：2006-05-02
申请号：US10149093
申请日：2000-12-06
申请人： Hervé Jaouen , Thomas Skotnicki , Malgorzata Jurczak
发明人： Hervé Jaouen , Thomas Skotnicki , Malgorzata Jurczak
IPC分类号： H01L29/82
CPC分类号： G10K9/13 , G01D5/242 , G01L9/0042 , Y10T428/1157 , Y10T428/1171 , Y10T428/19
摘要： A magnetic sensor includes a thin deformable membrane made of a conductive material forming a first plate of a capacitor which conducts an electric current therethrough. A second capacitor plate of the capacitor includes a doped region of a semiconductor substrate. A layer of a gaseous dielectric separates the two plates. The membrane deforms due to the effect of the Lorentz force generated by a magnetic field lying in the plane of the membrane and perpendicular to the lines of current being conducted therethrough. In addition, a process for fabricating this magnetic sensor is also provided as well as a device for measuring a magnetic field using the magnetic sensor.
摘要翻译：磁传感器包括由导电材料制成的薄的可变形膜，该导电材料形成电容器的第一板，其导通电流。电容器的第二电容器板包括半导体衬底的掺杂区域。气体介质层分离两个板。由于由位于膜的平面中的磁场产生的洛伦兹力的作用并且垂直于通过其传导的电流线，膜变形。此外，还提供了用于制造该磁传感器的工艺以及使用该磁传感器来测量磁场的装置。

6. 发明授权

US07396736B2 Magnetic sensor of very high sensitivity 有权
标题翻译：磁传感器灵敏度非常高
公开(公告)号：US07396736B2
公开(公告)日：2008-07-08
申请号：US11214248
申请日：2005-08-29
申请人： Hervé Jaouen , Thomas Skotnicki , Malgorzata Jurczak
发明人： Hervé Jaouen , Thomas Skotnicki , Malgorzata Jurczak
IPC分类号： H01L29/82
CPC分类号： G10K9/13 , G01D5/242 , G01L9/0042 , Y10T428/1157 , Y10T428/1171 , Y10T428/19
摘要： A magnetic sensor includes a thin deformable membrane made of a conductive material forming a first plate of a capacitor which conducts an electric current therethrough. A second capacitor plate of the capacitor includes a doped region of a semiconductor substrate. A layer of a gaseous dielectric separates the two plates. The membrane deforms due to the effect of the Lorentz force generated by a magnetic field lying in the plane of the membrane and perpendicular to the lines of current being conducted therethrough. In addition, a process for fabricating this magnetic sensor is also provided as well as a device for measuring a magnetic field using the magnetic sensor.
摘要翻译：磁传感器包括由导电材料制成的薄的可变形膜，该导电材料形成电容器的第一板，其导通电流。电容器的第二电容器板包括半导体衬底的掺杂区域。气体介质层分离两个板。由于由位于膜的平面中的磁场产生的洛伦兹力的作用并且垂直于通过其传导的电流线，膜变形。此外，还提供了用于制造该磁传感器的工艺以及使用该磁传感器来测量磁场的装置。

7. 发明授权

US06555482B2 Process for fabricating a MOS transistor having two gates, one of which is buried and corresponding transistor 有权
标题翻译：用于制造具有两个栅极的MOS晶体管的工艺，其中一个栅极被埋入并且对应的晶体管
公开(公告)号：US06555482B2
公开(公告)日：2003-04-29
申请号：US09812717
申请日：2001-03-20
申请人： Thomas Skotnicki , Malgorzata Jurczak , Michel Haond
发明人： Thomas Skotnicki , Malgorzata Jurczak , Michel Haond
IPC分类号： H01L21302
CPC分类号： H01L29/66772 , H01L29/78648
摘要： A method for making a MOS transistor includes forming a first gate within a silicon-on-insulator substrate, forming a semiconductor channel region transversely surmounting the first gate, and forming semiconductor drain and source regions on each side of the channel region. The semiconductor channel region and drain and source regions may be produced by epitaxy on an upper surface of the first gate. The channel region may be isolated from the upper surface of the first gate by forming a tunnel under the channel region and at least partially filling the tunnel with a first dielectric. The second gate is formed on the channel region and transverse to the channel region. The second gate may be separated from an upper surface of the channel region by a second dielectric.
摘要翻译：制造MOS晶体管的方法包括在绝缘体上硅衬底内形成第一栅极，形成横向覆盖第一栅极的半导体沟道区，以及在沟道区的每一侧上形成半导体漏极和源极区。半导体沟道区域和漏极和源极区域可以通过在第一栅极的上表面上外延生长。通道区域可以通过在通道区域下形成隧道并且用第一电介质至少部分地填充隧道而与第一栅极的上表面隔离。第二栅极形成在沟道区域上并且横向于沟道区域。第二栅极可以通过第二电介质与沟道区的上表面分离。

8. 发明授权

US06495403B1 Gate-all-around semiconductor device and process for fabricating the same 有权
标题翻译：全栅半导体器件及其制造方法
公开(公告)号：US06495403B1
公开(公告)日：2002-12-17
申请号：US09680035
申请日：2000-10-05
申请人： Thomas Skotnicki , Malgorzata Jurczak
发明人： Thomas Skotnicki , Malgorzata Jurczak
IPC分类号： H01L2184
CPC分类号： H01L29/78696 , H01L29/42392 , H01L29/6675 , H01L29/78648
摘要： A method is provided for fabricating a semiconductor device having a gate-all-around architecture. A substrate is produced so as to include an active central region with an active main surface surrounded by an insulating peripheral region with an insulating main surface. The active main surface and the insulating main surface are coextensive and constitute a main surface of the substrate. A fist layer of Ge or an SiGe alloy is formed on the active main surface, and a silicon layer is formed on the first layer and on the insulating main surface. The silicon layer and the first layer are masked and etched in order to form a stack on the active main surface, and the first layer is removed so that the silicon layer of the stack forms a bridge structure over the active main surface. The bridge structure defines a tunnel with a corresponding part of the active main surface. A thin layer of a dielectric material that does not fill the tunnel is formed on the external and internal surfaces of the bridge structure and on the side walls. A conducting material is deposited so as to cover the bridge structure and fill the tunnel, and the conducting material is masked and etched in order to form a gate-all-around region for the semiconductor device. Also provided is a semiconductor device having a gate-all-around architecture.
摘要翻译：提供了一种用于制造具有栅极全能结构的半导体器件的方法。制造基板以包括活性中心区域，活性主表面被具有绝缘主表面的绝缘外围区域包围。活性主表面和绝缘主表面共同延伸并构成基材的主表面。在活性主表面上形成第一层Ge或SiGe合金，并且在第一层和绝缘主表面上形成硅层。掩模和蚀刻硅层和第一层，以便在活性主表面上形成堆叠，并且去除第一层，使得堆叠的硅层在活性主表面上形成桥结构。桥结构定义了具有活动主表面的对应部分的隧道。在桥结构的外表面和内表面上以及在侧壁上形成不填充隧道的介电材料的薄层。沉积导电材料以覆盖桥结构并填充隧道，并且对导电材料进行掩模和蚀刻，以形成半导体器件的栅极全周区域。还提供了具有栅极全能结构的半导体器件。

9. 再颁专利

USRE41841E1 Method for making a silicon substrate comprising a buried thin silicon oxide film 有权
标题翻译：一种用于制造包含掩埋的薄氧化硅膜的硅衬底的方法
公开(公告)号：USRE41841E1
公开(公告)日：2010-10-19
申请号：US11208132
申请日：2000-06-08
申请人： Malgorzata Jurczak , Thomas Skotnicki
发明人： Malgorzata Jurczak , Thomas Skotnicki
IPC分类号： H01L21/30
CPC分类号： H01L21/76251
摘要： A method for making a silicon substrate having a buried thin silicon oxide film is described. The method consists of: a) producing a first element having a first silicon body whereof the main surface is coated, in succession, with a buffer layer of germanium, or of an alloy of germanium and silicon, and with a thin silicon film; b) producing a second element, having a silicon body whereof a main surface is coated with a thin silicon oxide film; c) linking the first element with the second element such that the thin silicon film of the first element is in contact with the thin silicon oxide film of the second element; and d) eliminating the buffer layer to recuperate the silicon substrate having a buried thin silicon oxide film and a reusable silicon substrate. The method may be useful in making microelectronic devices such as CMOS and MOSFET devices.
摘要翻译：描述了制造具有掩埋的薄氧化硅膜的硅衬底的方法。该方法包括：a）制备具有第一硅体的第一元件，该第一硅体的主表面依次用锗的缓冲层或锗和硅的合金以及薄的硅膜涂覆; b）制造具有硅主体的第二元件，主体表面涂覆有薄的氧化硅膜; c）将第一元件与第二元件连接，使得第一元件的薄硅膜与第二元件的薄氧化硅膜接触; 以及d）消除缓冲层以恢复具有掩埋的薄氧化硅膜和可重复使用的硅衬底的硅衬底。该方法可用于制造诸如CMOS和MOSFET器件的微电子器件。

10. 发明申请

US20060001113A1 Magnetic sensor of very high sensitivity 有权
标题翻译：磁传感器灵敏度非常高
公开(公告)号：US20060001113A1
公开(公告)日：2006-01-05
申请号：US11214248
申请日：2005-08-29
申请人： Herve Jaouen , Thomas Skotnicki , Malgorzata Jurczak
发明人： Herve Jaouen , Thomas Skotnicki , Malgorzata Jurczak
IPC分类号： H01L27/14 , H01L21/00
CPC分类号： G10K9/13 , G01D5/242 , G01L9/0042 , Y10T428/1157 , Y10T428/1171 , Y10T428/19
摘要： A magnetic sensor includes a thin deformable membrane made of a conductive material forming a first plate of a capacitor which conducts an electric current therethrough. A second capacitor plate of the capacitor includes a doped region of a semiconductor substrate. A layer of a gaseous dielectric separates the two plates. The membrane deforms due to the effect of the Lorentz force generated by a magnetic field lying in the plane of the membrane and perpendicular to the lines of current being conducted therethrough. In addition, a process for fabricating this magnetic sensor is also provided as well as a device for measuring a magnetic field using the magnetic sensor.
摘要翻译：磁传感器包括由导电材料制成的薄的可变形膜，该导电材料形成电容器的第一板，其导通电流。电容器的第二电容器板包括半导体衬底的掺杂区域。气体介质层分离两个板。由于由位于膜的平面中的磁场产生的洛伦兹力的作用并且垂直于通过其传导的电流线，膜变形。此外，还提供了用于制造该磁传感器的工艺以及使用该磁传感器来测量磁场的装置。

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