专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

61. 发明申请

US20120280344A1 Wafer Scale Packaging Platform For Transceivers 有权
标题翻译：收发器晶圆尺寸封装平台
公开(公告)号：US20120280344A1
公开(公告)日：2012-11-08
申请号：US13463408
申请日：2012-05-03
申请人： Kalpendu Shastri , Vipulkumar Patel , Mark Webster , Prakash Gothoskar , Ravinder Kachru , Soham Pathak , Rao V. Yelamarty , Thomas Daugherty , Bipin Dama , Kaushik Patel , Kishor Desai
发明人： Kalpendu Shastri , Vipulkumar Patel , Mark Webster , Prakash Gothoskar , Ravinder Kachru , Soham Pathak , Rao V. Yelamarty , Thomas Daugherty , Bipin Dama , Kaushik Patel , Kishor Desai
IPC分类号： H01L31/12
CPC分类号： H01L25/50 , G02B6/423 , G02B6/4244 , G02B6/4245 , G02B6/4249 , G02B6/4257 , G02B6/426 , H01L25/167 , H01L2224/16225 , H01L2224/48091 , H01L2224/48227 , H01L2924/00014
摘要： A wafer scale implementation of an opto-electronic transceiver assembly process utilizes a silicon wafer as an optical reference plane and platform upon which all necessary optical and electronic components are simultaneously assembled for a plurality of separate transceiver modules. In particular, a silicon wafer is utilized as a “platform” (interposer) upon which all of the components for a multiple number of transceiver modules are mounted or integrated, with the top surface of the silicon interposer used as a reference plane for defining the optical signal path between separate optical components. Indeed, by using a single silicon wafer as the platform for a large number of separate transceiver modules, one is able to use a wafer scale assembly process, as well as optical alignment and testing of these modules.
摘要翻译：光电子收发器组件过程的晶片级实现利用硅晶片作为光学参考平面和平台，同时为多个单独的收发器模块组装所有必需的光学和电子部件。特别地，硅晶片被用作平台（插入器），用于多个收发器模块的所有部件安装或集成在该平台上，硅插入器的顶表面用作用于定义光信号的参考平面分离的光学元件之间的路径。实际上，通过使用单个硅晶片作为大量单独的收发器模块的平台，可以使用晶片尺度组装过程以及这些模块的光学对准和测试。

62. 发明申请

US20110216997A1 Sub-Micron Planar Lightwave Devices Formed on an SOI Optical Platform 有权
标题翻译： Sub-Micron平面光波器件形成于SOI光学平台上
公开(公告)号：US20110216997A1
公开(公告)日：2011-09-08
申请号：US13042989
申请日：2011-03-08
申请人： Prakash Gothoskar , Margaret Ghiron , Robert Keith Montgomery , Vipulkumar Patel , Kalpendu Shastri , Soham Pathak , Katherine A. Yanushefski
发明人： Prakash Gothoskar , Margaret Ghiron , Robert Keith Montgomery , Vipulkumar Patel , Kalpendu Shastri , Soham Pathak , Katherine A. Yanushefski
IPC分类号： G02B6/34 , G02B6/122 , G02B6/32
CPC分类号： G02B6/136 , G02B6/12007 , G02B6/122 , G02B6/124 , G02B6/125 , G02B6/2813 , G02B2006/12061 , G02B2006/12097 , G02B2006/12102 , G02B2006/12104 , G02B2006/12107 , G02B2006/12147 , G02B2006/12159 , G02B2006/12173
摘要： A set of planar, two-dimensional optical devices is able to be created in a sub-micron surface layer of an SOI structure, or within a sub-micron thick combination of an SOI surface layer and an overlying polysilicon layer. Conventional masking/etching techniques may be used to form a variety of passive and optical devices in this SOI platform. Various regions of the devices may be doped to form the active device structures. Additionally, the polysilicon layer may be separately patterned to provide a region of effective mode index change for a propagating optical signal.
摘要翻译：能够在SOI结构的亚微米表面层中或在SOI表面层和上覆多晶硅层的亚微米厚度组合内产生一组平面二维光学器件。传统的掩模/蚀刻技术可用于在该SOI平台中形成各种无源和光学器件。可以掺杂器件的各个区域以形成有源器件结构。另外，多晶硅层可以被分开构图以提供传播光信号的有效模式折射率变化的区域。

63. 发明授权

US07929814B2 Sub-micron planar lightwave devices formed on an SOI optical platform 有权
标题翻译：在SOI光学平台上形成的亚微米平面光波器件
公开(公告)号：US07929814B2
公开(公告)日：2011-04-19
申请号：US10830571
申请日：2004-04-23
申请人： Prakash Gothoskar , Margaret Ghiron , Robert Keith Montgomery , Vipulkumar Patel , Kalpendu Shastri , Soham Pathak , Katherine A. Yanushefski
发明人： Prakash Gothoskar , Margaret Ghiron , Robert Keith Montgomery , Vipulkumar Patel , Kalpendu Shastri , Soham Pathak , Katherine A. Yanushefski
IPC分类号： G02B6/10 , G02B6/12
CPC分类号： G02B6/136 , G02B6/12007 , G02B6/122 , G02B6/124 , G02B6/125 , G02B6/2813 , G02B2006/12061 , G02B2006/12097 , G02B2006/12102 , G02B2006/12104 , G02B2006/12107 , G02B2006/12147 , G02B2006/12159 , G02B2006/12173
摘要： A set of planar, two-dimensional optical devices is able to be created in a sub-micron surface layer of an SOI structure, or within a sub-micron thick combination of an SOI surface layer and an overlying polysilicon layer. Conventional masking/etching techniques may be used to form a variety of passive and optical devices in this SOI platform. Various regions of the devices may be doped to form the active device structures. Additionally, the polysilicon layer may be separately patterned to provide a region of effective mode index change for a propagating optical signal.
摘要翻译：能够在SOI结构的亚微米表面层中或在SOI表面层和上覆多晶硅层的亚微米厚度组合内产生一组平面二维光学器件。传统的掩模/蚀刻技术可用于在该SOI平台中形成各种无源和光学器件。可以掺杂器件的各个区域以形成有源器件结构。另外，多晶硅层可以被分开构图以提供传播光信号的有效模式折射率变化的区域。

64. 发明申请

US20090135861A1 Soi-based tunable laser 有权
标题翻译：基于Soi的可调谐激光器
公开(公告)号：US20090135861A1
公开(公告)日：2009-05-28
申请号：US12291246
申请日：2008-11-06
申请人： Mark Webster , David Piede , Prakash Gothoskar
发明人： Mark Webster , David Piede , Prakash Gothoskar
IPC分类号： H01S3/10
CPC分类号： H01S5/141 , H01S5/021 , H01S5/02248 , H01S5/02268 , H01S5/06256
摘要： A silicon-on-insulator (SOI)-based tunable laser is formed to include the gain medium (such as a semiconductor optical amplifier) disposed within a cavity formed within the SOI substrate. A tunable wavelength reflecting element and associated phase matching element are formed on the surface of the SOI structure, with optical waveguides formed in the surface SOI layer providing the communication between these components. The tunable wavelength element is controlled to adjust the optical wavelength. Separate discrete lensing elements may be disposed in the cavity with the gain medium, providing efficient coupling of the optical signal into the SOI waveguides. Alternatively, the gain medium itself may be formed to include spot converting tapers on its endfaces, the tapers used to provide mode matching into the associated optical waveguides.
摘要翻译：形成绝缘体上硅（SOI）的可调谐激光器以包括设置在形成于SOI衬底内的空腔内的增益介质（例如半导体光放大器）。在SOI结构的表面上形成可调波长反射元件和相关的相位匹配元件，其中形成在表面SOI层中的光波导提供这些部件之间的连通。可调波长元件被控制以调节光学波长。单独的离散透镜元件可以用增益介质设置在空腔中，从而提供光信号到SOI波导的有效耦合。或者，增益介质本身可以被形成为包括其端面上的点变换锥度，用于向相关联的光波导提供模式匹配的锥度。

65. 发明申请

US20080105940A1 SOI-based inverse nanotaper optical detector 审中-公开
标题翻译：基于SOI的反向纳米光学检测器
公开(公告)号：US20080105940A1
公开(公告)日：2008-05-08
申请号：US11811799
申请日：2007-06-12
申请人： David Piede , Vipulkumar Patel , Margaret Ghiron , Prakash Gothoskar , Robert Keith Montgomery
发明人： David Piede , Vipulkumar Patel , Margaret Ghiron , Prakash Gothoskar , Robert Keith Montgomery
IPC分类号： H01L31/0232
CPC分类号： H01L31/03529 , H01L31/103 , Y02E10/50
摘要： A photodetector integrated within a silicon-on-insulator (SOI) structure is formed directly upon an inverse nanotaper endface coupling region to reduce polarization sensitivity at the detector's input. The photodetector may be germanium-based PN (PIN) junction photodetector, a SiGe photodetector, a metal/silicon Schottky barrier photodetector, or any other suitable silicon-based photodetector. The inverse nanotaper photodetector may also be formed as an in-line monitoring device, converting only a portion of the in-coupled optical signal and allowing for the remainder to thereafter propagate along an associated optical waveguide.
摘要翻译：集成在绝缘体上硅（SOI）结构中的光电检测器直接形成在反向纳米锥端面耦合区域上，以降低检测器输入处的偏振灵敏度。光电检测器可以是基于锗的PN（PIN）结光电检测器，SiGe光电检测器，金属/硅肖特基势垒光电检测器或任何其它合适的硅基光电检测器。反向纳米管光电检测器也可以形成为在线监测装置，仅转换一部分耦合内的光信号，并允许剩余部分随后沿相关联的光波导传播。

66. 发明授权

US07358585B2 Silicon-based Schottky barrier infrared optical detector 有权
标题翻译：硅基肖特基势垒红外光检测器
公开(公告)号：US07358585B2
公开(公告)日：2008-04-15
申请号：US10990725
申请日：2004-11-17
申请人： Vipulkumar Patel , Margaret Ghiron , Prakash Gothoskar , Robert Keith Montgomery , Soham Pathak , David Piede , Kalpendu Shastri , Katherine A. Yanushefski
发明人： Vipulkumar Patel , Margaret Ghiron , Prakash Gothoskar , Robert Keith Montgomery , Soham Pathak , David Piede , Kalpendu Shastri , Katherine A. Yanushefski
IPC分类号： G02B6/10 , H01L31/0224
CPC分类号： H01L31/108 , G02B6/12004 , G02B6/1228 , H01L31/022408 , H01L31/0232 , H01L31/03921 , H01L31/153 , Y02E10/50
摘要： A silicon-based IR photodetector is formed within a silicon-on-insulator (SOI) structure by placing a metallic strip (preferably, a silicide) over a portion of an optical waveguide formed within a planar silicon surface layer (i.e., “planar SOI layer”) of the SOI structure, the planar SOI layer comprising a thickness of less than one micron. Room temperature operation of the photodetector is accomplished as a result of the relatively low dark current associated with the SOI-based structure and the ability to use a relatively small surface area silicide strip to collect the photocurrent. The planar SOI layer may be doped, and the geometry of the silicide strip may be modified, as desired, to achieve improved results over prior art silicon-based photodetectors.
摘要翻译：通过将金属条（优选硅化物）放置在形成在平面硅表面层内的光波导的一部分（即，“平面SOI”）上，在绝缘体上硅（SOI）结构中形成硅基红外光电检测器层“），平面SOI层包括小于1微米的厚度。由于与基于SOI的结构相关联的相对较低的暗电流和使用相对小的表面积硅化物带收集光电流的能力，光电检测器的室温操作是完成的。可以掺杂平面SOI层，并且根据需要可以修改硅化物带的几何形状，以实现相对于现有技术的硅基光电探测器的改进的结果。

67. 发明申请

US20070292075A1 Silicon modulator offset tuning arrangement 有权
标题翻译：硅调制器偏移调谐布置
公开(公告)号：US20070292075A1
公开(公告)日：2007-12-20
申请号：US11810591
申请日：2007-06-06
申请人： Robert Keith Montgomery , Margaret Ghiron , Prakash Gothoskar , Paulius Mindaugas Mosinskis , Vipulkumar Patel , Kalpendu Shastri , Mark Webster
发明人： Robert Keith Montgomery , Margaret Ghiron , Prakash Gothoskar , Paulius Mindaugas Mosinskis , Vipulkumar Patel , Kalpendu Shastri , Mark Webster
IPC分类号： G02B6/12
CPC分类号： G02F1/025 , G02F1/0147 , G02F1/225 , G02F2201/126
摘要： A silicon-based optical modulator structure includes one or more separate localized heating elements for changing the refractive index of an associated portion of the structure and thereby providing corrective adjustments to address unwanted variations in device performance. Heating is provided by thermo-optic devices such as, for example, silicon-based resistors, silicide resistors, forward-biased PN junctions, and the like, where any of these structures may easily be incorporated with a silicon-based optical modulator. The application of a DC voltage to any of these structures will generate heat, which then transfers into the waveguiding area. The increase in local temperature of the waveguiding area will, in turn, increase the refractive index of the waveguiding in the area. Control of the applied DC voltage results in controlling the refractive index
摘要翻译：基于硅的光学调制器结构包括一个或多个单独的局部加热元件，用于改变结构的相关部分的折射率，从而提供校正调整以解决器件性能的不期望的变化。加热由诸如硅基电阻器，硅化物电阻器，正向偏置PN结等的热光器件提供，其中这些结构中的任何一种可以容易地与硅基光学调制器结合。对这些结构中的任何一个施加直流电压将产生热量，然后传递到波导区域。波导区域的局部温度的增加又将增加该区域中波导的折射率。施加的直流电压的控制导致控制折射率

68. 发明授权

US07118682B2 Low loss SOI/CMOS compatible silicon waveguide and method of making the same 有权
标题翻译：低损耗SOI / CMOS兼容硅波导及其制造方法
公开(公告)号：US07118682B2
公开(公告)日：2006-10-10
申请号：US10806738
申请日：2004-03-23
申请人： Vipulkumar Kantilal Patel , Prakash Gothoskar , Robert Keith Montgomery , Margaret Ghiron
发明人： Vipulkumar Kantilal Patel , Prakash Gothoskar , Robert Keith Montgomery , Margaret Ghiron
IPC分类号： B29D11/00
CPC分类号： G02F1/025
摘要： A method and structure for reducing optical signal loss in a silicon waveguide formed within a silicon-on-insulator (SOI) structure uses CMOS processing techniques to round the edges/corners of the silicon material along the extent of the waveguiding region. One exemplary set of processes utilizes an additional, sacrificial silicon layer that is subsequently etched to form silicon sidewall fillets along the optical waveguide, the fillets thus “rounding” the edges of the waveguide. Alternatively, the sacrificial silicon layer can be oxidized to consume a portion of the underlying silicon waveguide layer, also rounding the edges. Instead of using a sacrificial silicon layer, an oxidation-resistant layer may be patterned over a blanket silicon layer, the pattern defined to protect the optical waveguiding region. A thermal oxidation process is then used to convert the exposed portion of the silicon layer into silicon dioxide, forming a bird's beak structure at the edges of the silicon layer, thus defining the “rounded” edges of the silicon waveguiding structure.
摘要翻译：用于减少在绝缘体上硅（SOI）结构中形成的硅波导中的光信号损耗的方法和结构使用CMOS处理技术来沿着波导区域的范围舍入硅材料的边缘/角。一个示例性的工艺集合利用附加的牺牲硅层，其随后被蚀刻以沿着光波导形成硅侧壁圆角，因此圆角“波浪”了波导的边缘。或者，牺牲硅层可以被氧化以消耗下面的硅波导层的一部分，也是边缘的四周。代替使用牺牲硅层，可以在覆盖硅层上图案化抗氧化层，所述图案被限定为保护光波导区域。然后使用热氧化工艺将硅层的暴露部分转化成二氧化硅，在硅层的边缘处形成鸟的喙结构，从而限定硅波导结构的“圆形”边缘。

69. 发明授权

US07113676B2 Planar waveguide optical isolator in thin silicon-on-isolator (SOI) structure 失效
标题翻译：薄硅隔离器（SOI）结构中的平面波导光隔离器
公开(公告)号：US07113676B2
公开(公告)日：2006-09-26
申请号：US11005286
申请日：2004-12-06
申请人： David Piede , Margaret Ghiron , Prakash Gothoskar , Robert Keith Montgomery , Vipulkumar Patel , Kalpendu Shastri , Soham Pathak , Katherine A. Yanushefski , Harvey Wagner
发明人： David Piede , Margaret Ghiron , Prakash Gothoskar , Robert Keith Montgomery , Vipulkumar Patel , Kalpendu Shastri , Soham Pathak , Katherine A. Yanushefski , Harvey Wagner
IPC分类号： G02B6/26 , G02B6/42
CPC分类号： G02B6/1228 , G02B6/125 , G02B6/4207
摘要： A planar optical isolator is formed within the silicon surface layer of an SOI structure. A forward-directed signal is applied to an input waveguiding section of the isolator and thereafter propagates through a non-reciprocal waveguide coupling region into an output waveguide section. A rearward-directed signal enters via the output waveguide section and is thereafter coupled into the non-reciprocal waveguide structure, where the geometry of the structure functions to couple only a small amount of the reflected signal into the input waveguide section. In one embodiment, the non-reciprocal structure comprises an N-way directional coupler (with one output waveguide, one input waveguide and N−1 isolating waveguides). In another embodiment, the non-reciprocal structure comprises a waveguide expansion region including a tapered, mode-matching portion coupled to the output waveguide and an enlarged, non-mode matching portion coupled to the input waveguide such that a majority of a reflected signal will be mismatched with respect to the input waveguide section. By cascading a number of such planar SOI-based structures, increased isolation can be achieved—advantageously within a monolithic arrangement.
摘要翻译：在SOI结构的硅表面层内形成平面光隔离器。正向信号被施加到隔离器的输入波导部分，然后通过非互易波导耦合区域传播到输出波导部分中。后向信号经由输出波导部分进入，然后耦合到不可逆波导结构中，其中结构的几何结构仅将少量的反射信号耦合到输入波导部分中。在一个实施例中，非互易结构包括N路定向耦合器（具有一个输出波导，一个输入波导和N-1个隔离波导）。在另一个实施例中，不可逆结构包括波导扩展区域，其包括耦合到输出波导的锥形模式匹配部分和耦合到输入波导的放大的非模式匹配部分，使得反射信号的大部分将相对于输入波导部分不匹配。通过级联多个这种平面的基于SOI的结构，可以实现增加的隔离 - 有利地在单片布置中。

70. 发明授权

US07109739B2 Wafer-level opto-electronic testing apparatus and method 有权
标题翻译：晶圆级光电测试仪器及方法
公开(公告)号：US07109739B2
公开(公告)日：2006-09-19
申请号：US11075430
申请日：2005-03-08
申请人： Prakash Gothoskar , Margaret Ghiron , Robert Keith Montgomery , Vipulkumar Patel , Kalpendu Shastri , Soham Pathak , David Piede , Katherine A. Yanushefski
发明人： Prakash Gothoskar , Margaret Ghiron , Robert Keith Montgomery , Vipulkumar Patel , Kalpendu Shastri , Soham Pathak , David Piede , Katherine A. Yanushefski
IPC分类号： G01R31/26 , G01R31/00
CPC分类号： G02B6/30 , G02B6/34 , G02B2006/12107
摘要： A wafer-level testing arrangement for opto-electronic devices formed in a silicon-on-insulator (SOI) wafer structure utilizes a single opto-electronic testing element to perform both optical and electrical testing. Beam steering optics may be formed on the testing element and used to facilitate the coupling between optical probe signals and optical coupling elements (e.g., prism couplers, gratings) formed on the top surface of the SOI structure. The optical test signals are thereafter directed into optical waveguides formed in the top layer of the SOI structure. The opto-electronic testing element also comprises a plurality of electrical test pins that are positioned to contact a plurality of bondpad test sites on the opto-electronic device and perform electrical testing operations. The optical test signal results may be converted into electrical representations within the SOI structure and thus returned to the testing element as electrical signals.
摘要翻译：用于在绝缘体上硅（SOI）晶片结构中形成的光电器件的晶片级测试装置利用单个光电测试元件执行光学和电学测试。光束转向光学元件可以形成在测试元件上，并且用于促进光学探针信号与形成在SOI结构的顶表面上的光耦合元件（例如，棱镜耦合器，光栅）之间的耦合。此后，光学测试信号被引导到形成在SOI结构的顶层中的光波导中。光电测试元件还包括多个电测试引脚，其被定位成接触光电器件上的多个接合焊盘测试点并执行电测试操作。光学测试信号结果可以转换为SOI结构内的电气表示，并因此作为电信号返回到测试元件。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式