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1. 发明授权

US08803269B2 Wafer scale packaging platform for transceivers 有权
标题翻译：收发器晶圆级封装平台
公开(公告)号：US08803269B2
公开(公告)日：2014-08-12
申请号：US13463408
申请日：2012-05-03
申请人： Kalpendu Shastri , Vipulkumar Patel , Mark Webster , Prakash Gothoskar , Ravinder Kachru , Soham Pathak , Rao V. Yelamarty , Thomas Daugherty , Bipin Dama , Kaushik Patel , Kishor Desai
发明人： Kalpendu Shastri , Vipulkumar Patel , Mark Webster , Prakash Gothoskar , Ravinder Kachru , Soham Pathak , Rao V. Yelamarty , Thomas Daugherty , Bipin Dama , Kaushik Patel , Kishor Desai
IPC分类号： H01L31/0232 , H01L29/40 , H01L23/053 , H01L23/12
CPC分类号： H01L25/50 , G02B6/423 , G02B6/4244 , G02B6/4245 , G02B6/4249 , G02B6/4257 , G02B6/426 , H01L25/167 , H01L2224/16225 , H01L2224/48091 , H01L2224/48227 , H01L2924/00014
摘要： A wafer scale implementation of an opto-electronic transceiver assembly process utilizes a silicon wafer as an optical reference plane and platform upon which all necessary optical and electronic components are simultaneously assembled for a plurality of separate transceiver modules. In particular, a silicon wafer is utilized as a “platform” (interposer) upon which all of the components for a multiple number of transceiver modules are mounted or integrated, with the top surface of the silicon interposer used as a reference plane for defining the optical signal path between separate optical components. Indeed, by using a single silicon wafer as the platform for a large number of separate transceiver modules, one is able to use a wafer scale assembly process, as well as optical alignment and testing of these modules.
摘要翻译：光电子收发器组件过程的晶片级实现利用硅晶片作为光学参考平面和平台，同时为多个单独的收发器模块组装所有必需的光学和电子部件。特别地，硅晶片被用作“平台”（插入器），在其上安装或集成多个收发器模块的所有组件，硅插入器的顶表面用作参考平面，用于定义分离光学元件之间的光信号路径。实际上，通过使用单个硅晶片作为大量单独的收发器模块的平台，可以使用晶片尺度组装过程以及这些模块的光学对准和测试。

2. 发明申请

US20120280344A1 Wafer Scale Packaging Platform For Transceivers 有权
标题翻译：收发器晶圆尺寸封装平台
公开(公告)号：US20120280344A1
公开(公告)日：2012-11-08
申请号：US13463408
申请日：2012-05-03
申请人： Kalpendu Shastri , Vipulkumar Patel , Mark Webster , Prakash Gothoskar , Ravinder Kachru , Soham Pathak , Rao V. Yelamarty , Thomas Daugherty , Bipin Dama , Kaushik Patel , Kishor Desai
发明人： Kalpendu Shastri , Vipulkumar Patel , Mark Webster , Prakash Gothoskar , Ravinder Kachru , Soham Pathak , Rao V. Yelamarty , Thomas Daugherty , Bipin Dama , Kaushik Patel , Kishor Desai
IPC分类号： H01L31/12
CPC分类号： H01L25/50 , G02B6/423 , G02B6/4244 , G02B6/4245 , G02B6/4249 , G02B6/4257 , G02B6/426 , H01L25/167 , H01L2224/16225 , H01L2224/48091 , H01L2224/48227 , H01L2924/00014
摘要： A wafer scale implementation of an opto-electronic transceiver assembly process utilizes a silicon wafer as an optical reference plane and platform upon which all necessary optical and electronic components are simultaneously assembled for a plurality of separate transceiver modules. In particular, a silicon wafer is utilized as a “platform” (interposer) upon which all of the components for a multiple number of transceiver modules are mounted or integrated, with the top surface of the silicon interposer used as a reference plane for defining the optical signal path between separate optical components. Indeed, by using a single silicon wafer as the platform for a large number of separate transceiver modules, one is able to use a wafer scale assembly process, as well as optical alignment and testing of these modules.
摘要翻译：光电子收发器组件过程的晶片级实现利用硅晶片作为光学参考平面和平台，同时为多个单独的收发器模块组装所有必需的光学和电子部件。特别地，硅晶片被用作平台（插入器），用于多个收发器模块的所有部件安装或集成在该平台上，硅插入器的顶表面用作用于定义光信号的参考平面分离的光学元件之间的路径。实际上，通过使用单个硅晶片作为大量单独的收发器模块的平台，可以使用晶片尺度组装过程以及这些模块的光学对准和测试。

3. 发明申请

US20050289490A1 Integrated approach for design, simulation and verification of monolithic, silicon-based opto-electronic circuits 有权
标题翻译：用于单片硅基光电路的设计，仿真和验证的综合方法
公开(公告)号：US20050289490A1
公开(公告)日：2005-12-29
申请号：US11159283
申请日：2005-06-22
申请人： Kalpendu Shastri , Soham Pathak , Prakash Gothoskar , Paulius Mosinskis , Bipin Dama
发明人： Kalpendu Shastri , Soham Pathak , Prakash Gothoskar , Paulius Mosinskis , Bipin Dama
IPC分类号： G06F17/50 , G06G7/62
CPC分类号： G06F17/5036 , G06F17/5068
摘要： Computer-aided design (CAD) tools are used to perform the integrated design, verification and layout of electrical and optical components in a monolithic, silicon-based electro-optic chip. Separate top-level behavioral logic designs are prepared for the three different types of elements included within the final, silicon-based monolithic structure: (1) digital electronic integrated circuit elements; (2) analog/mixed signal electronic integrated circuit elements; and (3) opto-electronic elements (including passive and active optical elements). Once the behavioral logic design is completed, the results are combined and co-simulated. A physical layout design is developed and verified for each different type of element in the circuit. The separate physical layouts are then co-verified, to assess the properties of the overall physical design. The results of the co-simulation are compared to the results of the co-verification, with alterations made in the logic design and/or the physical layout until the desired operating parameters are obtained. Once the desired results are generated, conventional wafer-level fabrication operations are then considered to provide a final product (“tape out”).
摘要翻译：计算机辅助设计（CAD）工具用于在单片硅基电光芯片中执行电气和光学部件的集成设计，验证和布局。为最终的硅基单片结构中包含的三种不同类型的元件准备了独立的顶级行为逻辑设计：（1）数字电子集成电路元件; （2）模拟/混合信号电子集成电路元件; 和（3）光电元件（包括无源和有源光学元件）。一旦行为逻辑设计完成，结果将被合并并共同模拟。为电路中的每种不同类型的元件开发和验证物理布局设计。然后将单独的物理布局共同验证，以评估整体物理设计的属性。将共模拟的结果与协同验证的结果进行比较，在逻辑设计和/或物理布局中进行改变，直到获得所需的操作参数。一旦产生期望的结果，则常规晶圆级制造操作被认为是提供最终产品（“磁带输出”）。

4. 发明授权

US07269809B2 Integrated approach for design, simulation and verification of monolithic, silicon-based opto-electronic circuits 有权
标题翻译：用于单片硅基光电路的设计，仿真和验证的综合方法
公开(公告)号：US07269809B2
公开(公告)日：2007-09-11
申请号：US11159283
申请日：2005-06-22
申请人： Kalpendu Shastri , Soham Pathak , Prakash Gothoskar , Paulius Mosinskis , Bipin Dama
发明人： Kalpendu Shastri , Soham Pathak , Prakash Gothoskar , Paulius Mosinskis , Bipin Dama
IPC分类号： G06F17/50 , G06F17/10
CPC分类号： G06F17/5036 , G06F17/5068
摘要： Computer-aided design (CAD) tools are used to perform the integrated design, verification and layout of electrical and optical components in a monolithic, silicon-based electro-optic chip. Separate top-level behavioral logic designs are prepared for the three different types of elements included within the final, silicon-based monolithic structure: (1) digital electronic integrated circuit elements; (2) analog/mixed signal electronic integrated circuit elements; and (3) opto-electronic elements (including passive and active optical elements). Once the behavioral logic design is completed, the results are combined and co-simulated. A physical layout design is developed and verified for each different type of element in the circuit. The separate physical layouts are then co-verified, to assess the properties of the overall physical design. The results of the co-simulation are compared to the results of the co-verification, with alterations made in the logic design and/or the physical layout until the desired operating parameters are obtained. Once the desired results are generated, conventional wafer-level fabrication operations are then considered to provide a final product (“tape out”).
摘要翻译：计算机辅助设计（CAD）工具用于在单片硅基电光芯片中执行电气和光学部件的集成设计，验证和布局。为最终的硅基单片结构中包含的三种不同类型的元件准备了独立的顶级行为逻辑设计：（1）数字电子集成电路元件; （2）模拟/混合信号电子集成电路元件; 和（3）光电元件（包括无源和有源光学元件）。一旦行为逻辑设计完成，结果将被合并并共同模拟。为电路中的每种不同类型的元件开发和验证物理布局设计。然后将单独的物理布局共同验证，以评估整体物理设计的属性。将共模拟的结果与协同验证的结果进行比较，在逻辑设计和/或物理布局中进行改变，直到获得所需的操作参数。一旦产生期望的结果，则常规晶圆级制造操作被认为是提供最终产品（“磁带输出”）。

5. 发明授权

US07003196B2 External grating structures for interfacing wavelength-division-multiplexed optical sources with thin optical waveguides 有权
标题翻译：用于将波分复用光源与薄光波导接口连接的外部光栅结构
公开(公告)号：US07003196B2
公开(公告)日：2006-02-21
申请号：US10935145
申请日：2004-09-07
申请人： Margaret Ghiron , Prakash Gothoskar , Robert Keith Montgomery , Vipulkumar Patel , Soham Pathak , Kalpendu Shastri , Katherine A. Yanushefski
发明人： Margaret Ghiron , Prakash Gothoskar , Robert Keith Montgomery , Vipulkumar Patel , Soham Pathak , Kalpendu Shastri , Katherine A. Yanushefski
IPC分类号： G02B6/34
CPC分类号： G02B6/12007 , G02B6/122 , G02B6/29311 , G02B6/34
摘要： A coupling arrangement for allowing multiple wavelengths to be coupled into and out of a relatively thin silicon optical waveguide layer utilizes a diffractive optical element, in the form of a volume phase grating, in combination with a prism coupling structure. The diffractive optical element is formed to comprise a predetermined modulation index sufficient to diffract the various wavelengths through angles associated with improving the coupling efficiency of each wavelength into the silicon waveguide. The diffractive optical element may be formed as a separate element, or formed as an integral part of the coupling facet of the prism coupler.
摘要翻译：用于允许多个波长耦合到相对薄的硅光波导层中的耦合布置利用体积相位光栅的形式的衍射光学元件与棱镜耦合结构组合。衍射光学元件被形成为包括足以将各种波长衍射成与提高每个波长到硅波导的耦合效率相关联的角度的预定调制指数。衍射光学元件可以形成为单独的元件，或者形成为棱镜耦合器的耦合面的整体部分。

6. 发明申请

US20050194990A1 Wafer-level opto-electronic testing apparatus and method 有权
标题翻译：晶圆级光电测试仪器及方法
公开(公告)号：US20050194990A1
公开(公告)日：2005-09-08
申请号：US11075430
申请日：2005-03-08
申请人： Prakash Gothoskar , Margaret Ghiron , Robert Montgomery , Vipulkumar Patel , Kalpendu Shastri , Soham Pathak , David Piede , Katherine Yanushefski
发明人： Prakash Gothoskar , Margaret Ghiron , Robert Montgomery , Vipulkumar Patel , Kalpendu Shastri , Soham Pathak , David Piede , Katherine Yanushefski
IPC分类号： G01R31/26
CPC分类号： G02B6/30 , G02B6/34 , G02B2006/12107
摘要： A wafer-level testing arrangement for opto-electronic devices formed in a silicon-on-insulator (SOI) wafer structure utilizes a single opto-electronic testing element to perform both optical and electrical testing. Beam steering optics may be formed on the testing element and used to facilitate the coupling between optical probe signals and optical coupling elements (e.g., prism couplers, gratings) formed on the top surface of the SOI structure. The optical test signals are thereafter directed into optical waveguides formed in the top layer of the SOI structure. The opto-electronic testing element also comprises a plurality of electrical test pins that are positioned to contact a plurality of bondpad test sites on the opto-electronic device and perform electrical testing operations. The optical test signal results may be converted into electrical representations within the SOI structure and thus returned to the testing element as electrical signals.
摘要翻译：用于在绝缘体上硅（SOI）晶片结构中形成的光电器件的晶片级测试装置利用单个光电测试元件执行光学和电学测试。光束转向光学元件可以形成在测试元件上，并且用于促进光学探针信号与形成在SOI结构的顶表面上的光耦合元件（例如，棱镜耦合器，光栅）之间的耦合。此后，光学测试信号被引导到形成在SOI结构的顶层中的光波导中。光电测试元件还包括多个电测试引脚，其被定位成接触光电器件上的多个接合焊盘测试点并执行电测试操作。光学测试信号结果可以转换为SOI结构内的电气表示，并因此作为电信号返回到测试元件。

7. 发明申请

US20050189591A1 Active manipulation of light in a silicon-on-insulator (SOI) structure 有权
标题翻译：主动操纵绝缘体上硅（SOI）结构中的光
公开(公告)号：US20050189591A1
公开(公告)日：2005-09-01
申请号：US11069852
申请日：2005-02-28
申请人： Prakash Gothoskar , Margaret Ghiron , Robert Montgomery , Vipulkumar Patel , Kalpendu Shastri , Soham Pathak , Katherine Yanushefski
发明人： Prakash Gothoskar , Margaret Ghiron , Robert Montgomery , Vipulkumar Patel , Kalpendu Shastri , Soham Pathak , Katherine Yanushefski
IPC分类号： G02B6/12 , H01L27/15
CPC分类号： G02B6/12004 , G02F1/025 , G02F1/292 , G02F2001/294
摘要： An arrangement for actively controlling, in two dimensions, the manipulation of light within an SOI-based optical structure utilizes doped regions formed within the SOI layer and a polysilicon layer of a silicon-insulator-silicon capacitive (SISCAP) structure. The regions are oppositely doped so as to form an active device, where the application of a voltage potential between the oppositely doped regions functions to modify the refractive index in the affected area and alter the properties of an optical signal propagating through the region. The doped regions may be advantageously formed to exhibit any desired “shaped” (such as, for example, lenses, prisms, Bragg gratings, etc.), so as to manipulate the propagating beam as a function of the known properties of these devices. One or more active devices of the present invention may be included within a SISCAP formed, SOI-based optical element (such as, for example, a Mach-Zehnder interferometer, ring resonator, optical switch, etc.) so as to form an active, tunable element.
摘要翻译：用于主动地控制SOI基光学结构内的光的操纵的布置利用形成在SOI层内的掺杂区域和硅绝缘体 - 硅电容（SISCAP）结构的多晶硅层。这些区域相反地掺杂以形成有源器件，其中在相对掺杂区域之间施加电压电位用于改变受影响区域中的折射率并改变传播通过该区域的光信号的特性。可以有利地形成掺杂区域以呈现任何期望的“成形”（例如，透镜，棱镜，布拉格光栅等），以便根据这些器件的已知特性来操纵传播光束。本发明的一个或多个有源器件可以包括在形成SISCAP的SOI基光学元件（例如，诸如Mach-Zehnder干涉仪，环形谐振器，光学开关等）中，以形成活跃的，可调元素。

8. 发明申请

US20050135727A1 EMI-EMC shield for silicon-based optical transceiver 审中-公开
标题翻译：用于硅基光收发器的EMI-EMC屏蔽
公开(公告)号：US20050135727A1
公开(公告)日：2005-06-23
申请号：US11013722
申请日：2004-12-16
申请人： David Piede , Margaret Ghiron , Prakash Gothoskar , Robert Montgomery , Vipulkumar Patel , Kalpendu Shastri , Soham Pathak , Katherine Yanushefski
发明人： David Piede , Margaret Ghiron , Prakash Gothoskar , Robert Montgomery , Vipulkumar Patel , Kalpendu Shastri , Soham Pathak , Katherine Yanushefski
IPC分类号： G02B6/42 , G02B6/12
CPC分类号： G02B6/4277 , G02B6/42 , G02B6/4246 , H01L2224/48091 , H01L2224/49175 , H01L2924/00014
摘要： An SOI-based opto-electronic structure includes various electronic components disposed with their associated optical components within a single SOI layer, forming a monolithic arrangement. EMI/EMC shielding is provided by forming a metallized outer layer on the surface of an external prism coupler that interfaces with the SOI layer, the metallized layer including transparent apertures to allow an optical signal to be coupled into and out of the SOI layer. The opposing surface of the prism coupler may also be coated with a metallic material to provide additional shielding. Further, metallic shielding plates may be formed on the SOI structure itself, overlying the locations of EMI-sensitive electronics. All of these metallic layers are ultimately coupled to an external ground plane to isolate the structure and provide the necessary shielding.
摘要翻译：基于SOI的光电结构包括在单个SOI层内与其相关联的光学部件一起设置的各种电子部件，形成单片布置。通过在与SOI层相接的外部棱镜耦合器的表面上形成金属化的外层来提供EMI / EMC屏蔽，金属化层包括透明的孔，以允许光信号耦合到SOI层中。棱镜耦合器的相对表面也可以用金属材料涂覆以提供额外的屏蔽。此外，金属屏蔽板可以形成在SOI结构本身上，覆盖EMI敏感电子器件的位置。所有这些金属层最终被耦合到外部接地平面以隔离结构并提供必要的屏蔽。

9. 发明申请

US20050123232A1 Planar waveguide optical isolator in thin silicon-on-isolator (SOI) structure 失效
标题翻译：薄硅隔离器（SOI）结构中的平面波导光隔离器
公开(公告)号：US20050123232A1
公开(公告)日：2005-06-09
申请号：US11005286
申请日：2004-12-06
申请人： David Piede , Margaret Ghiron , Prakash Gothoskar , Robert Montgomery , Vipulkumar Patel , Kalpendu Shastri , Soham Pathak , Katherine Yanushefski , Harvey Wagner
发明人： David Piede , Margaret Ghiron , Prakash Gothoskar , Robert Montgomery , Vipulkumar Patel , Kalpendu Shastri , Soham Pathak , Katherine Yanushefski , Harvey Wagner
IPC分类号： G02B20060101 , G02B6/122 , G02B6/125 , G02B6/26 , G02B6/42
CPC分类号： G02B6/1228 , G02B6/125 , G02B6/4207
摘要： A planar optical isolator is formed within the silicon surface layer of an SOI structure. A forward-directed signal is applied to an input waveguiding section of the isolator and thereafter propagates through a non-reciprocal waveguide coupling region into an output waveguide section. A rearward-directed signal enters via the output waveguide section and is thereafter coupled into the non-reciprocal waveguide structure, where the geometry of the structure functions to couple only a small amount of the reflected signal into the input waveguide section. In one embodiment, the non-reciprocal structure comprises an N-way directional coupler (with one output waveguide, one input waveguide and N-1 isolating waveguides). In another embodiment, the non-reciprocal structure comprises a waveguide expansion region including a tapered, mode-matching portion coupled to the output waveguide and an enlarged, non-mode matching portion coupled to the input waveguide such that a majority of a reflected signal will be mismatched with respect to the input waveguide section. By cascading a number of such planar SOI-based structures, increased isolation can be achieved—advantageously within a monolithic arrangement.
摘要翻译：在SOI结构的硅表面层内形成平面光隔离器。正向信号被施加到隔离器的输入波导部分，然后通过非互易波导耦合区域传播到输出波导部分中。后向信号经由输出波导部分进入，然后耦合到不可逆波导结构中，其中结构的几何结构仅将少量的反射信号耦合到输入波导部分中。在一个实施例中，非互易结构包括N路定向耦合器（具有一个输出波导，一个输入波导和N-1个隔离波导）。在另一个实施例中，不可逆结构包括波导扩展区域，其包括耦合到输出波导的锥形模式匹配部分和耦合到输入波导的放大的非模式匹配部分，使得反射信号的大部分将相对于输入波导部分不匹配。通过级联多个这种平面的基于SOI的结构，可以实现增加的隔离 - 有利地在单片布置中。

10. 发明申请

US20080253713A1 Optical crossover in thin silicon 有权
标题翻译：薄硅光学交叉
公开(公告)号：US20080253713A1
公开(公告)日：2008-10-16
申请号：US12157630
申请日：2008-06-12
申请人： David Piede , Prakash Gothoskar , Margaret Ghiron , Robert Keith Montgomery , Vipulkumar Patel , Soham Pathak , Kalpendu Shastri , Katherine A. Yanushefski
发明人： David Piede , Prakash Gothoskar , Margaret Ghiron , Robert Keith Montgomery , Vipulkumar Patel , Soham Pathak , Kalpendu Shastri , Katherine A. Yanushefski
IPC分类号： G02B6/12
CPC分类号： G02B6/12004 , G02B6/125 , G02B2006/12061 , G02B2006/12097 , G02B2006/12104 , G02B2006/12176 , G02B2006/12195
摘要： An arrangement for providing optical crossovers between waveguides formed in an SOI-based structure utilize a patterned geometry in the SOI structure that is selected to reduce the effects of crosstalk in the area where the signals overlap. Preferably, the optical signals are fixed to propagate along orthogonal directions (or are of different wavelengths) to minimize the effects of crosstalk. The geometry of the SOI structure is patterned to include predetermined tapers and/or reflecting surfaces to direct/shape the propagating optical signals. The patterned waveguide regions within the optical crossover region may be formed to include overlying polysilicon segments to further shape the propagating beams and improve the coupling efficiency of the crossover arrangement.
摘要翻译：用于在基于SOI的结构中形成的波导之间提供光学交叉的装置利用SOI结构中的图案化几何形状，其被选择以减少信号重叠的区域中串扰的影响。优选地，光信号被固定以沿着正交方向（或不同波长）传播，以最小化串扰的影响。 SOI结构的几何形状被图案化以包括预定的锥形和/或反射表面以引导/形成传播的光学信号。光学交叉区域内的图案化波导区域可以形成为包括覆盖多晶硅段，以进一步使传播波束成形，并提高交叉布置的耦合效率。

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