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61. 发明授权

US07298006B2 Nonvolatile semiconductor memory device including improved gate electrode 有权
标题翻译：包括改进的栅电极的非易失性半导体存储器件
公开(公告)号：US07298006B2
公开(公告)日：2007-11-20
申请号：US11535514
申请日：2006-09-27
申请人： Fumitaka Arai , Yasuhiko Matsunaga , Makoto Sakuma , Riichiro Shirota , Akira Shimizu
发明人： Fumitaka Arai , Yasuhiko Matsunaga , Makoto Sakuma , Riichiro Shirota , Akira Shimizu
IPC分类号： H01L29/788
CPC分类号： H01L27/115 , G11C16/0483 , G11C16/10 , H01L21/28273 , H01L27/11521 , H01L29/42324 , H01L29/42336 , H01L29/7883
摘要： A floating gate is formed on a semiconductor substrate via a gate insulating film. Diffused layers are formed as sources or drain regions on opposite sides of the floating gate in the semiconductor substrate. First and second control gates are formed opposite to both of the diffused layers on the opposite sides of the floating gate via an inter-gate insulating film to drive the floating gate.
摘要翻译：通过栅极绝缘膜在半导体衬底上形成浮栅。扩散层在半导体衬底中的浮置栅极的相对侧上形成为源区或漏极区。第一和第二控制栅极通过栅极间绝缘膜与浮动栅极的相对侧上的两个扩散层相对形成，以驱动浮置栅极。

62. 发明申请

US20070187749A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD 有权
标题翻译：半导体器件和制造方法
公开(公告)号：US20070187749A1
公开(公告)日：2007-08-16
申请号：US11733488
申请日：2007-04-10
申请人： Kikuko Sugimae , Hiroyuki Kutsukake , Masayuki Ichige , Michiharu Matsui , Yuji Takeuchi , Riichiro Shirota
发明人： Kikuko Sugimae , Hiroyuki Kutsukake , Masayuki Ichige , Michiharu Matsui , Yuji Takeuchi , Riichiro Shirota
IPC分类号： H01L29/788
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L27/11529
摘要： A semiconductor device comprises a memory cell array portion and peripheral circuit portion, wherein a first insulation film including elements as main components other than nitrogen fills between the memory cell gate electrodes of the memory cell array portion, the first insulation film is formed as a liner on a sidewall of a peripheral gate electrode of the peripheral circuit portion simultaneously with the memory cell portion, and a second insulation film including nitrogen as the main component is formed on the sidewall of the peripheral gate electrode via the first insulation film, thus enabling not only the formation of the memory cell portion having high reliability, but also the formation of a peripheral circuit with good efficiency, simultaneously, and avoiding gate offset of a peripheral gate.
摘要翻译：半导体器件包括存储单元阵列部分和外围电路部分，其中包括作为除氮之外的主要成分的元素的第一绝缘膜填充在存储单元阵列部分的存储单元栅电极之间，第一绝缘膜形成为衬垫在周边电路部分的外围栅电极的侧壁上与存储单元部分同时，并且通过第一绝缘膜在外围栅电极的侧壁上形成包括氮作为主要成分的第二绝缘膜，从而不能仅形成具有高可靠性的存储单元部分，而且形成具有良好效率的周边电路，同时避免了外围栅极的栅极偏移。

63. 发明授权

US07248034B2 Time limit function utilization apparatus 有权
公开(公告)号：US07248034B2
公开(公告)日：2007-07-24
申请号：US11476720
申请日：2006-06-29
申请人： Hiroshi Watanabe , Kazuya Matsuzawa , Riichiro Shirota
发明人： Hiroshi Watanabe , Kazuya Matsuzawa , Riichiro Shirota
IPC分类号： G01R19/00
CPC分类号： H01L29/7883 , G01R31/2642 , G06F9/3802 , G06F2221/2137 , G06K19/0723 , G06K19/073 , G06K19/07372 , G06Q20/341 , G07C9/00111 , G07C2009/00976 , G07F7/082 , G07F7/084 , G07F7/1008 , G11C16/14 , G11C16/349 , H01L21/28273 , H01L27/115 , H01L27/11558 , H01L29/42324 , H01L29/66825
摘要： A time limit function utilization apparatus includes a first function block, a second function block, a signal line which connects the first and second function blocks and allows using a desired function that is generated by accessing the first and second function blocks with each other, and a semiconductor time switch interposed in or connected to the signal line, and disables or enables mutual access between the first and second function blocks upon the lapse of a predetermined time.

64. 发明申请

US20070152261A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE HAVING ELEMENT ISOLATING REGION OF TRENCH TYPE 有权
公开(公告)号：US20070152261A1
公开(公告)日：2007-07-05
申请号：US11687019
申请日：2007-03-16
申请人： Michiharu Matsui , Seiichi Mori , Riichiro Shirota , Yuji Takeuchi , Takeshi Kamigaichi
发明人： Michiharu Matsui , Seiichi Mori , Riichiro Shirota , Yuji Takeuchi , Takeshi Kamigaichi
IPC分类号： H01L29/788
CPC分类号： H01L27/11526 , H01L21/76229 , H01L27/105 , H01L27/115 , H01L27/11519 , H01L27/11521 , H01L27/11524 , H01L27/11529 , H01L27/11531 , H01L27/11543 , H01L29/7887
摘要： Disclosure is semiconductor device of a selective gate region, comprising a semiconductor layer, a first insulating film formed on the semiconductor layer, a first electrode layer formed on the first insulating layer, an element isolating region comprising an element isolating insulating film formed to extend through the first electrode layer and the first insulating film to reach an inner region of the semiconductor layer, the element isolating region isolating a element region and being self-aligned with the first electrode layer, a second insulating film formed on the first electrode layer and the element isolating region, an open portion exposing a surface of the first electrode layer being formed in the second insulating film, and a second electrode layer formed on the second insulating film and the exposed surface of the first electrode layer, the second electrode layer being electronically connected to the first electrode layer via the open portion.

65. 发明授权

US07224612B2 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US07224612B2
公开(公告)日：2007-05-29
申请号：US11194799
申请日：2005-08-02
申请人： Tomoharu Tanaka , Hiroshi Nakamura , Ken Takeuchi , Riichiro Shirota , Fumitaka Arai , Susumu Fujimura
发明人： Tomoharu Tanaka , Hiroshi Nakamura , Ken Takeuchi , Riichiro Shirota , Fumitaka Arai , Susumu Fujimura
IPC分类号： G11C16/04
CPC分类号： G11C16/0483 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C16/3404 , G11C16/3409 , G11C16/344 , G11C16/3445 , G11C16/345 , G11C16/3454 , G11C16/3459 , G11C16/3463 , G11C2211/5621
摘要： A NAND cell unit includes a plurality of memory cells which are connected in series. An erase operation is effected on all memory cells. Then, a soft-program voltage, which is opposite in polarity to the erase voltage applied in the erase operation, is applied to all memory cells, thereby setting all memory cells out of an over-erased state. Thereafter, a program voltage of 20V is applied to the control gate of any selected one of the memory cells, 0V is applied to the control gates of the two memory cells provided adjacent to the selected memory cell, and 11V is applied to the control gates of the remaining memory cells. Data is thereby programmed into the selected memory cell. The time for which the program voltage is applied to the selected memory cell is adjusted in accordance with the data to be programmed into the selected memory cell. Hence, data “0” can be correctly programmed into the selected memory cell, multi-value data can be read from any selected memory cell at high speed.
摘要翻译： NAND单元单元包括串联连接的多个存储单元。对所有存储单元进行擦除操作。然后，对所有存储单元施加与施加在擦除操作中的擦除电压极性相反的软编程电压，从而将所有存储单元设置为过擦除状态。此后，将20V的编程电压施加到任何一个存储单元的控制栅极，将0V施加到与所选存储单元相邻设置的两个存储单元的控制栅极，并将11V施加到控制栅极的剩余存储单元。因此数据被编程到所选择的存储单元中。根据要编程到所选择的存储单元中的数据来调整对所选存储单元施加编程电压的时间。因此，可以将数据“0”正确地编程到所选择的存储单元中，可以从任何选择的存储单元高速读取多值数据。

66. 发明申请

US20070070708A1 NONVOLATILE SEMICONDUCTOR MEMORY, FABRICATION METHOD FOR THE SAME, SEMICONDUCTOR INTEGRATED CIRCUITS AND SYSTEMS 失效
标题翻译：非线性半导体存储器，其制造方法，半导体集成电路和系统
公开(公告)号：US20070070708A1
公开(公告)日：2007-03-29
申请号：US11559785
申请日：2006-11-14
申请人： Masayuki ICHIGE , Koji Hashimoto , Tatsuaki Kuji , Seiichi Mori , Riichiro Shirota , Yuji Takeuchi , Koji Sakui
发明人： Masayuki ICHIGE , Koji Hashimoto , Tatsuaki Kuji , Seiichi Mori , Riichiro Shirota , Yuji Takeuchi , Koji Sakui
IPC分类号： G11C16/04
CPC分类号： H01L27/11521 , G11C16/0483 , H01L27/0207 , H01L27/115 , H01L27/11519 , H01L27/11524
摘要： A nonvolatile semiconductor memory which is configured to include a plurality of word lines disposed in a row direction; a plurality of bit lines disposed in a column direction perpendicular to the word lines; memory cell transistors having a charge storage layer, provided in the column direction and an electronic storage condition of the memory cell transistor configured to be controlled by one of the plurality of the word lines connected to the memory cell; a plurality of first select transistors, each including a gate electrode, selecting the memory cell transistors provided in the column direction, arranged in the column direction and adjacent to the memory cell transistors at a first end of the memory cell transistors; and a first select gate line connected to each of the gate electrodes of the first select transistors.
摘要翻译：一种非易失性半导体存储器，被配置为包括沿行方向布置的多个字线; 沿垂直于字线的列方向布置的多个位线; 具有沿列方向设置的电荷存储层的存储单元晶体管和存储单元晶体管的电子存储状态，其被配置为由连接到存储单元的多条字线之一控制; 多个第一选择晶体管，每个包括栅极，选择沿列方向设置的存储单元晶体管，其布置在存储单元晶体管的第一端处并与存储单元晶体管相邻; 以及连接到第一选择晶体管的每个栅电极的第一选择栅极线。

67. 发明授权

US07158398B2 Semiconductor memory device having row decoder in which high-voltage-applied portion is located adjacent to low-voltage-applied portion 失效
标题翻译：具有行解码器的半导体存储器件，其中高压施加部分位于与低电压施加部分相邻的位置
公开(公告)号：US07158398B2
公开(公告)日：2007-01-02
申请号：US11052792
申请日：2005-02-09
申请人： Akira Shimizu , Riichiro Shirota , Fumitaka Arai
发明人： Akira Shimizu , Riichiro Shirota , Fumitaka Arai
IPC分类号： G11C5/06
CPC分类号： G11C16/08 , G11C16/0483 , H01L27/105 , H01L27/115
摘要： A semiconductor memory device includes a first, second, and third memory cell transistors in which information can be electrically rewritten, addresses of which are consecutive in a row direction. One end of a current passage in each of a first, second, and third memory cell transistors is connected to a control electrode of the first, second, and third memory cell transistors. A write voltage, a pass voltage lower than the write voltage, and a first voltage lower than the pass voltage are applied to the other ends of the first, second, and third transfer transistors. A first control section applies the first on-voltage to make the first transfer transistor conductive, to a gate of the first transfer transistor. A second control section applies a second on-voltage to make the second and third transfer transistors conductive, to gates of the second and third transfer transistors.
摘要翻译：半导体存储器件包括第一，第二和第三存储单元晶体管，其中信息可被电重写，其地址在行方向上是连续的。第一，第二和第三存储单元晶体管中的每一个中的电流通路的一端连接到第一，第二和第三存储单元晶体管的控制电极。写入电压，低于写入电压的通过电压以及低于通过电压的第一电压施加到第一，第二和第三转移晶体管的另一端。第一控制部分将第一传导晶体管导通的第一导通电压施加到第一传输晶体管的栅极。第二控制部分施加第二导通电压以使第二和第三转移晶体管导通到第二和第三转移晶体管的栅极。

68. 发明授权

US07151686B2 Semiconductor memory device and electric device with the same 有权
标题翻译：半导体存储器件和电器件相同
公开(公告)号：US07151686B2
公开(公告)日：2006-12-19
申请号：US10944910
申请日：2004-09-21
申请人： Kikuko Sugimae , Takuya Futatsuyama , Riichiro Shirota , Masayuki Ichige
发明人： Kikuko Sugimae , Takuya Futatsuyama , Riichiro Shirota , Masayuki Ichige
IPC分类号： G11C17/00
CPC分类号： G11C8/12 , G11C8/10 , G11C16/08
摘要： A semiconductor memory device having: a cell array including bit lines, word lines and memory cells disposed at crossings thereof, plural memory cells being connected in series to constitute a NAND cell unit, plural blocks being arranged, each being constituted by plural NAND cell units arranged in the word line direction; and a row decoder configured to select a block, wherein the row decoder includes: transferring transistor arrays disposed in association with the blocks, in each of which transistors are arranged for transferring word line drive voltages; first decode portions disposed in association with the transferring transistor arrays, which are applied with boosted voltages to selectively drive the transferring transistor arrays; and second decode portions configured to select one of the blocks, each of which is disposed to be shared by adjacent two first decode portions.
摘要翻译：一种半导体存储器件，具有：包括位线，字线和位于其交叉处的存储单元的单元阵列，多个存储单元串联连接以构成NAND单元单元，多个块被布置，每个由多个NAND单元单元排列在字线方向; 以及配置为选择块的行解码器，其中所述行解码器包括：传送与所述块相关联地布置的晶体管阵列，其中每个晶体管布置用于传送字线驱动电压; 与传输晶体管阵列相关联地设置的第一解码部分，其被施加升压电压以选择性地驱动传输晶体管阵列; 以及第二解码部分，被配置为选择所述块之一，每个块被布置为由相邻的两个第一解码部分共享。

69. 发明申请

US20060262600A1 Non-Volatile semiconductor memory device 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US20060262600A1
公开(公告)日：2006-11-23
申请号：US11492994
申请日：2006-07-26
申请人： Riichiro Shirota , Kikuko Sugimae
发明人： Riichiro Shirota , Kikuko Sugimae
IPC分类号： G11C16/04
CPC分类号： H01L27/11526 , G11C16/0433 , H01L27/105 , H01L27/11521 , H01L27/11529 , H01L27/11558
摘要： A memory cell has a selection transistor constituted of an MOS transistor having a gate electrode and a cell transistor constituted of an MOS transistor having the same polarity as the selection transistor, in such a configuration that these two transistors are connected in series. A bit line is connected to a drain region of the selection transistor and a word line is connected to the gate electrode thereof. A gate electrode of the cell transistor is not electrically connected anywhere so as to be in a floating potential state, while a drain region thereof is connected to a source region of the selection transistor. A source line is connected to a source region of the cell transistor.
摘要翻译：存储单元具有由具有栅电极的MOS晶体管和由与选择晶体管具有相同极性的MOS晶体管构成的单元晶体管构成的选择晶体管，其结构是这两个晶体管串联连接。位线连接到选择晶体管的漏极区域，并且字线连接到其栅电极。单元晶体管的栅极电极不会在任何地方电连接，以便处于浮置电位状态，而其漏极区域连接到选择晶体管的源极区域。源极线连接到单元晶体管的源极区域。

70. 发明授权

US07095651B2 Non-volatile semiconductor memory device 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US07095651B2
公开(公告)日：2006-08-22
申请号：US11211633
申请日：2005-08-26
申请人： Riichiro Shirota , Kikuko Sugimae
发明人： Riichiro Shirota , Kikuko Sugimae
IPC分类号： G11C16/04 , G11C5/06
CPC分类号： H01L27/11526 , G11C16/0433 , H01L27/105 , H01L27/11521 , H01L27/11529 , H01L27/11558
摘要： A memory cell has a selection transistor constituted of an MOS transistor having a gate electrode and a cell transistor constituted of an MOS transistor having the same polarity as the selection transistor, in such a configuration that these two transistors are connected in series. A bit line is connected to a drain region of the selection transistor and a word line is connected to the gate electrode thereof. A gate electrode of the cell transistor is not electrically connected anywhere so as to be in a floating potential state, while a drain region thereof is connected to a source region of the selection transistor. A source line is connected to a source region of the cell transistor.
摘要翻译：存储单元具有由具有栅电极的MOS晶体管和由与选择晶体管具有相同极性的MOS晶体管构成的单元晶体管构成的选择晶体管，其结构是这两个晶体管串联连接。位线连接到选择晶体管的漏极区域，并且字线连接到其栅电极。单元晶体管的栅极电极不会在任何地方电连接，以便处于浮置电位状态，而其漏极区域连接到选择晶体管的源极区域。源极线连接到单元晶体管的源极区域。

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