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61. 发明授权

US6140674A Buried trench capacitor 失效
标题翻译：埋沟电容器
公开(公告)号：US6140674A
公开(公告)日：2000-10-31
申请号：US123117
申请日：1998-07-27
申请人： Frederick N. Hause , Mark I. Gardner , Charles E. May
发明人： Frederick N. Hause , Mark I. Gardner , Charles E. May
IPC分类号： H01L21/334 , H01L21/762 , H01L27/06 , H01L29/94 , H01L29/78 , H01L29/04
CPC分类号： H01L29/66181 , H01L21/76224 , H01L27/0623 , H01L29/945
摘要： An integrated circuit and a method of making the same are provided. The circuit includes a substrate that has a trench formed therein defining and isolating first and second active area and an upper surface. The circuit includes a capacitor that has a first insulating layer formed in the trench, a conductor layer formed on the first insulating layer, and a second insulating layer formed on the first insulating layer that fills the trench. The conductor layer is positioned substantially at or below the upper surface. The circuit integrates trench isolation structure with a capacitor that may be used as a filter between power and ground. The method integrates capacitor formation with trench isolation formation.
摘要翻译：提供集成电路及其制造方法。电路包括具有形成在其中的沟槽的衬底，其限定并隔离第一和第二有源区域和上表面。该电路包括具有形成在沟槽中的第一绝缘层的电容器，形成在第一绝缘层上的导体层，以及形成在填充沟槽的第一绝缘层上的第二绝缘层。导体层基本上位于上表面或下表面。该电路将沟槽隔离结构与可用作电源和地之间的滤波器的电容器集成。该方法集成了具有沟槽隔离形成的电容器形成。

62. 发明授权

US6114229A Polysilicon gate electrode critical dimension and drive current control in MOS transistor fabrication 有权
标题翻译：多晶硅栅极电极在MOS晶体管制造中的关键尺寸和驱动电流控制
公开(公告)号：US6114229A
公开(公告)日：2000-09-05
申请号：US196845
申请日：1998-11-20
申请人： Frederick N. Hause , Mark I. Gardner , Charles E. May
发明人： Frederick N. Hause , Mark I. Gardner , Charles E. May
IPC分类号： H01L21/28 , H01L21/20 , H01L21/3205 , H01L21/36 , H01L21/44 , H01L21/4763
CPC分类号： H01L21/28035
摘要： A method is provided for controlling the critical dimensions of a polysilicon gate electrode, and for improving transistor drive current control. The method involves subjecting the gate structure of a transistor to a thermal treatment process in the presence of hydrogen gas. The thermal treatment process is performed subsequent to gate etching and photoresist mask removal, and provides gate electrodes having a more homogeneous linewidth, thereby improving transistor performance.
摘要翻译：提供了一种用于控制多晶硅栅电极的临界尺寸并提高晶体管驱动电流控制的方法。该方法包括在氢气存在下对晶体管的栅极结构进行热处理工艺。在栅极蚀刻和光致抗蚀剂掩模去除之后进行热处理工艺，并且提供具有更均匀的线宽的栅电极，从而提高晶体管性能。

63. 发明授权

US6100146A Method of forming trench transistor with insulative spacers 失效
标题翻译：用绝缘间隔物形成沟槽晶体管的方法
公开(公告)号：US6100146A
公开(公告)日：2000-08-08
申请号：US739595
申请日：1996-10-30
申请人： Mark I. Gardner , Robert Dawson , H. Jim Fulford, Jr. , Frederick N. Hause , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
发明人： Mark I. Gardner , Robert Dawson , H. Jim Fulford, Jr. , Frederick N. Hause , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
IPC分类号： H01L21/336 , H01L29/423 , H01L29/78
CPC分类号： H01L29/7834 , H01L29/66621
摘要： An IGFET with a gate electrode and insulative spacers in a trench is disclosed. The IGFET includes a trench with opposing sidewalls and a bottom surface in a semiconductor substrate, a gate insulator on the bottom surface, a gate electrode on the gate insulator, and insulative spacers between the gate electrode and the sidewalls. A method of forming the IGFET includes implanting a doped layer into the substrate, etching completely through the doped layer and partially through the substrate to form the trench and split the doped layer into source and drain regions, depositing a blanket layer of insulative spacer material over the substrate and applying an anisotropic etch to form the insulative spacers on the sidewalls, growing the gate insulator on a central portion of the bottom surface between the insulative spacers, depositing a gate electrode material on the gate insulator and the insulative spacers, polishing the gate electrode material so that the gate electrode is substantially aligned with a top surface of the substrate, and applying a high-temperature anneal to diffuse the source and drain regions beneath the bottom surface, thereby forming a source and drain with channel junctions substantially aligned with the gate electrode. Advantageously, the channel length is significantly smaller than the trench length.
摘要翻译：公开了一种具有栅电极和沟槽中的绝缘间隔物的IGFET。 IGFET包括具有相对侧壁的沟槽和半导体衬底中的底表面，底表面上的栅极绝缘体，栅极绝缘体上的栅极电极以及栅电极和侧壁之间的绝缘间隔物。形成IGFET的方法包括将掺杂层注入到衬底中，通过掺杂层完全蚀刻并部分地穿过衬底以形成沟槽并将掺杂层分为源极和漏极区，将绝缘隔离材料的覆盖层沉积在基板并施加各向异性蚀刻以在侧壁上形成绝缘间隔物，在绝缘隔离物之间的底表面的中心部分上生长栅极绝缘体，在栅极绝缘体上沉积栅电极材料和绝缘间隔物，抛光栅极电极材料，使得栅电极基本上与衬底的顶表面对准，并施加高温退火以扩散底表面下面的源极和漏极区域，从而形成源极和漏极，其通道结基本上与栅电极。有利地，沟道长度明显小于沟槽长度。

64. 发明授权

US06080629A Ion implantation into a gate electrode layer using an implant profile displacement layer 失效
标题翻译：使用植入物轮廓位移层将离子注入到栅极电极层中
公开(公告)号：US06080629A
公开(公告)日：2000-06-27
申请号：US837579
申请日：1997-04-21
申请人： Mark I. Gardner , Robert Dawson , H. Jim Fulford, Jr. , Frederick N. Hause , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
发明人： Mark I. Gardner , Robert Dawson , H. Jim Fulford, Jr. , Frederick N. Hause , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
IPC分类号： H01L21/28 , H01L21/8238 , H01L21/336
CPC分类号： H01L21/823842 , H01L21/28035
摘要： A method for implanting a dopant into a thin gate electrode layer includes forming a displacement layer on the gate electrode layer to form a combined displacement/gate electrode layer, and implanting the dopant into the combined layer. The implanted dopant profile may substantially reside entirely within the gate electrode layer, or may substantially reside partially within the gate electrode layer and partially within the displacement layer. If the displacement layer is ultimately removed, at least some portion of the implanted dopant remains within the gate electrode layer. The gate electrode layer may be implanted before or after patterning and etching the gate electrode layer to define gate electrodes. Moreover, two different selective implants may be used to define separate regions of differing dopant concentration, such as P-type polysilicon and N-type polysilicon regions. Each region may utilize separate displacement layer thicknesses, which allows dopants of different atomic mass to use similar implant energies. A higher implant energy may be used to dope a gate electrode layer which is much thinner than normal range statistics require, without implant penetration into underlying structures.
摘要翻译：将掺杂剂注入到薄栅电极层中的方法包括在栅电极层上形成位移层以形成组合位移/栅极电极层，并将掺杂剂注入到组合层中。注入的掺杂剂分布基本上完全位于栅极电极层内，或者基本上部分地位于栅极电极层内部分地位于位移层内。如果位移层最终被去除，则注入的掺杂剂的至少一部分保留在栅电极层内。栅极电极层可以在图案化之前或之后被注入，并蚀刻栅电极层以限定栅电极。此外，可以使用两种不同的选择性植入来限定不同掺杂剂浓度的分开的区域，例如P型多晶硅和N型多晶硅区域。每个区域可以利用单独的位移层厚度，这允许不同原子质量的掺杂剂使用类似的注入能量。可以使用较高的注入能量来掺杂比正常范围统计要求更薄的栅极电极层，而不会使植入物渗入下面的结构。

65. 发明授权

US6069384A Integrated circuit including vertical transistors with spacer gates having selected gate widths 失效
标题翻译：集成电路包括具有选定栅极宽度的间隔栅极的垂直晶体管
公开(公告)号：US6069384A
公开(公告)日：2000-05-30
申请号：US811416
申请日：1997-03-04
申请人： Frederick N. Hause , Mark I. Gardner
发明人： Frederick N. Hause , Mark I. Gardner
IPC分类号： H01L21/336 , H01L21/8234 , H01L27/088 , H01L29/78 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113
CPC分类号： H01L29/66666 , H01L21/823468 , H01L21/823487 , H01L27/088 , H01L29/7827
摘要： Improvements in the compactness and performance of integrated circuit devices are gained through the fabrication of vertical transistors for which channel sizes are determined by the accuracy of etch techniques rather than the resolution of photolithographic techniques. A method of fabricating an integrated circuit includes forming a plurality of doped layers in a series of depths in a substrate wafer, and etching a trench in the substrate wafer. The trench extends through the doped layers at a plurality of depths and is bounded by vertical sidewalls and a planar horizontal floor. The method further includes forming a conductive sidewall spacer adjacent to the vertical sidewalls of the trench.
摘要翻译：通过制造垂直晶体管获得集成电路器件的紧凑性和性能的改进，其中沟道尺寸由蚀刻技术的精度而不是光刻技术的分辨率决定。制造集成电路的方法包括在衬底晶片中形成一系列深度的多个掺杂层，并蚀刻衬底晶片中的沟槽。沟槽在多个深度处延伸穿过掺杂层，并且由垂直侧壁和平面水平地板界定。该方法还包括形成与沟槽的垂直侧壁相邻的导电侧壁间隔物。

66. 发明授权

US6048785A Semiconductor fabrication method of combining a plurality of fields defined by a reticle image using segment stitching 失效
标题翻译：半导体制造方法，其使用片段拼接来组合由标线片图像定义的多个场
公开(公告)号：US6048785A
公开(公告)日：2000-04-11
申请号：US876628
申请日：1997-06-16
申请人： H. Jim Fulford, Jr. , Robert Dawson , Mark I. Gardner , Frederick N. Hause , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
发明人： H. Jim Fulford, Jr. , Robert Dawson , Mark I. Gardner , Frederick N. Hause , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
IPC分类号： H01L21/768 , H01L21/4763
CPC分类号： H01L21/76895 , Y10S438/946 , Y10S438/949
摘要： Each region of multiple regions on a semiconductor substrate is imaged in an exposure field defined by a reticle. The regions are separated and electrically isolated within the semiconductor substrate by an isolation such as a field oxide or trench isolation. The regions are interconnected by imaging using a stitching reticle having an exposure field overlapping a plurality of the regions. The combination of reticle-imaged fields effectively increases the size of a field formed using a step and repeat technique while achieving high imaging resolution within the combined regions. Similarly, a plurality of integrated chip sets, including microprocessor, memory, and support chips, are constructed on a single semiconductor wafer using separate reticle imaging of each of the plurality of integrated chip sets. The different circuits are interconnected using a stitch mask and etch operation that combines the regions.
摘要翻译：在半导体衬底上的多个区域的每个区域以由掩模版定义的曝光区域成像。这些区域通过诸如场氧化物或沟槽隔离的隔离在半导体衬底内分离和电隔离。这些区域通过使用具有与多个区域重叠的曝光场的拼接掩模版进行成像来互连。掩模版成像场的组合有效地增加了使用步骤和重复技术形成的场的大小，同时在组合区域内实现高成像分辨率。类似地，使用多个集成芯片组中的每一个的单独掩模版成像，在单个半导体晶片上构造包括微处理器，存储器和支持芯片的多个集成芯片组。使用组合这些区域的针迹掩模和蚀刻操作来使不同的电路互连。

67. 发明授权

US6037244A Method of manufacturing a semiconductor device using advanced contact formation 失效
标题翻译：使用高级接触形成制造半导体器件的方法
公开(公告)号：US6037244A
公开(公告)日：2000-03-14
申请号：US821660
申请日：1997-03-19
申请人： Mark I. Gardner , Thomas E. Spikes, Jr. , Robert Paiz , Frederick N. Hause , Sey-Ping Sun
发明人： Mark I. Gardner , Thomas E. Spikes, Jr. , Robert Paiz , Frederick N. Hause , Sey-Ping Sun
IPC分类号： H01L21/768 , H01L21/28 , H01L21/31
CPC分类号： H01L21/76895 , H01L21/76807
摘要： A method of forming a semiconductor device by using a pillar to form a contact with an active region of the device. A semiconductor device is formed by forming one or more active regions on a substrate of the semiconductor device and forming a pillar over at least a portion of one of the active regions. An insulating film selective to the pillar is provided over portions of the substrate adjacent the pillar. The pillar is then used to form a conductive contact with the active region over which it is formed. In one embodiment, the pillar is formed from a photoresist, while in other embodiments, the pillar is formed from a conductor material such as a metal. The active region may form a source/drain region or a gate electrode.
摘要翻译：一种通过使用柱形成与器件的有源区的接触形成半导体器件的方法。通过在半导体器件的衬底上形成一个或多个有源区并在一个有源区的至少一部分上形成柱来形成半导体器件。在基板的邻近柱的部分上设置对柱子有选择性的绝缘膜。然后使用该柱与其形成的有源区形成导电接触。在一个实施例中，柱由光致抗蚀剂形成，而在其它实施例中，柱由诸如金属的导体材料形成。有源区可以形成源/漏区或栅电极。

68. 发明授权

US5976938A Method of making enhancement-mode and depletion-mode IGFETs with different gate thicknesses 失效
标题翻译：制造具有不同栅极厚度的增强型和耗尽型IGFET的方法
公开(公告)号：US5976938A
公开(公告)日：1999-11-02
申请号：US844925
申请日：1997-04-21
申请人： Mark I. Gardner , Frederick N. Hause
发明人： Mark I. Gardner , Frederick N. Hause
IPC分类号： H01L21/8236
CPC分类号： H01L21/8236
摘要： A method of making enhancement-mode and depletion-mode IGFETs with different gate thicknesses is disclosed. The method includes providing a semiconductor substrate with first and second device regions, forming a first gate with a first thickness over the first device region, forming a second gate with a second thickness over the second device region, wherein the second thickness is substantially greater than the first thickness, implanting a dopant into the substrate and into the first and second gates to implant source and drain regions in the first device region and source and drain regions in the second device region, and transferring the dopant through the first gate into a first channel region in the first device region beneath the first gate without transferring essentially any of the dopant through the second gate into a second channel region in the second device region beneath the second gate, thereby providing depletion-mode doping in the first channel region while retaining enhancement-mode doping in the second channel region. The dopant can be implanted through the first gate into the first channel region. Alternatively, the dopant can be implanted into the first gate but not the first channel region and then diffused from the first gate into the first channel region. Advantageously, by employing different gate thicknesses, a single implant step can be used to provide lightly doped source/drain regions for enhancement and depletion-mode IGFETs as well as depletion-mode doping for channel regions of depletion-mode IGFETs (with thin gates) while retaining enhancement-mode doping for channel regions of enhancement-mode IGFETs (with thick gates).
摘要翻译：公开了一种制造具有不同栅极厚度的增强型和耗尽型IGFET的方法。该方法包括向半导体衬底提供第一和第二器件区域，在第一器件区域上形成具有第一厚度的第一栅极，在第二器件区域上形成具有第二厚度的第二栅极，其中第二厚度基本上大于第一厚度，将掺杂剂注入到衬底中并进入第一和第二栅极，以在第一器件区域和第二器件区域中的源极和漏极区域中注入源极和漏极区域，并将掺杂剂通过第一栅极转移到第一在第一栅极下方的第一器件区域中的沟道区域，而不将基本上任何掺杂剂通过第二栅极转移到第二栅极下面的第二器件区域中的第二沟道区域中，由此在第一沟道区域中提供耗尽模式掺杂，同时保留在第二通道区域中的增强型掺杂。掺杂剂可以通过第一栅极注入第一沟道区。或者，可以将掺杂剂注入第一栅极而不是第一沟道区，然后从第一栅极扩散到第一沟道区。有利地，通过采用不同的栅极厚度，可以使用单个注入步骤来提供用于增强和耗尽型IGFET的轻掺杂源极/漏极区域以及耗尽型IGFET（具有薄栅极）的沟道区域的耗尽模式掺杂，同时保持增强型IGFET（具有厚栅极）的沟道区域的增强型掺杂。

69. 发明授权

US5937299A Method for forming an IGFET with silicide source/drain contacts in close proximity to a gate with sloped sidewalls 失效
标题翻译：用于形成具有硅化物源极/漏极接触的IGFET的方法，其紧邻具有倾斜侧壁的栅极
公开(公告)号：US5937299A
公开(公告)日：1999-08-10
申请号：US837522
申请日：1997-04-21
申请人： Mark W. Michael , Robert Dawson , H. Jim Fulford, Jr. , Mark I. Gardner , Frederick N. Hause , Bradley T. Moore , Derick J. Wristers
发明人： Mark W. Michael , Robert Dawson , H. Jim Fulford, Jr. , Mark I. Gardner , Frederick N. Hause , Bradley T. Moore , Derick J. Wristers
IPC分类号： H01L21/28 , H01L21/336 , H01L29/08 , H01L29/417 , H01L29/423
CPC分类号： H01L29/6659 , H01L21/28114 , H01L29/0847 , H01L29/41775 , H01L29/42376 , H01L29/66628 , H01L29/665
摘要： An IGFET with source and drain contacts in close proximity to a gate with sloped sidewalls is disclosed. A method of making the IGFET includes forming a gate over a semiconductor substrate, wherein the gate includes a top surface, a bottom surface and opposing sidewalls, and the top surface has a substantially greater length than the bottom surface, forming a source and a drain that extend into the substrate, depositing a contact material over the gate, source and drain, and forming a gate contact on the gate, a source contact on the source, and a drain contact on the drain. The gate is separated from the source and drain contacts due to a retrograde slope of the gate sidewalls, and the gate contact is separated from the source and drain contacts due to a lack of step coverage in the contact material. Preferably, the contact material is a refractory metal, and the contacts are formed by converting the refractory metal into a silicide. In this manner, a highly miniaturized IGFET can be provided with densely-packed gate, source and drain contacts without the need for sidewall spacers adjacent to the gate.
摘要翻译：公开了具有源极和漏极触点的IGFET，其紧邻具有倾斜侧壁的栅极。制造IGFET的方法包括在半导体衬底上形成栅极，其中栅极包括顶表面，底表面和相对的侧壁，并且顶表面具有比底表面大得多的长度，形成源极和漏极延伸到衬底中，在栅极，源极和漏极上沉积接触材料，以及在栅极上形成栅极接触，源极上的源极接触和漏极上的漏极接触。由于栅极侧壁的逆向斜坡，栅极与源极和漏极接触分离，并且由于接触材料中缺少台阶覆盖，栅极接触与源极和漏极接触分离。优选地，接触材料是难熔金属，并且通过将难熔金属转化为硅化物形成触点。以这种方式，高度小型化的IGFET可以设置有密集封装的栅极，源极和漏极接触，而不需要邻近栅极的侧壁间隔。

70. 发明授权

US5933717A Vertical transistor interconnect structure and fabrication method thereof 失效
标题翻译：垂直晶体管互连结构及其制造方法
公开(公告)号：US5933717A
公开(公告)日：1999-08-03
申请号：US811381
申请日：1997-03-04
申请人： Frederick N. Hause , Mark I. Gardner
发明人： Frederick N. Hause , Mark I. Gardner
IPC分类号： H01L21/768 , H01L21/8234 , H01L27/088 , H01L21/8238
CPC分类号： H01L21/823487 , H01L21/768 , H01L27/088
摘要： It has been discovered that improvements in the compactness and performance of integrated circuit devices are gained through the fabrication of vertical transistors for which channel sizes are determined by the accuracy of etch techniques rather than the resolution of photolithographic techniques. Etching in the vertical dimension is precisely controlled to resolutions of about 0.1 .mu.m while advanced photolithographic techniques in a volume production environment achieve resolutions of 0.25 .mu.m. Interconnect structures for connecting to high density vertical transistors are formed by depositing metal into the trenches etched during fabrication of the vertical transistors. A method of fabricating an integrated circuit includes etching a trench with a sidewall in a substrate wafer and forming a vertical transistor on the sidewall. The vertical transistor has a drain, a channel and a source doped at a series of vertical depths in the substrate wafer. The transistor has a gate coupled to the sidewall adjacent to the drain, the channel, and the source. The method of fabricating an integrated circuit further includes forming an interconnect in the trench coupled to the vertical transistor. An integrated circuit includes a substrate wafer having a trench with a sidewall and a vertical transistor formed on the sidewall of the trench. The vertical transistor has a drain, a channel and a source doped at a series of vertical depths in the substrate wafer. The vertical transistor has a gate coupled to the sidewall adjacent to the drain, the channel, and the source. The integrated circuit further includes an interconnect in the trench coupled to the vertical transistor.
摘要翻译：已经发现，通过制造垂直晶体管来获得集成电路器件的紧凑性和性能的改进，其中沟道尺寸由蚀刻技术的精度而不是光刻技术的分辨率确定。在垂直尺寸上的蚀刻被精确地控制在约0.1μm的分辨率上，而在批量生产环境中的先进的光刻技术实现了0.25μm的分辨率。用于连接到高密度垂直晶体管的互连结构通过在垂直晶体管的制造过程中蚀刻的沟槽中沉积金属而形成。制造集成电路的方法包括：在衬底晶片中蚀刻具有侧壁的沟槽，并在侧壁上形成垂直晶体管。垂直晶体管具有在衬底晶片中的一系列垂直深度处掺杂的漏极，沟道和源极。晶体管具有与漏极，沟道和源极相邻的侧壁耦合的栅极。制造集成电路的方法还包括在与垂直晶体管耦合的沟槽中形成互连。集成电路包括具有侧壁沟槽和形成在沟槽侧壁上的垂直晶体管的衬底晶片。垂直晶体管具有在衬底晶片中的一系列垂直深度处掺杂的漏极，沟道和源极。垂直晶体管具有与漏极，沟道和源极相邻的侧壁耦合的栅极。该集成电路还包括在与该垂直晶体管耦合的沟槽中的互连。

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