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    • 65. 发明授权
    • Power amplifier for amplifying high-frequency (H.F.) signals
    • 用于放大高频(H.F.)信号的功率放大器
    • US07551036B2
    • 2009-06-23
    • US11719893
    • 2005-11-10
    • Manfred BerrothLei Wu
    • Manfred BerrothLei Wu
    • H03F3/04
    • H03F3/195H03F1/0277H03F1/223H03F1/52H03F1/523H03F3/211H03F3/423H03F3/604H03F3/72H03F2200/451H03F2203/7215
    • An H.F. power amplifier is disclosed having a plurality of branches (10, 11, 12) switched in parallel. Each branch comprises a plurality of amplifier elements (T1, T4) switched in series. Resistors (R2, R5) enable the voltage (U_DS) applied to the amplifier elements (T1, T4) to be set at a fraction of a supply voltage (Ud) applied to the branches (10, 11, 12). Capacitors (C2, C4) are used to adjust the source impedance of the amplifier elements (T2, T4). In order to prevent the gate-drain voltage (U_GD) from exceeding the breakdown voltage of an amplifier element (T1, T4) and damaging the amplifier element (T1, T4), a limiting path (7) is connected according to the invention between the gate terminal (G) and the drain terminal (D) of the amplifier element (T1, T4), the limiting path (7) being switchable between a conducting state and a blocking state depending on the gate-drain voltage (U_GD).
    • 公开了具有并行切换的多个分支(10,11,12)的功率放大器。 每个分支包括串联切换的多个放大器元件(T1,T4)。 电阻器(R2,R5)使得施加到放大器元件(T1,T4)的电压(U_DS)被设置为施加到分支(10,11,12)的电源电压(Ud)的一小部分。 电容器(C2,C4)用于调节放大器元件(T2,T4)的源阻抗。 为了防止栅极 - 漏极电压(U_GD)超过放大器元件(T1,T4)的击穿电压并损坏放大器元件(T1,T4),根据本发明,限制路径(7)连接在 放电元件(T1,T4)的栅极端子(G)和漏极端子(D),限制路径(7)可根据栅极 - 漏极电压(U_GD)在导通状态和阻塞状态之间切换。
    • 68. 发明授权
    • Apparatus for clock data recovery
    • 时钟数据恢复装置
    • US07295644B1
    • 2007-11-13
    • US10619278
    • 2003-07-14
    • Lei WuHenri Sutioso
    • Lei WuHenri Sutioso
    • H03D3/24
    • H03L7/0807H03L7/0891H03L7/093
    • Circuits, architectures, a system and methods for clock data recovery. The circuit generally includes (a) a clock phase adjustment circuit, receiving clock phase information and providing a clock phase adjustment signal, (b) a clock frequency adjustment circuit, receiving clock frequency information and providing a clock frequency adjustment signal, and (c) an adder circuit, receiving the clock phase adjustment signal and the clock frequency adjustment signal, and providing a clock recovery adjustment signal. The architectures and/or systems generally comprise those that include a clock data recovery circuit embodying one or more of the inventive concepts disclosed herein. The method generally comprises the steps of (1) sampling the data stream at predetermined times, (2) generating clock frequency information and clock phase information from sampled data, and (3) altering a frequency and/or a phase of the clock signal in response to the clock frequency information and the clock phase information. The present invention prevents or reduces the likelihood of the potential nonconvergence/clock runaway problem, advantageously with minimal or no changes to existing designs and logic. The present invention further advantageously improves system stability, reliability and performance with a minimum of additional circuitry.
    • 电路,架构,时钟数据恢复的系统和方法。 电路通常包括(a)时钟相位调整电路,接收时钟相位信息并提供时钟相位调整信号,(b)时钟频率调整电路,接收时钟频率信息和提供时钟频率调整信号,以及(c) 加法电路,接收时钟相位调整信号和时钟频率调整信号,并提供时钟恢复调整信号。 架构和/或系统通常包括包括体现本文公开的一个或多个本发明构思的时钟数据恢复电路的结构和/或系统。 该方法通常包括以下步骤:(1)在预定时间对数据流进行采样,(2)从采样数据生成时钟频率信息和时钟相位信息,以及(3)改变时钟信号的频率和/ 响应于时钟频率信息和时钟相位信息。 本发明防止或减少潜在的非会聚/时钟失控问题的可能性,有利地是对现有设计和逻辑的最小化或不变化。 本发明进一步有利地利用最小的附加电路提高了系统稳定性,可靠性和性能。