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61. 发明授权

US07343095B2 Optical interleaver 有权
标题翻译：光交织器
公开(公告)号：US07343095B2
公开(公告)日：2008-03-11
申请号：US10862827
申请日：2004-06-07
申请人： Ying Zhang , Qi Jie Wang , Yeng Chai Soh
发明人： Ying Zhang , Qi Jie Wang , Yeng Chai Soh
IPC分类号： H04J14/02
CPC分类号： G02B6/29338 , G02B6/2861 , G02B6/29353 , G02B6/29356 , G02B6/29386 , G02B2006/2865
摘要： An optical interleaver comprising a first optical 3×3 coupler for receiving a broadband optical signal at one input port thereof, a second 3×3 optical coupler, three differential delay lines connected in parallel port-to-port between output ports of the first optical 3×3 coupler and input ports of the second optical 3×3 coupler, an infinite impulse response (IIR) element disposed in each of two of the delay lines, and wherein optical signals travelling in the respective delay lines interfere at the second 3×3 coupler to produce three frequency shifted transmission channel output signals at respective output ports of the second 3×3 coupler.
摘要翻译：一种光学交织器，包括用于在其一个输入端口处接收宽带光信号的第一光学3x3耦合器，第二3×3光耦合器，在第一光学3x3耦合器的输出端口和输入端之间并行连接到端口的端口的三个差分延迟线第二光学3x3耦合器的端口，设置在两个延迟线中的每一个中的无限脉冲响应（IIR）元件，并且其中在各个延迟线中行进的光信号在第二3x3耦合器处干扰以产生三个频移传输信道输出信号在第二3x3耦合器的相应输出端口处。

62. 发明申请

US20080010286A1 Server bookmarks 有权
标题翻译：服务器书签
公开(公告)号：US20080010286A1
公开(公告)日：2008-01-10
申请号：US11327644
申请日：2006-01-09
申请人： Ying Zhang , Jeffrey Korn
发明人： Ying Zhang , Jeffrey Korn
IPC分类号： G06F17/30
CPC分类号： G06F17/30884
摘要： A system receives, at a server, an action request from a client associated with bookmarks, where the bookmarks identify user designated documents. The system accesses bookmark records stored at the server based on the action request and acting on the bookmark records in a manner specified by the action request.
摘要翻译：系统在服务器处接收来自与书签相关联的客户端的动作请求，其中书签识别用户指定的文档。系统根据动作请求访问存储在服务器上的书签记录，并以动作请求指定的方式对书签记录进行操作。

63. 发明申请

US20070140149A1 Method and apparatus for optimizing convergecast operations in a wireless sensor network 有权
标题翻译：用于优化无线传感器网络中的收敛操作的方法和装置
公开(公告)号：US20070140149A1
公开(公告)日：2007-06-21
申请号：US11314616
申请日：2005-12-20
申请人： Shashidhar Gandham , Ying Zhang , Qingfeng Huang
发明人： Shashidhar Gandham , Ying Zhang , Qingfeng Huang
IPC分类号： H04L12/28
CPC分类号： H04L43/00 , H04L43/0888 , H04W84/18
摘要： One embodiment of the present invention provides a system that optimizes packet transmissions during a convergecast operation in a convergecast network. During operation, the system receives a request to perform the convergecast operation in the convergecast network. This convergecast network includes a base-station and a plurality of nodes, wherein during the convergecast operation the plurality of nodes communicate packets to the base-station. In response to the request, the system constructs a convergecast-tree, which includes the base-station and the plurality of nodes, based on hop counts from the plurality of nodes to the base-station. Next, the system linearizes the convergecast-tree so that the convergecast-tree contains a plurality of linear branches. The system then schedules packet transmission for each of the linear branches and each node in each branch based on a set of predetermined criteria to obtain a scheduled order. Finally, the system performs packet transmissions in the convergecast-tree using the scheduled order. Note that performing the convergecast operation in this way substantially optimizes the convergecast operation by reducing a total number of timeslots required to complete the convergecast operation.
摘要翻译：本发明的一个实施例提供了一种在收敛网络中的收敛过程中优化分组传输的系统。在运行期间，系统接收到在Convergecast网络中执行Convergecast操作的请求。该Convergecast网络包括基站和多个节点，其中在Convergecast操作期间，多个节点向基站传送分组。响应于该请求，系统基于从多个节点到基站的跳数来构建包括基站和多个节点的Convergecast-tree。接下来，系统使收敛树线性化，使得收敛树包含多个线性分支。然后，系统基于一组预定标准来调度每个分支中的每个线性分支和每个节点的分组传输以获得调度顺序。最后，系统使用调度顺序在convergecast-tree中执行分组传输。注意，以这种方式执行Convergecast操作通过减少完成Convergecast操作所需的时隙的总数大大优化了Convergecast操作。

64. 发明授权

US07211490B2 Ultra thin channel MOSFET 失效
标题翻译：超薄通道MOSFET
公开(公告)号：US07211490B2
公开(公告)日：2007-05-01
申请号：US11083743
申请日：2005-03-18
申请人： Bruce B. Doris , Thomas S. Kanarsky , Ying Zhang , Huilong Zhu , Meikei Ieong , Omer Dokumaci
发明人： Bruce B. Doris , Thomas S. Kanarsky , Ying Zhang , Huilong Zhu , Meikei Ieong , Omer Dokumaci
IPC分类号： H01L21/336 , H01L29/76
CPC分类号： H01L29/66772 , H01L21/84 , H01L27/1203 , H01L29/6656 , H01L29/78612 , H01L29/78621
摘要： Described is a method for making thin channel silicon-on-insulator structures. The inventive method comprises forming a set of thin spacer abutting a gate region in a first device and a second device region; forming a raised source/drain region on either side of the gate region in the first device region and the second device region, implanting dopants of a first conductivity type into the raised source drain region in the first device region to form a first dopant impurity region, where the second device region is protected by a second device region block mask; implanting dopants of a second conductivity type into the raised source/drain region in the second device region to form a second dopant impurity region, where the first device region is protected by a first device region block mask; and activating the first dopant impurity region and the second dopant impurity region to provide a thin channel MOSFET.
摘要翻译：描述了制造薄沟道硅绝缘体上结构的方法。本发明的方法包括在第一装置和第二装置区域中形成邻接栅极区的一组薄间隔件; 在第一器件区域和第二器件区域中的栅极区域的任一侧上形成凸起的源极/漏极区域，将第一导电类型的掺杂剂注入到第一器件区域中的凸起的源极漏极区域中以形成第一掺杂剂杂质区域，其中所述第二设备区域被第二设备区域块掩码保护; 将第二导电类型的掺杂剂注入所述第二器件区域中的所述升高的源极/漏极区域中以形成第二掺杂剂杂质区域，其中所述第一器件区域被第一器件区域阻挡掩模保护; 以及激活第一掺杂杂质区和第二掺杂杂质区，以提供薄沟道MOSFET。

65. 发明申请

US20060287456A1 Braided comb-shaped salt-resistant polymer thickening agent 有权
标题翻译：编织梳形耐盐聚合物增稠剂
公开(公告)号：US20060287456A1
公开(公告)日：2006-12-21
申请号：US11447035
申请日：2006-06-06
申请人： Shiyi Yuan , Jianhui Luo , Ruoying Pu , Yuzhang Liu , Huaijiang Zhu , Pingmei Wang , Chunming Xiong , Ying Zhang , Fengluan Bai , Jingbo Yang
发明人： Shiyi Yuan , Jianhui Luo , Ruoying Pu , Yuzhang Liu , Huaijiang Zhu , Pingmei Wang , Chunming Xiong , Ying Zhang , Fengluan Bai , Jingbo Yang
IPC分类号： C08F228/02
CPC分类号： C08F222/02 , C08F220/06 , C08F220/20 , C08F220/56 , C08F220/58 , C08F228/02 , C09K8/588
摘要： A braided comb-shaped salt-resistant thickening agent for tertiary oil extraction from class I oil reservoir is disclosed. The agent is polymerized with monomer (A) and monomer (B), and monomer (A) is one or multiple water soluble non-saturated compound(s) with alkenyl chain, while monomer (B) is at least one compound with the following formula: Monomer (A) is preferably acrylamide, ethenyl pyrrolidone, 2-acrylamide-2 methylpropane sulfonic acid, and acrylic acid or the mixture of the above said compounds, and in the formula of monomer (B), A is COOH, OH, SO3H, R1 and R2 are H or C1-C12 alkyl, R3 and R4 represent C1-C12 alkyl, C1-C12 alkylaryl, C1-C12 alkyl ether or C1-C12 alkyl ester group. This thickening agent has fine water solubility and good property to thicken water medium. The polymer's molecules present a braided comb-shaped structure in water solution with fine salt-resistant performances. The agent can be used together with the water extracted from oil mines to compound the polymer for tertiary oil extraction, and the polymer solution's viscosity can reach the level of the comb-shaped salt-resistant polymer solution applied in class I oil reservoir, so it can promote the economic benefits of tertiary oil extraction from class II oil reservoir and expand the application scope.
摘要翻译：公开了一种用于三级油从I类油藏提取的编织梳形耐盐增稠剂。该试剂与单体（A）和单体（B）聚合，单体（A）是具有烯基链的一种或多种水溶性非饱和化合物，而单体（B）是至少一种具有下列化合物的化合物式（A）优选为丙烯酰胺，乙烯基吡咯烷酮，2-丙烯酰胺-2-甲基丙烷磺酸，丙烯酸或上述化合物的混合物，在式（B）中，A为COOH，OH， SO 3 H，R 1和R 2均为H或C 1 -C 12烷基， C 1 -C 4烷基，R 3和R 4代表C 1 -C 12烷基，C 1〜 C 1 -C 12烷基芳基，C 1 -C 12烷基醚或C 1 -C 3烷基芳基，烷基酯基团。该增稠剂具有良好的水溶性和对增稠水介质的良好性能。聚合物的分子在水溶液中呈现编织梳状结构，具有良好的耐盐性能。该试剂可以与从油矿提取的水一起使用，将聚合物复合，用于三级油萃取，聚合物溶液的粘度可以达到应用于I级油藏的梳状耐盐聚合物溶液的水平，因此可以促进二级油藏三级采油的经济效益，扩大应用范围。

66. 发明授权

US07091566B2 Dual gate FinFet 有权
标题翻译：双门FinFet
公开(公告)号：US07091566B2
公开(公告)日：2006-08-15
申请号：US10717737
申请日：2003-11-20
申请人： Huilong Zhu , Jochen Beintner , Bruce B. Doris , Ying Zhang
发明人： Huilong Zhu , Jochen Beintner , Bruce B. Doris , Ying Zhang
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/785 , H01L29/66795 , H01L29/7856
摘要： A field effect transistor (FET), integrated circuit (IC) chip including the FETs and a method of forming the FETS. Each FET includes a device gate along one side of a semiconductor (e.g., silicon) fin and a back bias gate along an opposite of the fin. Back bias gate dielectric differs from the device gate dielectric either in its material and/or thickness. Device thresholds can be adjusted by adjusting back bias gate voltage.
摘要翻译：包括FET的场效应晶体管（FET），集成电路（IC）芯片和形成FET的方法。每个FET包括沿半导体（例如，硅）翅片的一侧的器件栅极和沿鳍片相对的背偏置栅极。背偏置栅极电介质的不同之处在于器件栅极电介质的材料和/或厚度。可以通过调整背偏置栅极电压来调整器件阈值。

67. 发明申请

US20050164468A1 Selective silicon-on-insulator isolation structure and method 有权
公开(公告)号：US20050164468A1
公开(公告)日：2005-07-28
申请号：US11082993
申请日：2005-03-17
申请人： An Steegen , Maheswaran Surendra , Hsing-Jen Wann , Ying Zhang , Franz Zach , Robert Wong
发明人： An Steegen , Maheswaran Surendra , Hsing-Jen Wann , Ying Zhang , Franz Zach , Robert Wong
IPC分类号： H01L21/336 , H01L21/76 , H01L21/8234 , H01L21/8238 , H01L21/8242 , H01L21/84 , H01L27/12 , H01L29/76 , H01L31/062
CPC分类号： H01L29/66651 , H01L21/823481 , H01L21/823878 , H01L21/84 , H01L27/1203 , H01L29/0653 , H01L29/66772
摘要： A first aspect of the present invention is a method of forming an isolation structure including: (a) providing a semiconductor substrate; (b) forming a buried N-doped region in the substrate; (c) forming a vertical trench in the substrate, the trench extending into the N-doped region; (d) removing the N-doped region to form a lateral trench communicating with and extending perpendicular to the vertical trench; and (e) at least partially filling the lateral trench and filling the vertical trench with one or more insulating materials.

68. 发明申请

US20050093076A1 METHOD AND STRUCTURE FOR FORMING STRAINED Si FOR CMOS DEVICES 失效
标题翻译：用于形成用于CMOS器件的应变Si的方法和结构
公开(公告)号：US20050093076A1
公开(公告)日：2005-05-05
申请号：US10605906
申请日：2003-11-05
申请人： An Steegen , Haining Yang , Ying Zhang
发明人： An Steegen , Haining Yang , Ying Zhang
IPC分类号： H01L21/20 , H01L21/265 , H01L21/336 , H01L21/762 , H01L21/8238 , H01L29/10 , H01L29/78 , H01L29/06 , C30B1/00 , H01L31/0328
CPC分类号： H01L29/7833 , H01L21/02381 , H01L21/0243 , H01L21/02532 , H01L21/02658 , H01L21/26506 , H01L21/76224 , H01L21/76232 , H01L21/76283 , H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L29/1054 , H01L29/665 , H01L29/66575 , H01L29/78 , H01L29/7842 , H01L29/7846 , H01L29/7849
摘要： A method for manufacturing a device including an n-type device and a p-type device. In an aspect of the invention, the method involves doping a portion of a semiconductor substrate and forming a gap in the semiconductor substrate by removing at least a portion of the doped portion of the semiconductor substrate. The method further involves growing a strain layer in at least a portion of the gap in the semiconductor substrate. For the n-type device, the strain layer is grown on at least a portion which is substantially directly under a channel of the n-type device. For the p-type device, the strain layer is grown on at least a portion which is substantially directly under a source region or drain region of the p-type device and not substantially under a channel of the p-type device.
摘要翻译：一种制造包括n型器件和p型器件的器件的方法。在本发明的一个方面，该方法包括通过去除半导体衬底的掺杂部分的至少一部分来掺杂半导体衬底的一部分并在半导体衬底中形成间隙。该方法还包括在半导体衬底中的间隙的至少一部分中生长应变层。对于n型器件，应变层在基本上直接位于n型器件的沟道下方的至少一部分上生长。对于p型器件，应变层生长在基本上直接位于p型器件的源极区域或漏极区域的部分上，并且基本上不在p型器件的沟道下生长。

69. 发明授权

US06876040B1 Dense SRAM cells with selective SOI 失效
标题翻译：具有选择性SOI的密集SRAM单元
公开(公告)号：US06876040B1
公开(公告)日：2005-04-05
申请号：US10735169
申请日：2003-12-12
申请人： Hsingjen Wann , Ying Zhang , Robert C. Wong , An Steegen
发明人： Hsingjen Wann , Ying Zhang , Robert C. Wong , An Steegen
IPC分类号： H01L21/8244 , H01L21/84 , H01L27/11 , H01L27/12 , H01L27/01 , H01L29/76 , H01L29/94 , H01L31/0392
CPC分类号： H01L27/1207 , H01L21/84 , H01L27/11 , H01L27/1104 , Y10S257/903
摘要： A SRAM cell fabricated in SSOI (selective silicon on insulator) comprises cross coupled PFET pull-up devices P1, P2 and NFET pull-down devices N1, N2, with the P1, P2 devices being connected to the power supply and the N1, N2 devices being connected to the ground. A first passgate NL is coupled between a first bitline and the junction of the devices P1 and N1, with its gate coupled to a wordline, and a second passgate NR is coupled between a second bitline and the junction of devices P2 and N2, with its gate coupled to the wordline. Each of the pull-up devices P1, P2, the pull-down devices N1, N2, and the first and second passgates NL, NR are fabricated with selective SOI, with buried oxide being selectively provided under the drains of the pull-up devices P1 and P2, the drains of the pull-down devices N1 and N2, and the sources and drains of the passgate devices NL and NR.
摘要翻译：在SSOI（选择性绝缘体硅）上制造的SRAM单元包括交叉耦合的PFET上拉器件P1，P2和NFET下拉器件N1，N2，其中P1，P2器件连接到电源，N1，N2 设备连接到地面。第一通路门NL耦合在第一位线和器件P1和N1的接点之间，其栅极耦合到字线，并且第二通路门NR耦合在第二位线和器件P2和N2的接点之间，其中门连接到字线。上拉器件P1，P2，下拉器件N1，N2以及第一和第二通路NL，NR中的每一个被制造成具有选择性SOI，其中掩埋氧化物选择性地设置在上拉器件的漏极下 P1和P2，下拉装置N1和N2的下水道，以及通道装置NL和NR的源极和漏极。

70. 发明申请

US20050048752A1 Ultra thin channel MOSFET 有权
标题翻译：超薄通道MOSFET
公开(公告)号：US20050048752A1
公开(公告)日：2005-03-03
申请号：US10650229
申请日：2003-08-28
申请人： Bruce Doris , Thomas Kanarsky , Ying Zhang , Huilong Zhu , Meikei Ieong , Omer Dokumaci
发明人： Bruce Doris , Thomas Kanarsky , Ying Zhang , Huilong Zhu , Meikei Ieong , Omer Dokumaci
IPC分类号： H01L21/336 , H01L21/84 , H01L27/12 , H01L29/786 , H01L21/3205
CPC分类号： H01L29/66772 , H01L21/84 , H01L27/1203 , H01L29/6656 , H01L29/78612 , H01L29/78621
摘要： Described is a method for making thin channel silicon-on-insulator structures. The inventive method comprises forming a set of thin spacer abutting a gate region in a first device and a second device region; forming a raised source/drain region on either side of the gate region in the first device region and the second device region, implanting dopants of a first conductivity type into the raised source drain region in the first device region to form a first dopant impurity region, where the second device region is protected by a second device region block mask; implanting dopants of a second conductivity type into the raised source/drain region in the second device region to form a second dopant impurity region, where the first device region is protected by a first device region block mask; and activating the first dopant impurity region and the second dopant impurity region to provide a thin channel MOSFET.
摘要翻译：描述了制造薄沟道硅绝缘体上结构的方法。本发明的方法包括在第一装置和第二装置区域中形成邻接栅极区的一组薄间隔件; 在第一器件区域和第二器件区域中的栅极区域的任一侧上形成凸起的源极/漏极区域，将第一导电类型的掺杂剂注入到第一器件区域中的凸起的源极漏极区域中以形成第一掺杂剂杂质区域，其中所述第二设备区域被第二设备区域块掩码保护; 将第二导电类型的掺杂剂注入所述第二器件区域中的所述升高的源极/漏极区域中以形成第二掺杂剂杂质区域，其中所述第一器件区域被第一器件区域阻挡掩模保护; 以及激活第一掺杂杂质区和第二掺杂杂质区，以提供薄沟道MOSFET。

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