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1. 发明申请

US20050093076A1 METHOD AND STRUCTURE FOR FORMING STRAINED Si FOR CMOS DEVICES 失效
标题翻译：用于形成用于CMOS器件的应变Si的方法和结构
公开(公告)号：US20050093076A1
公开(公告)日：2005-05-05
申请号：US10605906
申请日：2003-11-05
申请人： An Steegen , Haining Yang , Ying Zhang
发明人： An Steegen , Haining Yang , Ying Zhang
IPC分类号： H01L21/20 , H01L21/265 , H01L21/336 , H01L21/762 , H01L21/8238 , H01L29/10 , H01L29/78 , H01L29/06 , C30B1/00 , H01L31/0328
CPC分类号： H01L29/7833 , H01L21/02381 , H01L21/0243 , H01L21/02532 , H01L21/02658 , H01L21/26506 , H01L21/76224 , H01L21/76232 , H01L21/76283 , H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L29/1054 , H01L29/665 , H01L29/66575 , H01L29/78 , H01L29/7842 , H01L29/7846 , H01L29/7849
摘要： A method for manufacturing a device including an n-type device and a p-type device. In an aspect of the invention, the method involves doping a portion of a semiconductor substrate and forming a gap in the semiconductor substrate by removing at least a portion of the doped portion of the semiconductor substrate. The method further involves growing a strain layer in at least a portion of the gap in the semiconductor substrate. For the n-type device, the strain layer is grown on at least a portion which is substantially directly under a channel of the n-type device. For the p-type device, the strain layer is grown on at least a portion which is substantially directly under a source region or drain region of the p-type device and not substantially under a channel of the p-type device.
摘要翻译：一种制造包括n型器件和p型器件的器件的方法。在本发明的一个方面，该方法包括通过去除半导体衬底的掺杂部分的至少一部分来掺杂半导体衬底的一部分并在半导体衬底中形成间隙。该方法还包括在半导体衬底中的间隙的至少一部分中生长应变层。对于n型器件，应变层在基本上直接位于n型器件的沟道下方的至少一部分上生长。对于p型器件，应变层生长在基本上直接位于p型器件的源极区域或漏极区域的部分上，并且基本上不在p型器件的沟道下生长。

2. 发明申请

US20080003735A1 METHOD AND STRUCTURE FOR FORMING STRAINED SI FOR CMOS DEVICES 失效
公开(公告)号：US20080003735A1
公开(公告)日：2008-01-03
申请号：US11854829
申请日：2007-09-13
申请人： An STEEGEN , Haining Yang , Ying Zhang
发明人： An STEEGEN , Haining Yang , Ying Zhang
IPC分类号： H01L21/00
CPC分类号： H01L29/7833 , H01L21/02381 , H01L21/0243 , H01L21/02532 , H01L21/02658 , H01L21/26506 , H01L21/76224 , H01L21/76232 , H01L21/76283 , H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L29/1054 , H01L29/665 , H01L29/66575 , H01L29/78 , H01L29/7842 , H01L29/7846 , H01L29/7849
摘要： A semiconductor device includes a semiconductor substrate having at least one gap, extending under a portion of the semiconductor substrate. A gate stack is on the semiconductor substrate. A strain layer is formed in at least a portion of the at least one gap. The strain layer is formed only under at least one of a source region and a drain region of the semiconductor device.

3. 发明申请

US20050164468A1 Selective silicon-on-insulator isolation structure and method 有权
公开(公告)号：US20050164468A1
公开(公告)日：2005-07-28
申请号：US11082993
申请日：2005-03-17
申请人： An Steegen , Maheswaran Surendra , Hsing-Jen Wann , Ying Zhang , Franz Zach , Robert Wong
发明人： An Steegen , Maheswaran Surendra , Hsing-Jen Wann , Ying Zhang , Franz Zach , Robert Wong
IPC分类号： H01L21/336 , H01L21/76 , H01L21/8234 , H01L21/8238 , H01L21/8242 , H01L21/84 , H01L27/12 , H01L29/76 , H01L31/062
CPC分类号： H01L29/66651 , H01L21/823481 , H01L21/823878 , H01L21/84 , H01L27/1203 , H01L29/0653 , H01L29/66772
摘要： A first aspect of the present invention is a method of forming an isolation structure including: (a) providing a semiconductor substrate; (b) forming a buried N-doped region in the substrate; (c) forming a vertical trench in the substrate, the trench extending into the N-doped region; (d) removing the N-doped region to form a lateral trench communicating with and extending perpendicular to the vertical trench; and (e) at least partially filling the lateral trench and filling the vertical trench with one or more insulating materials.

4. 发明授权

US06876040B1 Dense SRAM cells with selective SOI 失效
标题翻译：具有选择性SOI的密集SRAM单元
公开(公告)号：US06876040B1
公开(公告)日：2005-04-05
申请号：US10735169
申请日：2003-12-12
申请人： Hsingjen Wann , Ying Zhang , Robert C. Wong , An Steegen
发明人： Hsingjen Wann , Ying Zhang , Robert C. Wong , An Steegen
IPC分类号： H01L21/8244 , H01L21/84 , H01L27/11 , H01L27/12 , H01L27/01 , H01L29/76 , H01L29/94 , H01L31/0392
CPC分类号： H01L27/1207 , H01L21/84 , H01L27/11 , H01L27/1104 , Y10S257/903
摘要： A SRAM cell fabricated in SSOI (selective silicon on insulator) comprises cross coupled PFET pull-up devices P1, P2 and NFET pull-down devices N1, N2, with the P1, P2 devices being connected to the power supply and the N1, N2 devices being connected to the ground. A first passgate NL is coupled between a first bitline and the junction of the devices P1 and N1, with its gate coupled to a wordline, and a second passgate NR is coupled between a second bitline and the junction of devices P2 and N2, with its gate coupled to the wordline. Each of the pull-up devices P1, P2, the pull-down devices N1, N2, and the first and second passgates NL, NR are fabricated with selective SOI, with buried oxide being selectively provided under the drains of the pull-up devices P1 and P2, the drains of the pull-down devices N1 and N2, and the sources and drains of the passgate devices NL and NR.
摘要翻译：在SSOI（选择性绝缘体硅）上制造的SRAM单元包括交叉耦合的PFET上拉器件P1，P2和NFET下拉器件N1，N2，其中P1，P2器件连接到电源，N1，N2 设备连接到地面。第一通路门NL耦合在第一位线和器件P1和N1的接点之间，其栅极耦合到字线，并且第二通路门NR耦合在第二位线和器件P2和N2的接点之间，其中门连接到字线。上拉器件P1，P2，下拉器件N1，N2以及第一和第二通路NL，NR中的每一个被制造成具有选择性SOI，其中掩埋氧化物选择性地设置在上拉器件的漏极下 P1和P2，下拉装置N1和N2的下水道，以及通道装置NL和NR的源极和漏极。

5. 发明申请

US20060046428A1 Trench sidewall passivation for lateral rie in a selective silicon-on-insulator process flow 失效
标题翻译：在选择性绝缘体上硅工艺流程中用于侧向的沟槽侧壁钝化
公开(公告)号：US20060046428A1
公开(公告)日：2006-03-02
申请号：US10929990
申请日：2004-08-30
申请人： Christopher Baiocco , An Steegen , Ying Zhang
发明人： Christopher Baiocco , An Steegen , Ying Zhang
IPC分类号： H01L21/76
CPC分类号： H01L21/76232
摘要： A lateral trench in a semiconductor substrate is formed by the following steps. Form a lateral implant mask (LIM) over a top surface of the semiconductor substrate. Implant a heavy dopant concentration into the substrate through the LIM to form a lateral implant region (LIR) in the substrate. Strip the LIM exposing the top surface of the substrate. Form an epitaxial silicon layer over the top surface of the substrate burying the LIR. Form a trench mask over the epitaxial layer. Etch a trench reaching through the epitaxial layer and the LIR. Form oxidized trench sidewalls, an oxidized trench bottom and oxidized sidewalls of the LIR. Etch the oxidized sidewalls of the LIR until the LIR is exposed. Form laterally extending trenches by etching away the LIR.
摘要翻译：通过以下步骤形成半导体衬底中的横向沟槽。在半导体衬底的顶表面上形成横向植入掩模（LIM）。通过LIM将重掺杂浓度植入到衬底中，以在衬底中形成横向植入区域（LIR）。剥离LIM暴露衬底的顶部表面。在掩埋LIR的衬底的顶表面上形成外延硅层。在外延层上形成沟槽掩模。蚀刻穿过外延层和LIR的沟槽。形成氧化的沟槽侧壁，氧化沟槽底部和LIR的氧化侧壁。蚀刻LIR的氧化侧壁，直到LIR暴露。通过蚀刻掉LIR形成横向延伸的沟槽。

6. 发明申请

US20080029818A1 SELECTIVE SILICON-ON-INSULATOR ISOLATION STRUCTURE AND METHOD 有权
标题翻译：选择性绝缘子绝缘体隔离结构和方法
公开(公告)号：US20080029818A1
公开(公告)日：2008-02-07
申请号：US11871249
申请日：2007-10-12
申请人： An Steegen , Maheswaran Surendra , Hsing-Jen Wann , Ying Zhang , Franz Zach , Robert Wong
发明人： An Steegen , Maheswaran Surendra , Hsing-Jen Wann , Ying Zhang , Franz Zach , Robert Wong
IPC分类号： H01L27/12
CPC分类号： H01L29/66651 , H01L21/823481 , H01L21/823878 , H01L21/84 , H01L27/1203 , H01L29/0653 , H01L29/66772
摘要： A first aspect of the present invention is a method of forming an isolation structure including: (a) providing a semiconductor substrate; (b) forming a buried N-doped region in the substrate; (c) forming a vertical trench in the substrate, the trench extending into the N-doped region; (d) removing the N-doped region to form a lateral trench communicating with and extending perpendicular to the vertical trench; and (e) at least partially filling the lateral trench and filling the vertical trench with one or more insulating materials.
摘要翻译：本发明的第一方面是一种形成隔离结构的方法，包括：（a）提供半导体衬底; （b）在衬底中形成掩埋的N掺杂区域; （c）在所述衬底中形成垂直沟槽，所述沟槽延伸到所述N掺杂区域中; （d）去除所述N掺杂区域以形成与所述垂直沟槽连通并垂直于所述垂直沟槽延伸的横向沟槽; 和（e）至少部分地填充横向沟槽并用一种或多种绝缘材料填充垂直沟槽。

7. 发明申请

US20200165340A1 ANTI-PROGRAMMED DEATH-LIGAND 1 (PD-L1) ANTIBODIES AND THERAPEUTIC USES THEREOF 审中-公开
公开(公告)号：US20200165340A1
公开(公告)日：2020-05-28
申请号：US16486150
申请日：2017-02-16
申请人： Ying Zhang , Xiangtan Tenghua Bioscience
发明人： Ying Zhang
IPC分类号： C07K16/28 , A61K39/395 , A61P35/00 , A61K31/454
摘要： Anti-programmed death-ligand 1 (PD-L1) antibodies, methods of using the same, therapeutic compositions thereof, and uses thereof in upregulating cell-mediated immune responses and treating T cell dysfunctional disorders are provided. The use of the anti-PD-L1 antibody as a diagnostic agent in vitro is also provided.

8. 发明申请

US20200062847A1 RECOMBINANT ANTIBODIES TO PROGRAMMED DEATH 1 (PD-1) AND USES THEREFOR 审中-公开
公开(公告)号：US20200062847A1
公开(公告)日：2020-02-27
申请号：US16488667
申请日：2017-03-04
申请人： Ying ZHANG , Xiangtan Tenghua Bioscience
发明人： Ying Zhang
IPC分类号： C07K16/28
摘要： Provided are monoclonal antibody, particularly rabbit recombinant antibody, which specifically binds to human PD-1 with biological functions and super high affinity, and methods of use. In various embodiments, the antibodies are fully humanized antibodies that bind to human PD-1. Nucleic acid molecules encoding the antibodies and methods for expressing the antibodies are also provided. In some embodiments, the antibodies are useful for inhibiting or neutralizing PD-1 activity, thus providing a means of treating, preventing and/or diagnosing a disease or disorder such as cancer or a viral infection.

9. 发明授权

US09472444B2 Wafer support device 有权
标题翻译：晶圆支撑装置
公开(公告)号：US09472444B2
公开(公告)日：2016-10-18
申请号：US13593479
申请日：2012-08-23
申请人： Tien-Chih Cheng , Ying Zhang , Shu-Huei Suen , Chen-Chiao Kao
发明人： Tien-Chih Cheng , Ying Zhang , Shu-Huei Suen , Chen-Chiao Kao
IPC分类号： B05C13/00 , B23B31/28 , B05D1/02 , B05C11/00 , B05D3/12 , H01L21/687
CPC分类号： H01L21/6875 , B05B13/02 , B05B15/00 , B24B7/228 , H01L21/6833 , H01L21/68757 , Y10T279/23
摘要： A wafer support device is provided. The wafer support device includes a plurality of support portions; and a bottom area located among the support portions, wherein the bottom area has a protective layer formed thereon. A method for processing a working surface of a wafer support device is also provided.
摘要翻译：提供了晶片支撑装置。晶片支撑装置包括多个支撑部分; 以及位于支撑部之间的底部区域，其中底部区域具有形成在其上的保护层。还提供了一种用于处理晶片支撑装置的工作表面的方法。

10. 发明授权

US09150472B2 Method and composition for inhibiting asphaltene deposition in a hydrocarbon mixture 有权
标题翻译：抑制烃混合物中沥青质沉积的方法和组合物
公开(公告)号：US09150472B2
公开(公告)日：2015-10-06
申请号：US14366828
申请日：2012-12-17
申请人： Zhongxin Huo , Timothy Michael Shea , Cornelis Antonius Theodorus Kuijvenhoven , Ying Zhang
发明人： Zhongxin Huo , Timothy Michael Shea , Cornelis Antonius Theodorus Kuijvenhoven , Ying Zhang
IPC分类号： C10G75/04 , C07C7/20 , C09K8/524 , E21B43/25
CPC分类号： C07C7/20 , C09K8/524 , C10G75/04 , E21B43/25
摘要： A method of inhibiting the deposition of asphaltene in a mixture comprising hydrocarbons, the method comprising contacting the mixture with a composition which comprises at least one poly(hydroxycarboxylic acid) amide salt derivative.
摘要翻译：一种抑制沥青质沉积在包含烃的混合物中的方法，该方法包括使混合物与包含至少一种聚（羟基羧酸）酰胺盐衍生物的组合物接触。

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