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61. 发明授权

US07353470B2 Variable clocked scan test improvements 失效
标题翻译：可变时钟扫描测试改进
公开(公告)号：US07353470B2
公开(公告)日：2008-04-01
申请号：US11182809
申请日：2005-07-18
申请人： Laurence H. Cooke , Bulent I. Dervisoglu
发明人： Laurence H. Cooke , Bulent I. Dervisoglu
IPC分类号： G06F17/50
CPC分类号： G01R31/318552
摘要： Addition of specific test logic may improve the level of test vector compression achieved from existing variable scan test logic. Methods for determining the compressed vectors' states, given the desired uncompressed vectors' values may be used, and techniques for selectively enabling test or other features on a chip by inserting the proper code or codes into the chip may further be used. Techniques may be used to incorporate and apply various types of reset operations to multiple strings of variable scan test logic, as may methods to minimize the test vector compression computation time.
摘要翻译：添加特定的测试逻辑可以提高从现有的可变扫描测试逻辑实现的测试向量压缩的水平。可以使用给定期望的未压缩向量值来确定压缩向量状态的方法，并且还可以使用用于通过将适当的代码或代码插入到芯片中来选择性地启用芯片上的测试或其他特征的技术。技术可以用于将各种类型的复位操作并入并应用于多个可变扫描测试逻辑串，作为使测试向量压缩计算时间最小化的方法。

62. 发明授权

US07181705B2 Hierarchical test circuit structure for chips with multiple circuit blocks 有权
标题翻译：具有多个电路块的芯片的分层测试电路结构
公开(公告)号：US07181705B2
公开(公告)日：2007-02-20
申请号：US10327369
申请日：2002-12-20
申请人： Bulent Dervisoglu , Laurence H. Cooke
发明人： Bulent Dervisoglu , Laurence H. Cooke
IPC分类号： G06F17/50
CPC分类号： G01R31/318586 , G01R31/318505 , G01R31/318536
摘要： A system and method for testing an integrated circuit having internal circuit blocks. Each of the internal circuit blocks may have its own test circuit block, referred to as a socket access port. The integrated circuit preferably includes a chip access port (e.g., an IEEE standard 1149.1 compliant test access port) connected to a set of boundary-scan cells, and connected in a hierarchical fashion to the lower-level test circuit blocks. Each of the lower-level test control circuit blocks preferably comprises a socket access port controller, and test operation is transferred downward and upwards within said hierarchical structure by communicating from a test control circuit block to the test control circuit block at the immediately higher or immediately lower level in the hierarchical structure. Each of the lower-level test control circuit blocks of the hierarchical test control network may be functionally identical. Further, each of the lower-level test control circuit blocks may be structurally identical. An existing boundary scan may be easily modified for use in the hierarchical structure by adding push instructions to send it to a lower-level test circuit block, and pop instructions to return control to the higher level test circuit block.
摘要翻译：一种用于测试具有内部电路块的集成电路的系统和方法。每个内部电路块可以具有其自己的测试电路块，称为插座接入端口。集成电路优选地包括连接到一组边界扫描单元的芯片接入端口（例如，符合IEEE标准1149.1的测试接入端口），并且以分层方式连接到下级测试电路块。每个下级测试控制电路块优选地包括插座访问端口控制器，并且测试操作在所述分级结构内通过从测试控制电路块到测试控制电路块在立即更高或立即通信而向下和向下传送层次结构较低。分级测试控制网络的每个下级测试控制电路块可以在功能上相同。此外，每个下级测试控制电路块可以在结构上相同。可以通过添加推送指令将其发送到较低级别的测试电路块，并且弹出指令将控制返回到较高级别的测试电路块，可以容易地修改现有边界扫描以用于分级结构。

63. 发明授权

US07080301B2 On-chip service processor 无效
公开(公告)号：US07080301B2
公开(公告)日：2006-07-18
申请号：US11261762
申请日：2005-10-31
申请人： Bulent Dervisoglu , Laurence H. Cooke , Vacit Arat
发明人： Bulent Dervisoglu , Laurence H. Cooke , Vacit Arat
IPC分类号： G01R31/28
CPC分类号： G01R31/318572 , G01R31/31705 , G01R31/31723 , G01R31/318385 , G01R31/318566
摘要： An integrated circuit is described that includes a stored program processor for test and debug of user-definable logic plus external interface between the test/debug circuits and the component pins. The external interface may be via an existing test interface or a separate serial or parallel port. Test and debug circuits may contain scan strings that may be used to observe states in user-definable logic or be used to provide pseudo-random bit sequences to user-definable logic. Test and debug circuits may also contain an on-chip logic analyzer for capturing sequences of logic states in user-definable circuits. Test and debug circuits may be designed to observe states in user-definable circuits during the normal system operation of said user-definable circuits.

64. 发明授权

US06964001B2 On-chip service processor 有权
标题翻译：片上服务处理器
公开(公告)号：US06964001B2
公开(公告)日：2005-11-08
申请号：US10767265
申请日：2004-01-30
申请人： Bulent Dervisoglu , Laurence H. Cooke , Vacit Arat
发明人： Bulent Dervisoglu , Laurence H. Cooke , Vacit Arat
IPC分类号： G01R31/317 , G01R31/3185 , G01R31/28
CPC分类号： G01R31/318572 , G01R31/31705 , G01R31/31723 , G01R31/318385 , G01R31/318566
摘要： An integrated circuit is described which include a stored program processor for test and debug of user-definable logic plus external interface between the test/debug circuits and the component pins. The external interface may be via an existing test interface, or a separate serial or parallel port. Test and debug circuits may contain scan strings that may be used to observe states in user-definable logic or be used to provide pseudo-random bit sequences to user-definable logic. Test and debug circuits may also contain on-chip logic analyzer for capturing sequences of logic states in user-definable circuits. Test and debug circuits may be designed to observe states in user-definable circuits during the normal system operation of said user-definable circuits.
摘要翻译：描述了一种集成电路，其包括存储的程序处理器，用于测试和调试用户可定义逻辑以及测试/调试电路和组件引脚之间的外部接口。外部接口可以通过现有的测试接口或单独的串行或并行端口。测试和调试电路可能包含可用于观察用户可定义逻辑状态的扫描串，或用于向用户定义的逻辑提供伪随机位序列。测试和调试电路还可以包含片上逻辑分析仪，用于捕获用户可定义电路中的逻辑状态序列。测试和调试电路可以被设计为在所述用户可定义电路的正常系统操作期间观察用户可定义电路中的状态。

65. 发明授权

US06651237B2 System and method for H-Tree clocking layout 有权
标题翻译： H-tree时钟布局的系统和方法
公开(公告)号：US06651237B2
公开(公告)日：2003-11-18
申请号：US09765959
申请日：2001-01-18
申请人： Laurence H. Cooke , Kumar Venkatramani
发明人： Laurence H. Cooke , Kumar Venkatramani
IPC分类号： G06F1750
CPC分类号： G06F1/10 , G06F17/5077
摘要： A technique for constructing a balanced H-Tree clock layout suited for application to clock signals in integrated circuits, but applicable to other signals requiring balanced distribution over a wide area, involves routing clock wires in a circuit design wherein internal circuit blocks are divided, to the extent possible, into groups having an equal number of circuit blocks. An upper H-Tree clock layout structure is established using the center of mass of each of the circuit block groups as guideposts. Adjustments in wire length to balance the wires of the H-Tree layout. A lower H-Tree clock layout structure is established using center points between pairs of adjacent or nearby circuit blocks as guideposts for the endpoints of clock wires, and then routing, to the extent necessary, wire segments to the individual circuit blocks.
摘要翻译：用于构建适用于集成电路中的时钟信号的平衡H-Tree时钟布局的技术，但是适用于需要在广域上平衡分配的其他信号的技术涉及以内部电路块划分的电路设计路由时钟线，在可能的范围内，具有相等数量的电路块的组。使用每个电路块组的质心作为路标建立上部H-Tree时钟布局结构。电线长度调整以平衡H-Tree布局的电线。使用相邻或附近电路块对之间的中心点作为时钟线端点的路标来建立较低的H-tree时钟布局结构，然后在必要的范围内将线段路由到各个电路块。

66. 发明授权

US09280490B2 Secure computing 有权
标题翻译：安全计算
公开(公告)号：US09280490B2
公开(公告)日：2016-03-08
申请号：US13864688
申请日：2013-04-17
申请人： Laurence H. Cooke
发明人： Laurence H. Cooke
IPC分类号： G06F11/30 , G06F12/14 , G06F12/08 , G06F21/52 , G06F9/30 , G06F21/75 , G06F21/85
CPC分类号： G06F12/1408 , G06F9/30178 , G06F12/0875 , G06F21/52 , G06F21/75 , G06F21/85 , G06F2212/402 , G06F2212/452 , G06F2221/2125
摘要： Techniques and logic are presented for encrypting and decrypting programs and related data within a multi-processor system to prevent tampering. The decryption and encryption may be performed either between a system bus and a processor's individual L1 cache memory or between a processor's instruction and execution unit and their respective L1 caches. The logic may include one or more linear feedback shift registers (LFSRs) that may be used for generation of unique sequential address related codes to perform the decryption of instructions and transformation logic that may be used for generation of equivalent offset address related codes to perform decryption and encryption of data. The logic may also be programmable and may be used for test purposes.
摘要翻译：提出了技术和逻辑，用于在多处理器系统内对程序和相关数据进行加密和解密，以防止篡改。解密和加密可以在系统总线和处理器的单个L1高速缓冲存储器之间或处理器的指令和执行单元与它们各自的L1高速缓存之间执行。该逻辑可以包括一个或多个线性反馈移位寄存器（LFSR），其可用于生成唯一的顺序地址相关代码，以执行指令和转换逻辑的解密，转换逻辑可用于产生等效的偏移地址相关代码以执行解密和数据加密。逻辑也可以是可编程的，并且可以用于测试目的。

67. 发明授权

US09219118B2 Use of hydrocarbon nanorings for data storage 有权
标题翻译：使用碳氢化合物纳米数据进行数据存储
公开(公告)号：US09219118B2
公开(公告)日：2015-12-22
申请号：US14289104
申请日：2014-05-28
申请人： Laurence H. Cooke
发明人： Laurence H. Cooke
IPC分类号： G11C19/08 , H01L29/06 , G11C11/14 , G11C11/16 , G11C13/02 , H01F1/42 , G11C11/44 , H01L51/00 , B82Y10/00 , H01L51/05
CPC分类号： H01L29/0669 , B82Y10/00 , G11C11/14 , G11C11/161 , G11C11/44 , G11C13/025 , G11C2213/35 , H01F1/42 , H01L51/0052 , H01L51/0575
摘要： Hydro-carbon nanorings may be used in storage. Sufficiently cooled, an externally hydrogen doped carbon nanoring may be used to create a radial dipole field to contain streams of electrons. Similarly, an internally hydrogen doped carbon nanoring may be used to create a radial dipole field to contain streams of positrons. When matched streams of positrons and electrons are sufficiently compressed they may form Cooper pairs with magnetic moments aligned to the movement of the stream. Matched adjacent Cooper pairs of electrons and positrons may contain information within their magnetic moments, and as such, may transmit and store information with little or no energy loss. Information may be similarly encoded in magnetic moments of spins of pairs of positrons and electrons, not in the form of Cooper pairs.
摘要翻译：水碳纳米管可用于储存。足够冷却，可以使用外部氢掺杂的碳纳米来产生径向偶极场以包含电子流。类似地，内部氢掺杂的碳纳米可以用于产生径向偶极场以包含正电子流。当正电子和电子的匹配流被充分压缩时，它们可以形成具有与流的运动对准的磁矩的Cooper对。匹配的Cooper对电子和正电子可能包含其磁矩内的信息，因此，可以很少或没有能量损失传输和存储信息。信息可以类似地编码在正电子和电子对的旋转的磁矩中，而不是以Cooper对的形式。

68. 发明授权

US09124256B2 Tunable clock system 有权
标题翻译：可调时钟系统
公开(公告)号：US09124256B2
公开(公告)日：2015-09-01
申请号：US14589444
申请日：2015-01-05
申请人： Laurence H. Cooke
发明人： Laurence H. Cooke
IPC分类号： H03K3/00 , H03K5/13 , H03K5/00
CPC分类号： H03K5/15 , H03K5/131 , H03K5/133 , H03K5/15013 , H03K2005/00065 , H03K2005/00247
摘要： A memory-like structure composed of variable resistor elements for use in tuning respective branches and leaves of a clock distribution structure, which may be used to compensate for chip-by-chip and/or combinatorial logic path-by-path delay variations, which may be due, for example, to physical variations in deep submicron devices and interconnections, is presented. A single system clocked scan flip-flop with the capability to perform delay test measurements is also presented. Methods for measuring combinatorial logic path delays to determine the maximum clock frequency and delays to program the variable resistors, as well as methods for calibrating and measuring the programmed variable resistors, are also presented.
摘要翻译：由可变电阻器元件组成的存储器状结构，用于调整时钟分配结构的相应分支和叶片，其可用于补偿逐芯片和/或组合逻辑逐个路径延迟变化，其中可能是因为例如深亚微米器件和互连中的物理变化。还提供了具有执行延迟测试测量功能的单个系统时钟扫描触发器。还提出了用于测量组合逻辑路径延迟以确定最大时钟频率和编程可变电阻器的延迟的方法，以及用于校准和测量编程的可变电阻器的方法。

69. 发明授权

US09007798B2 Nearest neighbor serial content addressable memory 有权
公开(公告)号：US09007798B2
公开(公告)日：2015-04-14
申请号：US13739618
申请日：2013-01-11
申请人： Laurence H. Cooke
发明人： Laurence H. Cooke
IPC分类号： G11C15/00 , G06K9/62 , G11C15/04 , H03K19/02
CPC分类号： G11C15/00 , G06K9/6276 , G11C15/04 , H03K19/02
摘要： A digital design and technique may be used to implement a Manhattan Nearest Neighbor content addressable memory function by augmenting a serial content addressable memory design with additional memory and counters for bit serially accumulating in parallel and subsequently comparing in parallel all the Manhattan distances between a serially inputted vector and all corresponding vectors resident in the CAM. Other distance measures, besides a Manhattan distance, may optionally be used in conjunction with similar techniques and designs.

70. 发明授权

US08996938B2 On-chip service processor 有权
标题翻译：片上服务处理器
公开(公告)号：US08996938B2
公开(公告)日：2015-03-31
申请号：US13027009
申请日：2011-02-14
申请人： Bulent Dervisoglu , Laurence H. Cooke , Vacit Arat
发明人： Bulent Dervisoglu , Laurence H. Cooke , Vacit Arat
IPC分类号： G01R31/28 , G01R31/3185 , G01R31/317 , G01R31/3183
CPC分类号： G01R31/318572 , G01R31/31705 , G01R31/31723 , G01R31/318385 , G01R31/318566
摘要： An integrated circuit is described that includes a stored program processor for test and debug of user-definable logic plus external interface between the test/debug circuits and the component pins. The external interface may be via an existing test interface or a separate serial or parallel port. Test and debug circuits may contain scan strings that may be used to observe states in user-definable logic or be used to provide pseudo-random bit sequences to user-definable logic. Test and debug circuits may also contain an on-chip logic analyzer for capturing sequences of logic states in user-definable circuits. Test and debug circuits may be designed to observe states in user-definable circuits during the normal system operation of said user-definable circuits.
摘要翻译：描述了一种集成电路，其包括存储的程序处理器，用于测试和调试用户可定义逻辑以及测试/调试电路和组件引脚之间的外部接口。外部接口可以通过现有的测试接口或单独的串行或并行端口。测试和调试电路可能包含可用于观察用户可定义逻辑状态的扫描串，或用于向用户定义的逻辑提供伪随机位序列。测试和调试电路还可以包含用于捕获用户可定义电路中的逻辑状态序列的片上逻辑分析器。测试和调试电路可以被设计为在所述用户可定义电路的正常系统操作期间观察用户可定义电路中的状态。

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