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1. 发明授权

US06687865B1 On-chip service processor for test and debug of integrated circuits 有权
标题翻译：用于集成电路测试和调试的片上服务处理器
公开(公告)号：US06687865B1
公开(公告)日：2004-02-03
申请号：US09275726
申请日：1999-03-24
申请人： Bulent Dervisoglu , Laurence H. Cooke , Vacit Arat
发明人： Bulent Dervisoglu , Laurence H. Cooke , Vacit Arat
IPC分类号： G01R3128
CPC分类号： G01R31/318572 , G01R31/31705 , G01R31/31723 , G01R31/318385 , G01R31/318566
摘要： An integrated circuit is described which include a stored program processor for test and debug of user-definable logic plus external interface between the test/debug circuits and the component pins. The external interface may be via an existing test interface, or a separate serial or parallel port. Test and debug circuits may contain scan strings that may be used to observe states in user-definable logic or be used to provide pseudo-random bit sequences to user-definable logic. Test and debug circuits may also contain on-chip logic analyzer for capturing sequences of logic states in user-definable circuits. Test and debug circuits may be designed to observe states in user-definable circuits during the normal system operation of said user-definable circuits.
摘要翻译：描述了一种集成电路，其包括存储的程序处理器，用于测试和调试用户可定义逻辑以及测试/调试电路和组件引脚之间的外部接口。外部接口可以通过现有的测试接口或单独的串行或并行端口。测试和调试电路可能包含可用于观察用户可定义逻辑状态的扫描串，或用于向用户定义的逻辑提供伪随机位序列。测试和调试电路还可以包含片上逻辑分析仪，用于捕获用户可定义电路中的逻辑状态序列。测试和调试电路可以被设计为在所述用户可定义电路的正常系统操作期间观察用户可定义电路中的状态。

2. 发明申请

US20080168309A1 On-chip service processor 有权
标题翻译：片上服务处理器
公开(公告)号：US20080168309A1
公开(公告)日：2008-07-10
申请号：US11424610
申请日：2006-06-16
申请人： Bulent Dervisoglu , Laurence H. Cooke , Vacit Arat
发明人： Bulent Dervisoglu , Laurence H. Cooke , Vacit Arat
IPC分类号： G06F11/00
CPC分类号： G01R31/318572 , G01R31/31705 , G01R31/31723 , G01R31/318385 , G01R31/318566
摘要： An integrated circuit is described that includes a stored program processor for test and debug of user-definable logic plus external interface between the test/debug circuits and the component pins. The external interface may be via an existing test interface or a separate serial or parallel port. Test and debug circuits may contain scan strings that may be used to observe states in user-definable logic or be used to provide pseudo-random bit sequences to user-definable logic. Test and debug circuits may also contain an on-chip logic analyzer for capturing sequences of logic states in user-definable circuits. Test and debug circuits may be designed to observe states in user-definable circuits during the normal system operation of said user-definable circuits.
摘要翻译：描述了一种集成电路，其包括存储的程序处理器，用于测试和调试用户可定义逻辑以及测试/调试电路和组件引脚之间的外部接口。外部接口可以通过现有的测试接口或单独的串行或并行端口。测试和调试电路可能包含可用于观察用户可定义逻辑状态的扫描串，或用于向用户定义的逻辑提供伪随机位序列。测试和调试电路还可以包含用于捕获用户可定义电路中的逻辑状态序列的片上逻辑分析器。测试和调试电路可以被设计为在所述用户可定义电路的正常系统操作期间观察用户可定义电路中的状态。

3. 发明申请

US20100162046A1 ON-CHIP SERVICE PROCESSOR 有权
标题翻译：在线服务处理器
公开(公告)号：US20100162046A1
公开(公告)日：2010-06-24
申请号：US12717391
申请日：2010-03-04
申请人： Bulent Dervisoglu , Laurence H. Cooke , Vacit Arat
发明人： Bulent Dervisoglu , Laurence H. Cooke , Vacit Arat
IPC分类号： G06F11/26
CPC分类号： G01R31/318572 , G01R31/31705 , G01R31/31723 , G01R31/318385 , G01R31/318566
摘要： An integrated circuit is described that includes a stored program processor for test and debug of user-definable logic plus external interface between the test/debug circuits and the component pins. The external interface may be via an existing test interface or a separate serial or parallel port. Test and debug circuits may contain scan strings that may be used to observe states in user-definable logic or be used to provide pseudo-random bit sequences to user-definable logic. Test and debug circuits may also contain an on-chip logic analyzer for capturing sequences of logic states in user-definable circuits. Test and debug circuits may be designed to observe states in user-definable circuits during the normal system operation of said user-definable circuits.
摘要翻译：描述了一种集成电路，其包括存储的程序处理器，用于测试和调试用户可定义逻辑以及测试/调试电路和组件引脚之间的外部接口。外部接口可以通过现有的测试接口或单独的串行或并行端口。测试和调试电路可能包含可用于观察用户可定义逻辑状态的扫描串，或用于向用户定义的逻辑提供伪随机位序列。测试和调试电路还可以包含用于捕获用户可定义电路中的逻辑状态序列的片上逻辑分析器。测试和调试电路可以被设计为在所述用户可定义电路的正常系统操作期间观察用户可定义电路中的状态。

4. 发明授权

US08996938B2 On-chip service processor 有权
标题翻译：片上服务处理器
公开(公告)号：US08996938B2
公开(公告)日：2015-03-31
申请号：US13027009
申请日：2011-02-14
申请人： Bulent Dervisoglu , Laurence H. Cooke , Vacit Arat
发明人： Bulent Dervisoglu , Laurence H. Cooke , Vacit Arat
IPC分类号： G01R31/28 , G01R31/3185 , G01R31/317 , G01R31/3183
CPC分类号： G01R31/318572 , G01R31/31705 , G01R31/31723 , G01R31/318385 , G01R31/318566
摘要： An integrated circuit is described that includes a stored program processor for test and debug of user-definable logic plus external interface between the test/debug circuits and the component pins. The external interface may be via an existing test interface or a separate serial or parallel port. Test and debug circuits may contain scan strings that may be used to observe states in user-definable logic or be used to provide pseudo-random bit sequences to user-definable logic. Test and debug circuits may also contain an on-chip logic analyzer for capturing sequences of logic states in user-definable circuits. Test and debug circuits may be designed to observe states in user-definable circuits during the normal system operation of said user-definable circuits.
摘要翻译：描述了一种集成电路，其包括存储的程序处理器，用于测试和调试用户可定义逻辑以及测试/调试电路和组件引脚之间的外部接口。外部接口可以通过现有的测试接口或单独的串行或并行端口。测试和调试电路可能包含可用于观察用户可定义逻辑状态的扫描串，或用于向用户定义的逻辑提供伪随机位序列。测试和调试电路还可以包含用于捕获用户可定义电路中的逻辑状态序列的片上逻辑分析器。测试和调试电路可以被设计为在所述用户可定义电路的正常系统操作期间观察用户可定义电路中的状态。

5. 发明申请

US20120011411A1 ON-CHIP SERVICE PROCESSOR 有权
标题翻译：在线服务处理器
公开(公告)号：US20120011411A1
公开(公告)日：2012-01-12
申请号：US13027009
申请日：2011-02-14
申请人： Bulent Dervisoglu , Laurence H. Cooke , Vacit Arat
发明人： Bulent Dervisoglu , Laurence H. Cooke , Vacit Arat
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/318572 , G01R31/31705 , G01R31/31723 , G01R31/318385 , G01R31/318566
摘要： An integrated circuit is described that includes a stored program processor for test and debug of user-definable logic plus external interface between the test/debug circuits and the component pins. The external interface may be via an existing test interface or a separate serial or parallel port. Test and debug circuits may contain scan strings that may be used to observe states in user-definable logic or be used to provide pseudo-random bit sequences to user-definable logic. Test and debug circuits may also contain an on-chip logic analyzer for capturing sequences of logic states in user-definable circuits. Test and debug circuits may be designed to observe states in user-definable circuits during the normal system operation of said user-definable circuits.
摘要翻译：描述了一种集成电路，其包括存储的程序处理器，用于测试和调试用户可定义逻辑以及测试/调试电路和组件引脚之间的外部接口。外部接口可以通过现有的测试接口或单独的串行或并行端口。测试和调试电路可能包含可用于观察用户可定义逻辑状态的扫描串，或用于向用户定义的逻辑提供伪随机位序列。测试和调试电路还可以包含用于捕获用户可定义电路中的逻辑状态序列的片上逻辑分析器。测试和调试电路可以被设计为在所述用户可定义电路的正常系统操作期间观察用户可定义电路中的状态。

6. 发明授权

US07836371B2 On-chip service processor 有权
标题翻译：片上服务处理器
公开(公告)号：US07836371B2
公开(公告)日：2010-11-16
申请号：US11424610
申请日：2006-06-16
申请人： Bulent Dervisoglu , Laurence H. Cooke , Vacit Arat
发明人： Bulent Dervisoglu , Laurence H. Cooke , Vacit Arat
IPC分类号： G01R31/28
CPC分类号： G01R31/318572 , G01R31/31705 , G01R31/31723 , G01R31/318385 , G01R31/318566
摘要： An integrated circuit is described that includes a stored program processor for test and debug of user-definable logic plus external interface between the test/debug circuits and the component pins. The external interface may be via an existing test interface or a separate serial or parallel port. Test and debug circuits may contain scan strings that may be used to observe states in user-definable logic or be used to provide pseudo-random bit sequences to user-definable logic. Test and debug circuits may also contain an on-chip logic analyzer for capturing sequences of logic states in user-definable circuits. Test and debug circuits may be designed to observe states in user-definable circuits during the normal system operation of said user-definable circuits.
摘要翻译：描述了一种集成电路，其包括存储的程序处理器，用于测试和调试用户可定义逻辑以及测试/调试电路和组件引脚之间的外部接口。外部接口可以通过现有的测试接口或单独的串行或并行端口。测试和调试电路可能包含可用于观察用户可定义逻辑状态的扫描串，或用于向用户定义的逻辑提供伪随机位序列。测试和调试电路还可以包含用于捕获用户可定义电路中的逻辑状态序列的片上逻辑分析器。测试和调试电路可以被设计为在所述用户可定义电路的正常系统操作期间观察用户可定义电路中的状态。

7. 发明授权

US07080301B2 On-chip service processor 无效
公开(公告)号：US07080301B2
公开(公告)日：2006-07-18
申请号：US11261762
申请日：2005-10-31
申请人： Bulent Dervisoglu , Laurence H. Cooke , Vacit Arat
发明人： Bulent Dervisoglu , Laurence H. Cooke , Vacit Arat
IPC分类号： G01R31/28
CPC分类号： G01R31/318572 , G01R31/31705 , G01R31/31723 , G01R31/318385 , G01R31/318566
摘要： An integrated circuit is described that includes a stored program processor for test and debug of user-definable logic plus external interface between the test/debug circuits and the component pins. The external interface may be via an existing test interface or a separate serial or parallel port. Test and debug circuits may contain scan strings that may be used to observe states in user-definable logic or be used to provide pseudo-random bit sequences to user-definable logic. Test and debug circuits may also contain an on-chip logic analyzer for capturing sequences of logic states in user-definable circuits. Test and debug circuits may be designed to observe states in user-definable circuits during the normal system operation of said user-definable circuits.

8. 发明授权

US06964001B2 On-chip service processor 有权
标题翻译：片上服务处理器
公开(公告)号：US06964001B2
公开(公告)日：2005-11-08
申请号：US10767265
申请日：2004-01-30
申请人： Bulent Dervisoglu , Laurence H. Cooke , Vacit Arat
发明人： Bulent Dervisoglu , Laurence H. Cooke , Vacit Arat
IPC分类号： G01R31/317 , G01R31/3185 , G01R31/28
CPC分类号： G01R31/318572 , G01R31/31705 , G01R31/31723 , G01R31/318385 , G01R31/318566
摘要： An integrated circuit is described which include a stored program processor for test and debug of user-definable logic plus external interface between the test/debug circuits and the component pins. The external interface may be via an existing test interface, or a separate serial or parallel port. Test and debug circuits may contain scan strings that may be used to observe states in user-definable logic or be used to provide pseudo-random bit sequences to user-definable logic. Test and debug circuits may also contain on-chip logic analyzer for capturing sequences of logic states in user-definable circuits. Test and debug circuits may be designed to observe states in user-definable circuits during the normal system operation of said user-definable circuits.
摘要翻译：描述了一种集成电路，其包括存储的程序处理器，用于测试和调试用户可定义逻辑以及测试/调试电路和组件引脚之间的外部接口。外部接口可以通过现有的测试接口或单独的串行或并行端口。测试和调试电路可能包含可用于观察用户可定义逻辑状态的扫描串，或用于向用户定义的逻辑提供伪随机位序列。测试和调试电路还可以包含片上逻辑分析仪，用于捕获用户可定义电路中的逻辑状态序列。测试和调试电路可以被设计为在所述用户可定义电路的正常系统操作期间观察用户可定义电路中的状态。

9. 发明申请

US20060064615A1 On-chip service processor 无效
公开(公告)号：US20060064615A1
公开(公告)日：2006-03-23
申请号：US11261762
申请日：2005-10-31
申请人： Bulent Dervisoglu , Laurence Cooke , Vacit Arat
发明人： Bulent Dervisoglu , Laurence Cooke , Vacit Arat
IPC分类号： G01R31/28
CPC分类号： G01R31/318572 , G01R31/31705 , G01R31/31723 , G01R31/318385 , G01R31/318566
摘要： An integrated circuit is described that includes a stored program processor for test and debug of user-definable logic plus external interface between the test/debug circuits and the component pins. The external interface may be via an existing test interface or a separate serial or parallel port. Test and debug circuits may contain scan strings that may be used to observe states in user-definable logic or be used to provide pseudo-random bit sequences to user-definable logic. Test and debug circuits may also contain an on-chip logic analyzer for capturing sequences of logic states in user-definable circuits. Test and debug circuits may be designed to observe states in user-definable circuits during the normal system operation of said user-definable circuits.

10. 发明授权

US07200784B2 Accelerated scan circuitry and method for reducing scan test data volume and execution time 有权
公开(公告)号：US07200784B2
公开(公告)日：2007-04-03
申请号：US10931191
申请日：2004-09-01
申请人： Bulent Dervisoglu , Laurence H. Cooke
发明人： Bulent Dervisoglu , Laurence H. Cooke
IPC分类号： G01R31/28
CPC分类号： G01R31/318547 , G01R31/318335 , G01R31/318385 , G01R31/318536 , G01R31/318572
摘要： An architecture and methodology for test data compression using combinational functions to provide serial coupling between consecutive segments of a scan-chain are described. Compressed serial-scan sequences are derived starting from scan state identifying desired Care_In values and using symbolic computations iteratively in order to determine the necessary previous scan-chain state until computed previous scan-chain state matches given known starting scan-chain state. A novel design for a new flip-flop is also presented that allows implementing scan-chains that can be easily started and stopped without requiring an additional control signal. Extensions of the architecture and methodology are discussed to handle unknown (X) values in scan-chains, proper clocking of compressed data into multiple scan-chains, the use of a data-spreading network and the use of a pseudo-random signal generator to feed the segmented scan-chains in order to implement Built In Self Test (BIST).

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