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61. 发明授权

US06523159B2 Method for adding decoupling capacitance during integrated circuit design 有权
标题翻译：在集成电路设计期间添加去耦电容的方法
公开(公告)号：US06523159B2
公开(公告)日：2003-02-18
申请号：US09761464
申请日：2001-01-16
申请人： Kerry Bernstein , John M. Cohn , Jose L. P. Neves
发明人： Kerry Bernstein , John M. Cohn , Jose L. P. Neves
IPC分类号： G06F1750
CPC分类号： G06F17/5036
摘要： A method and a related program storage product for adding decoupling capacitance in an integrated circuit during the floor planning stage of the integrated circuit design. The invention overlay a power grid on the floor plan and then divides the power grid into regions or macros. For each region or macro, a support decoupling capacitance value required to support a voltage of the power grid and a native capacitance value are determined. Based on those values, a required decoupling capacitance value along with its decoupling capacitance area is determined. The design is then alternated based on the decoupling capacitance area.
摘要翻译：一种用于在集成电路设计的平面布置阶段期间在集成电路中添加去耦电容的方法和相关程序存储产品。本发明在平面图上覆盖电网，然后将电网划分为区域或宏。对于每个区域或宏，确定支持电网电压所需的支持去耦电容值和固有电容值。基于这些值，确定所需的去耦电容值及其去耦电容面积。然后基于去耦电容面积交替设计。

62. 发明授权

US06453431B1 System technique for detecting soft errors in statically coupled CMOS logic 失效
标题翻译：用于检测静态耦合CMOS逻辑中的软错误的系统技术
公开(公告)号：US06453431B1
公开(公告)日：2002-09-17
申请号：US09346509
申请日：1999-07-01
申请人： Kerry Bernstein , Andres Bryant , William A. Klaasen , Wilbur David Pricer
发明人： Kerry Bernstein , Andres Bryant , William A. Klaasen , Wilbur David Pricer
IPC分类号： G06K504
CPC分类号： G11C5/005 , G06F11/00
摘要： Circuit for detecting error transients in logic circuits due to atomic events or other non-recurring noise sources includes a first circuit coupled to a data line for sensing a first signal on the data line at a first point in time (T1) and a second circuit coupled to the data line for sensing the first signal on the data line at a second point in time (T2) such that a time difference between T1 and T2 is small enough so that the first signal is still present on the data line in the absence of a perturbation event and such that the time difference between T1 and T2 is large enough so that any such perturbation event is resolved. A compare circuit coupled to the first and second circuits compares the sensing of the first signal by the first and second circuits, and generates an error signal in response to a non-compare.
摘要翻译：用于检测由于原子事件或其他非循环噪声源引起的逻辑电路中的错误瞬变的电路包括耦合到数据线的第一电路，用于感测在第一时间点（T1）的数据线上的第一信号，以及第二电路耦合到数据线，用于在第二时间点（T2）感测数据线上的第一信号，使得T1和T2之间的时间差足够小，使得第一信号在不存在的情况下仍然存在于数据线上的扰动事件，并且使得T1和T2之间的时间差足够大，使得任何这样的扰动事件被解决。耦合到第一和第二电路的比较电路比较第一和第二电路对第一信号的感测，并且响应于非比较而产生误差信号。

63. 发明授权

US6091273A Voltage limiting circuit for fuse technology 失效
标题翻译：保险丝技术限压电路
公开(公告)号：US6091273A
公开(公告)日：2000-07-18
申请号：US914857
申请日：1997-08-19
申请人： Kerry Bernstein , Daniel Charles Edelstein , William Alan Klaasen , Wilbur David Pricer
发明人： Kerry Bernstein , Daniel Charles Edelstein , William Alan Klaasen , Wilbur David Pricer
IPC分类号： G11C17/18 , H03K17/687 , H03L5/00
CPC分类号： H03K17/6872 , G11C17/18
摘要： A voltage limiting circuit for fuse technology. The voltage limiting circuit is coupled to the two terminals. The voltage limiting circuit is responsive to a fuse blow through a low impedance sensing circuit, and then minimizes the voltage across the fuse gap that is created by the fuse blow. Thus, the invention prevents dendritic growth and corrosion in copper or similar types of fuses.
摘要翻译：一种用于保险丝技术的限压电路。电压限制电路耦合到两个端子。电压限制电路响应于通过低阻抗感测电路的保险丝熔断，然后使由保险丝熔断产生的熔丝间隙上的电压最小化。因此，本发明防止了铜或类似类型的保险丝中的树枝状生长和腐蚀。

64. 发明授权

US4742487A Inhibit and transfer circuitry for memory cell being read from multiple ports 失效
标题翻译：用于从多个端口读取的存储器单元的禁止和传送电路
公开(公告)号：US4742487A
公开(公告)日：1988-05-03
申请号：US852465
申请日：1986-04-15
申请人： Kerry Bernstein
发明人： Kerry Bernstein
IPC分类号： G11C11/41 , G11C8/16 , G11C11/401 , G11C11/419 , G11C7/00
CPC分类号： G11C8/16
摘要： An inhibit and transfer circuit for a memory system having multiple read ports. Bit lines are precharged. In a reading operation, the precharging is disconnected at the same time that the bit lines are selectively connected to one or more sense latches, associated with multiple reading ports. Feedback paths in the sense latches are disconnected during the reading. The selection of the sense latches to which the bit lines are coupled is determined by a comparison of multiple addressing signals.
摘要翻译：一种用于具有多个读端口的存储器系统的抑制和传输电路。位线预充电。在读取操作中，在与多个读取端口相关联的一个或多个感测锁存器选择性地连接位线的同时，预充电被断开。在读取期间，感测锁存器中的反馈路径被断开。通过比较多个寻址信号来确定位线耦合到的读出锁存器的选择。

65. 发明授权

US4577292A Support circuitry for multi-port systems 失效
标题翻译：支持多端口系统的电路
公开(公告)号：US4577292A
公开(公告)日：1986-03-18
申请号：US499729
申请日：1983-05-31
申请人： Kerry Bernstein
发明人： Kerry Bernstein
IPC分类号： G11C11/417 , G11C7/00 , G11C8/16 , G11C8/18 , G11C8/20 , G11C11/41 , H01L27/10 , G11C13/00
CPC分类号： G11C8/16 , G11C7/00 , G11C8/18 , G11C8/20
摘要： The present invention is especially directed towards an improved support circuitry for a memory array which utilizes support circuitry in a memory array such that, when an address compare occurs, selected one of the array word decoders are disabled to prevent a multiple read, and selected higher order read heads are disabled and the output data of the highest order bit lines is transferred onto all of the lower order bit lines having the same address as the uninhibited word decoder.
摘要翻译：本发明特别涉及用于存储器阵列的改进的支持电路，该支持电路利用存储器阵列中的支持电路，使得当发生地址比较时，所选择的一个阵列字解码器被禁止以防止多次读取并选择更高顺序读取头被禁用，并且最高位位线的输出数据被传送到具有与非禁止字解码器相同的地址的所有低位位线上。

66. 发明授权

US09496981B2 System and method of masking electromagnetic interference (EMI) emissions of a circuit 有权
标题翻译：屏蔽电路的电磁干扰（EMI）发射的系统和方法
公开(公告)号：US09496981B2
公开(公告)日：2016-11-15
申请号：US12507481
申请日：2009-07-22
申请人： Kerry Bernstein , Sebastian T. Ventrone
发明人： Kerry Bernstein , Sebastian T. Ventrone
IPC分类号： H04K1/02 , H04K3/00
CPC分类号： H04K3/825 , H04K3/42
摘要： A system is provided for securing information residing on a circuit (e.g., processor). In particular, a system and method is provided for masking electromagnetic interference (EMI) emissions emitting from a circuit using a random noise generator in combination with a low noise amplifier and antenna. The random number generator matches a frequency of a circuit to be protected, and generates a random signal to be superimposed on data. The low noise amplifier receives the random signal from the random number generator, and an antenna receives the random signal from the low noise amplifier and transmits the random signal to mask the data of the circuit to be protected.
摘要翻译：提供了用于保护驻留在电路（例如，处理器）上的信息的系统。特别地，提供了一种用于屏蔽使用随机噪声发生器与低噪声放大器和天线组合的从电路发射的电磁干扰（EMI）发射的系统和方法。随机数发生器匹配要保护的电路的频率，并产生要叠加在数据上的随机信号。低噪声放大器从随机数发生器接收随机信号，并且天线从低噪声放大器接收随机信号，并发送随机信号以掩蔽要被保护的电路的数据。

67. 发明授权

US09264150B2 Reactive metal optical security device and methods of fabrication and use 有权
标题翻译：反应性金属光学安全装置及其制造和使用方法
公开(公告)号：US09264150B2
公开(公告)日：2016-02-16
申请号：US13432414
申请日：2012-03-28
申请人： Kerry Bernstein , Kenneth J. Goodnow , Clarence R. Ogilvie , Charles S. Woodruff , Sebastian T. Ventrone
发明人： Kerry Bernstein , Kenneth J. Goodnow , Clarence R. Ogilvie , Charles S. Woodruff , Sebastian T. Ventrone
IPC分类号： H04B10/85 , G02B26/08
CPC分类号： H04B10/85 , G02B26/0816
摘要： A reactive metal optical security device for implementation in an optical network and/or system to provide a mechanism for disrupting the optical network and/or system. The security device includes a mirror comprising a reactive metal stack and configured to reflect an optical signal and receive an electrical signal. The security device further includes a semiconductor chip configured to send the electrical signal to the mirror.
摘要翻译：一种用于在光网络和/或系统中实现以提供用于中断光网络和/或系统的机制的无功金属光学安全装置。安全装置包括反射镜，其包括无功金属堆叠并且被配置为反射光信号并接收电信号。安全装置还包括被配置为将电信号发送到反射镜的半导体芯片。

68. 发明授权

US09052724B2 Electro-rheological micro-channel anisotropic cooled integrated circuits and methods thereof 有权
标题翻译：电流变微通道各向异性冷却集成电路及其方法
公开(公告)号：US09052724B2
公开(公告)日：2015-06-09
申请号：US13568248
申请日：2012-08-07
申请人： Kerry Bernstein , Kenneth J. Goodnow , Clarence R. Ogilvie
发明人： Kerry Bernstein , Kenneth J. Goodnow , Clarence R. Ogilvie
IPC分类号： H01L23/34 , G05D23/00 , G05D23/19 , H01L23/38 , H01L23/473 , H05K7/20 , G06F1/20
CPC分类号： G05D23/1919 , G06F1/206 , H01L23/38 , H01L23/473 , H01L2224/16225 , H01L2924/1305 , H01L2924/15174 , H01L2924/15311 , H05K7/20272 , H05K7/20281 , H05K7/20518 , H01L2924/00
摘要： An integrated circuit chip having micro-channels formed in multiple regions of the integrated circuit chip and a method of cooling the integrated circuit chip. The method includes for any region of the multiple regions, allowing a coolant to flow through micro-channels of the region only when a temperature of the region exceed a first specified temperature and blocking the coolant from flowing through the micro-channels of the region when a temperature of the region is below a second specified temperature.
摘要翻译：具有形成在集成电路芯片的多个区域中的微通道的集成电路芯片和冷却集成电路芯片的方法。该方法包括对于多个区域的任何区域，只有当该区域的温度超过第一规定温度并且阻止冷却剂流过该区域的微通道时，冷却剂才能流过该区域的微通道，该区域的温度低于第二规定温度。

69. 发明授权

US08853007B2 In-plane silicon heat spreader and method therefor 有权
标题翻译：平面硅散热器及其方法
公开(公告)号：US08853007B2
公开(公告)日：2014-10-07
申请号：US13024994
申请日：2011-02-10
申请人： Kerry Bernstein , Sri M. Sri-Jayantha
发明人： Kerry Bernstein , Sri M. Sri-Jayantha
IPC分类号： H01L23/36 , H01L23/373 , H01L25/065 , H01L23/367 , H01L23/00
CPC分类号： H01L23/3672 , H01L23/3738 , H01L24/29 , H01L24/32 , H01L24/48 , H01L25/0657 , H01L2224/48091 , H01L2224/73253 , H01L2225/06513 , H01L2225/06589 , H01L2924/00014 , H01L2924/01006 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/0132 , H01L2924/10253 , H01L2924/19041 , H01L2924/01014 , H01L2924/3512 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A method of dissipating heat from a heat source includes providing a plurality of heat flux paths in a plane of the heat source to remove heat from the heat source.
摘要翻译：从热源散热的方法包括在热源的平面中提供多个热通路，以从热源移除热量。

70. 发明申请

US20130249596A1 INACTIVITY TRIGGERED SELF CLOCKING LOGIC FAMILY 有权
标题翻译：不活动触发自锁定逻辑系列
公开(公告)号：US20130249596A1
公开(公告)日：2013-09-26
申请号：US13426776
申请日：2012-03-22
申请人： Kerry Bernstein , Kenneth J. Goodnow , Clarence R. Ogilvie , John Sargis, JR. , Sebastian T. Ventrone , Charles S. Woodruff
发明人： Kerry Bernstein , Kenneth J. Goodnow , Clarence R. Ogilvie , John Sargis, JR. , Sebastian T. Ventrone , Charles S. Woodruff
IPC分类号： H03K19/00
CPC分类号： H03K19/0966 , H03K19/0013
摘要： Localized logic regions of a circuit include a local comparator electrically connected to a local resistive voltage circuit, to a local resistive ground circuit, and to a local register structure. The local comparator supplies a clock pulse to the local register structures when the local reference voltage is below a local voltage threshold. Activity in the local combinatorial logic structure causes the local reference voltage to drop below the local reference voltage independently of changes in the global reference voltage causing the comparator to output the clock pulse (with sufficient delay to allow the logic results to be stored in the registers only after setup times have been met in the local logic devices). This eliminates the need for a clock distribution tree, thereby saving power when there is no activity in the local combinatorial logic structure.
摘要翻译：电路的局部逻辑区域包括电连接到局部电阻电压电路的本地比较器，局部电阻接地电路和局部寄存器结构。当本地参考电压低于本地电压阈值时，本地比较器会向本地寄存器结构提供时钟脉冲。本地组合逻辑结构中的活动导致本地参考电压低于局部参考电压，而与全局参考电压的变化无关，导致比较器输出时钟脉冲（具有足够的延迟以允许逻辑结果存储在寄存器中只有在本地逻辑设备中已经满足设置时间之后）。这消除了对时钟分配树的需要，从而在局部组合逻辑结构中没有活动时节省功率。

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