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61. 发明授权

US07344938B2 Method of fabricating memory 有权
标题翻译：制造记忆的方法
公开(公告)号：US07344938B2
公开(公告)日：2008-03-18
申请号：US11745059
申请日：2007-05-07
申请人： Kent Kuohua Chang , Jongoh Kim , Yider Wu
发明人： Kent Kuohua Chang , Jongoh Kim , Yider Wu
IPC分类号： H01L21/8244
CPC分类号： H01L27/11568 , H01L27/105 , H01L27/11573
摘要： A method of fabricating a memory device is described. During the process of forming the memory cell area and the periphery area of a semiconductor device a photoresist layer is formed on the memory cell area before the spacers are formed on the sidewalls of the gates. Therefore, the memory cell area is prevented from being damaged to mitigate the leakage current problem during the process of forming spacers in the periphery circuit area.
摘要翻译：描述了一种制造存储器件的方法。在形成存储单元区域和半导体器件的外围区域的过程中，在形成在栅极的侧壁上的间隔物之前，在存储单元区域上形成光致抗蚀剂层。因此，在外围电路区域中形成间隔物的过程中，防止存储单元区域被损坏以减轻漏电流问题。

62. 发明授权

US07229876B2 Method of fabricating memory 有权
标题翻译：制造记忆的方法
公开(公告)号：US07229876B2
公开(公告)日：2007-06-12
申请号：US11138612
申请日：2005-05-25
申请人： Kent Kuohua Chang , Jongoh Kim , Yider Wu
发明人： Kent Kuohua Chang , Jongoh Kim , Yider Wu
IPC分类号： H01L21/8244
CPC分类号： H01L27/11568 , H01L27/105 , H01L27/11573
摘要： A method of fabricating a memory device is described. During the process of forming the memory cell area and the periphery area of a semiconductor device a photoresist layer is formed on the memory cell area before the spacers are formed on the sidewalls of the gates. Therefore, the memory cell area is prevented from being damaged to mitigate the leakage current problem during the process of forming spacers in the periphery circuit area.
摘要翻译：描述了一种制造存储器件的方法。在形成存储单元区域和半导体器件的外围区域的过程中，在形成在栅极的侧壁上的间隔物之前，在存储单元区域上形成光致抗蚀剂层。因此，在外围电路区域中形成间隔物的过程中，防止存储单元区域被损坏以减轻漏电流问题。

63. 发明授权

US07098096B2 Method of fabricating multi-bit flash memory 有权
标题翻译：制造多位闪存的方法
公开(公告)号：US07098096B2
公开(公告)日：2006-08-29
申请号：US10707874
申请日：2004-01-20
申请人： Kent Kuohua Chang
发明人： Kent Kuohua Chang
IPC分类号： H01L21/8238
CPC分类号： H01L27/11521 , H01L21/28273 , H01L27/115 , H01L29/7887
摘要： A method of fabricating a multi-bit flash memory, having a control gate, a floating gate, a source region, a drain region and a channel region. An isolation region is formed in the floating gate to partition the floating gate into a plurality of conductive blocks. The conductive blocks are arranged in an array with rows extending from the source region to the drain region. Each row of the array has two conductive blocks. Before any data is written to the flash memory, the channel regions under the conductive blocks of the same row have the same threshold voltage, while the channel regions under the conductive blocks of different rows have different threshold voltage.
摘要翻译：一种制造具有控制栅极，浮置栅极，源极区域，漏极区域和沟道区域的多位闪存的方法。隔离区域形成在浮动栅极中，以将浮动栅极分隔成多个导电块。导电块被布置成具有从源极区域延伸到漏极区域的行的阵列。阵列的每一行都有两个导电块。在将任何数据写入闪速存储器之前，同一行的导电块下方的沟道区具有相同的阈值电压，而不同行的导电块下的沟道区具有不同的阈值电压。

64. 发明授权

US06838345B2 SiN ROM and method of fabricating the same 有权
标题翻译： SiN ROM及其制造方法
公开(公告)号：US06838345B2
公开(公告)日：2005-01-04
申请号：US10248165
申请日：2002-12-23
申请人： Kent Kuohua Chang
发明人： Kent Kuohua Chang
IPC分类号： H01L21/28 , H01L21/8246 , H01L27/115 , H01L29/792 , H01L21/336
CPC分类号： H01L27/11568 , H01L21/28282 , H01L27/115 , H01L29/7923
摘要： A fabrication method for a silicon nitride read only memory includes sequentially forming a tunneling oxide layer and a charge capture layer on a substrate. An isolation region is formed in the charge capture layer to partition the charge capture layer into a plurality of charge capture blocks. A stacked dielectric layer is then formed on the charge capture layer and the isolation region. Thereafter, the stacked dielectric layer and the charge capture layer are patterned to expose regions of the substrate for forming bit lines, followed by forming a field oxide layer and a control gate. A step of threshold voltage adjustment is subsequently performed such that the channel regions under the charge capture blocks are implanted to adjust the threshold voltages thereof
摘要翻译：氮化硅只读存储器的制造方法包括在衬底上依次形成隧穿氧化物层和电荷俘获层。在电荷俘获层中形成隔离区，以将电荷俘获层划分成多个电荷俘获块。然后在电荷俘获层和隔离区上形成堆叠的介质层。此后，对堆叠的电介质层和电荷俘获层进行图案化以暴露用于形成位线的衬底的区域，随后形成场氧化物层和控制栅极。随后执行阈值电压调整的步骤，使得注入电荷俘获块下方的沟道区域以调整其阈值电压

65. 发明授权

US06797567B2 High-K tunneling dielectric for read only memory device and fabrication method thereof 有权
标题翻译：用于只读存储器件的高K隧道电介质及其制造方法
公开(公告)号：US06797567B2
公开(公告)日：2004-09-28
申请号：US10248179
申请日：2002-12-24
申请人： Kent Kuohua Chang
发明人： Kent Kuohua Chang
IPC分类号： H01L21336
CPC分类号： H01L21/28202 , H01L21/28282 , H01L27/115 , H01L27/11568 , H01L29/518
摘要： A fabrication method for a read only memory device with a high dielectric constant tunneling dielectric layer, wherein this method provides forming a tunneling dielectric layer on a substrate, wherein the tunneling dielectric layer is formed with HfSiON or HfOxNy. An electron trapping layer and a top oxide layer are sequentially formed over the tunneling dielectric layer. Thereafter, the oxide layer, the electron trapping layer and the tunneling dielectric layer are patterned to form a plurality of stacked structures, followed by forming doped regions in the substrate between the stacked structures. Buried drain oxide layers are further formed over the surface of the doped regions, followed by forming a patterned conductive layer as the word line for the read only memory device.
摘要翻译：一种用于具有高介电常数隧道介电层的只读存储器件的制造方法，其中该方法提供在衬底上形成隧道电介质层，其中隧道电介质层由HfSiON或HfO x N y形成。在隧道电介质层上顺序地形成电子捕获层和顶部氧化物层。此后，对氧化物层，电子俘获层和隧道电介质层进行构图以形成多个堆叠结构，随后在堆叠结构之间的衬底中形成掺杂区域。掩埋的漏极氧化物层进一步形成在掺杂区域的表面上，随后形成图案化的导电层作为只读存储器件的字线。

66. 发明授权

US06674133B2 Twin bit cell flash memory device 有权
标题翻译：双位单元闪存设备
公开(公告)号：US06674133B2
公开(公告)日：2004-01-06
申请号：US10063879
申请日：2002-05-21
申请人： Kent Kuohua Chang
发明人： Kent Kuohua Chang
IPC分类号： H01L2976
CPC分类号： H01L27/11521 , G11C11/5621 , G11C16/0458 , H01L27/115 , H01L29/7887
摘要： The present invention provides a twin bit cell flash memory device and its fabricating method. The method is to first form a gate oxide layer on the surface of the silicon substrate followed by forming a polysilicon germanium (Si1−xGex, x=0.05˜1.0) layer on the gate oxide layer. Thereafter, an ion implantation process is performed to form at least one insulating region in the polysilicon germanium layer for separating the polysilicon germanium layer into two isolated conductive regions and forming a twin bit cell structure. Then, a dielectric layer is formed on the polysilicon germanium layer and a photo-etching-process (PEP) is performed to etch portions of the dielectric layer and the polysilicon germanium layer for forming a floating gate of the twin bit cell flash memory. Finally, a control gate is formed over the floating gate.
摘要翻译：本发明提供一种双位单元闪存器件及其制造方法。该方法首先在硅衬底的表面上形成栅氧化层，然后在栅极氧化层上形成多晶锗（Si1-xGex，x = 0.05〜1.0）层。此后，进行离子注入工艺以在多晶硅锗层中形成至少一个绝缘区域，用于将多晶硅锗层分离成两个隔离的导电区域并形成双位晶胞结构。然后，在多晶硅锗层上形成电介质层，并进行光蚀刻工艺（PEP）以蚀刻介电层和多晶硅锗层的部分，以形成双位晶胞闪存的浮动栅极。最后，在浮动栅极上形成控制栅极。

67. 发明授权

US06673720B2 Method for improving the reliability of flash memories 有权
标题翻译：提高闪速存储器可靠性的方法
公开(公告)号：US06673720B2
公开(公告)日：2004-01-06
申请号：US09683850
申请日：2002-02-22
申请人： Weng-Hsing Huang , Kent Kuohua Chang
发明人： Weng-Hsing Huang , Kent Kuohua Chang
IPC分类号： H01L21211
CPC分类号： H01L27/11521 , H01L27/115
摘要： A method for reducing random bit failures of flash memory fabrication processes with an HTO film. The random bit failures are caused by HF acid penetration. The HTO film, which functions as an interface reinforcement layer, is formed on a sacrificial layer and a PL1 layer. With the aid of the HTO film, the flash memory is free of acid-corroded seams.
摘要翻译：一种利用HTO薄膜减少闪速存储器制造工艺的随机位故障的方法。随机位故障是由HF酸渗透引起的。用作界面加强层的HTO膜形成在牺牲层和PL1层上。借助HTO胶片，闪存中没有酸腐蚀的接缝。

68. 发明授权

US06670672B1 Structure of discrete NROM cell 有权
标题翻译：离散NROM单元的结构
公开(公告)号：US06670672B1
公开(公告)日：2003-12-30
申请号：US10175839
申请日：2002-06-21
申请人： Kent Kuohua Chang , Erh-Kun Lai
发明人： Kent Kuohua Chang , Erh-Kun Lai
IPC分类号： H01L29792
CPC分类号： H01L27/11568 , H01L27/115 , H01L29/66833 , H01L29/792
摘要： A discrete NROM cell, at least comprising: a substrate; a first ON stacking gate and a second ON stacking gate over the substrate, wherein the ON stacking gate is a structure having a nitride layer over a bottom oxide layer; an oxide layer formed over the substrate covering the first and second ON stacking gate; a polysilicon layer formed over the oxide layer; and the source/drain implanted in the substrate and next to the ON stacking gates. The structure of discrete NROM cell of the invention can solve the problem of the electrons being trapped in the nitride layer of NROM cell, and also control the source/drain implant and ON structure at precisely symmetrical positions.
摘要翻译：一个离散的NROM电池，至少包括：一个衬底; 在所述衬底上的第一ON堆叠栅极和第二ON堆叠栅极，其中所述ON堆叠栅极是在底部氧化物层上方具有氮化物层的结构; 形成在所述基板上的覆盖所述第一和第二ON堆叠栅极的氧化物层; 形成在所述氧化物层上的多晶硅层; 并且注入到衬底中并且靠近ON堆叠栅极的源极/漏极。本发明的离散NROM电池的结构可以解决电子被捕获在NROM电池的氮化物层中的问题，并且还可以在精确对称的位置控制源极/漏极注入和ON结构。

69. 发明授权

US06589835B2 Method of manufacturing flash memory 有权
公开(公告)号：US06589835B2
公开(公告)日：2003-07-08
申请号：US09814408
申请日：2001-03-22
申请人： Kent Kuohua Chang
发明人： Kent Kuohua Chang
IPC分类号： H01L218238
CPC分类号： H01L29/511 , H01L21/28273
摘要： A process of manufacturing a flash memory device having a tunnel oxide layer with high reliability, low defect and interface trap by using semi-atmospheric pressure chemical vapor deposition (SPACVD) and tetra-ethyl-ortho-silicate (TEOS) reactant. SAPCVD is performed accompanied with a reaction temperature between about 600° C. and about 750° C. and a reaction pressure between about 340 Torr and about 500 Torr to react TEOS and oxygen.

70. 发明授权

US06538292B2 Twin bit cell flash memory device 有权
公开(公告)号：US06538292B2
公开(公告)日：2003-03-25
申请号：US09820294
申请日：2001-03-29
申请人： Kent Kuohua Chang , Fuh-Cheng Jong
发明人： Kent Kuohua Chang , Fuh-Cheng Jong
IPC分类号： H01L2976
CPC分类号： H01L21/28273 , H01L21/28282 , H01L29/7887
摘要： A semiconductor wafer comprises a semiconductor substrate of a first conductive type, a source and a drain of a second conductive type positioned in predetermined areas of the semiconductor substrate, and a channel positioned on the surface of the semiconductor substrate between the source and the drain. The memory device contains a first dielectric layer covering the surface of the channel. A conductive layer covers the surface of the first dielectric layer, the conductive layer containing an insulating region for separating the conductive layer so as to form two isolated conductive regions. A second dielectric layer covers the surface of the conductive layer. A gate covers the surface of the second dielectric layer. Each conductive region is used as a charge trapping layer so as to receive and store electrons injected into the conductive region, thus forming a twin bit cell flash memory device.

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