专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06599801B1 Method of fabricating NROM memory cell 有权
标题翻译：制造NROM记忆体的方法
公开(公告)号：US06599801B1
公开(公告)日：2003-07-29
申请号：US10178524
申请日：2002-06-25
申请人： Kent Kuohua Chang , Erh-Kun Lai
发明人： Kent Kuohua Chang , Erh-Kun Lai
IPC分类号： H01L21336
CPC分类号： H01L27/11568 , H01L27/105 , H01L27/115 , H01L27/11573
摘要： A method of fabricating NROM memory cell, wherein the NROM device comprises a memory array and a peripheral portion. The fabricating method comprising the steps of: providing a substrate which a oxide layer is formed thereon; forming a peripheral polysilicon layer on the oxide layer; defining a patterned peripheral polysilicon; forming an ONO layer over the substrate in the memory array and the peripheral portion; forming an array polysilicon layer on the ONO layer; and defining a patterned array polysilicon. The method of fabricating NROM memory cell according to the invention can solve the problems of top oxide loss, touch between nitride and polysilicon, and BD over-diffusion.
摘要翻译：一种制造NROM存储单元的方法，其中NROM器件包括存储器阵列和外围部分。该制造方法包括以下步骤：提供在其上形成氧化物层的衬底; 在所述氧化物层上形成外围多晶硅层; 限定图案化的外围多晶硅; 在存储器阵列和周边部分中的衬底上形成ONO层; 在ONO层上形成阵列多晶硅层; 并且限定图案化阵列多晶硅。根据本发明的制造NROM存储单元的方法可以解决顶部氧化物损失，氮化物和多晶硅之间的接触以及BD过度扩散的问题。

2. 发明授权

US06670672B1 Structure of discrete NROM cell 有权
标题翻译：离散NROM单元的结构
公开(公告)号：US06670672B1
公开(公告)日：2003-12-30
申请号：US10175839
申请日：2002-06-21
申请人： Kent Kuohua Chang , Erh-Kun Lai
发明人： Kent Kuohua Chang , Erh-Kun Lai
IPC分类号： H01L29792
CPC分类号： H01L27/11568 , H01L27/115 , H01L29/66833 , H01L29/792
摘要： A discrete NROM cell, at least comprising: a substrate; a first ON stacking gate and a second ON stacking gate over the substrate, wherein the ON stacking gate is a structure having a nitride layer over a bottom oxide layer; an oxide layer formed over the substrate covering the first and second ON stacking gate; a polysilicon layer formed over the oxide layer; and the source/drain implanted in the substrate and next to the ON stacking gates. The structure of discrete NROM cell of the invention can solve the problem of the electrons being trapped in the nitride layer of NROM cell, and also control the source/drain implant and ON structure at precisely symmetrical positions.
摘要翻译：一个离散的NROM电池，至少包括：一个衬底; 在所述衬底上的第一ON堆叠栅极和第二ON堆叠栅极，其中所述ON堆叠栅极是在底部氧化物层上方具有氮化物层的结构; 形成在所述基板上的覆盖所述第一和第二ON堆叠栅极的氧化物层; 形成在所述氧化物层上的多晶硅层; 并且注入到衬底中并且靠近ON堆叠栅极的源极/漏极。本发明的离散NROM电池的结构可以解决电子被捕获在NROM电池的氮化物层中的问题，并且还可以在精确对称的位置控制源极/漏极注入和ON结构。

3. 发明申请

US20120065741A1 GUIDED TISSUE REGENERATION MEMBRANE 审中-公开
标题翻译：指导组织再生膜
公开(公告)号：US20120065741A1
公开(公告)日：2012-03-15
申请号：US12880502
申请日：2010-09-13
申请人： Chao-Fu Chang , Kent Kuohua Chang
发明人： Chao-Fu Chang , Kent Kuohua Chang
IPC分类号： A61F2/02
CPC分类号： A61C8/0006 , A61L31/005 , A61L31/146
摘要： A guided tissue regeneration membrane has a top surface, a bottom surface and a plurality of through holes formed through the top and bottom surfaces. Each of the plurality of through holes has a base opening on the top surface and a tip opening on the bottom surface. The diameter of the base opening is larger than that of the tip opening. The guided tissue regeneration membrane is placed between a hard tissue and a soft tissue of gums with the top surface thereof facing the hard tissue so as to hinder the soft tissue from rapidly growing. The tip openings are available for the soft tissue to supply nutrient to the hard tissue therethrough. The hard tissue can grow from the base openings, through the corresponding through holes and to the soft tissue to repair periodontal tissue.
摘要翻译：引导组织再生膜具有顶表面，底表面和穿过顶表面和底表面形成的多个通孔。多个通孔中的每一个在顶表面上具有基部开口，在底面上具有顶端开口。基座开口的直径大于顶端开口的直径。引导组织再生膜置于硬组织和牙龈软组织之间，其顶表面面向硬组织，以阻止软组织迅速生长。尖端开口可用于软组织，以通过其中的硬组织提供营养。硬组织可以从基底开口，通过相应的通孔和软组织生长，以修复牙周组织。

4. 发明授权

US06706612B2 Fabrication method for shallow trench isolation 有权
标题翻译：浅沟槽隔离的制作方法
公开(公告)号：US06706612B2
公开(公告)日：2004-03-16
申请号：US10064370
申请日：2002-07-08
申请人： Szu-Tsun Ma , Kent Kuohua Chang
发明人： Szu-Tsun Ma , Kent Kuohua Chang
IPC分类号： H01L2176
CPC分类号： H01L21/76224
摘要： A method for fabricating a shallow trench isolation structure includes forming a hard mask layer over a substrate. An ion bombardment step is further performed on the surface of the hard mask layer, followed by forming a patterned photoresist layer on the surface of the hard mask layer. Thereafter, the hard mask layer is patterned using the photoresist layer as an etching mask. An etching process is further performed to form a trench in the substrate. The photoresist layer is then removed, followed by filling an insulation layer in the trench. After this, the hard mask is removed to complete the fabrication of a shallow trench isolation region.
摘要翻译：一种用于制造浅沟槽隔离结构的方法包括在衬底上形成硬掩模层。在硬掩模层的表面上进一步进行离子轰击步骤，然后在硬掩模层的表面上形成图案化的光致抗蚀剂层。此后，使用光致抗蚀剂层作为蚀刻掩模来对硬掩模层进行图案化。进一步进行蚀刻工艺以在衬底中形成沟槽。然后去除光致抗蚀剂层，然后在沟槽中填充绝缘层。之后，去除硬掩模以完成浅沟槽隔离区的制造。

5. 发明授权

US06580639B1 Method of reducing program disturbs in NAND type flash memory devices 有权
标题翻译：减少NAND型闪存器件编程干扰的方法
公开(公告)号：US06580639B1
公开(公告)日：2003-06-17
申请号：US09372406
申请日：1999-08-10
申请人： Yue-Song He , Kent Kuohua Chang , Allen U. Huang
发明人： Yue-Song He , Kent Kuohua Chang , Allen U. Huang
IPC分类号： G11C1604
CPC分类号： H01L29/66575 , G11C16/0483 , H01L21/26506 , H01L21/26513 , H01L29/66825 , H01L29/66833 , H01L29/78
摘要： The present invention makes use of ion bombardment to amorphize the source and drain regions of a short channel FET prior to implanting. The source/drain implants are then localized to a shallow depth by appropriate choice of implanting conditions, typically employing rather low bombardment voltages of approximately 10 KeV. Amorphous source/drain regions substantially hinder the diffusion of source/drain dopants and thereby reduce the possibility of punchthrough and loss of FET function. Such devices are preferably used in NAND type flash memory devices maintaining proper self-boosting voltages and FET functions even when short channel lengths are employed.
摘要翻译：本发明利用离子轰击在植入之前使短沟道FET的源极和漏极区域非晶化。然后通过适当选择植入条件将源极/漏极植入物定位到浅深度，通常采用约10KeV的相当低的轰击电压。无定形源极/漏极区域基本上阻碍了源极/漏极掺杂剂的扩散，从而降低了FET功能的穿透和损失的可能性。这种器件优选地用于NAND型闪速存储器件中，即使采用短沟道长度，它们也保持适当的自增强电压和FET功能。

6. 发明授权

US06566203B2 Method for preventing electron secondary injection in a pocket implantation process 有权
公开(公告)号：US06566203B2
公开(公告)日：2003-05-20
申请号：US09682341
申请日：2001-08-22
申请人： Kent Kuohua Chang , Samuel Cheng-Sheng Pan
发明人： Kent Kuohua Chang , Samuel Cheng-Sheng Pan
IPC分类号： H01L218234
CPC分类号： H01L21/26586 , H01L21/2652 , H01L21/3144 , H01L27/115 , H01L27/11568 , H01L29/1083
摘要： A method for preventing electron secondary injection in a pocket implantation process performed on a nitride read only memory (NROM). The NROM has an oxide-nitride-oxide (ONO) layer formed on a silicon substrate. A plurality of bit line masks, arranged in a column, is formed on the surface of the ONO layer. A plurality of N type bit lines is formed in a region of the substrate not covered by the bit line masks. The method starts by performing a pocket implantation process of Indium ions with low energy, high dosage and using an angle nearly parallel to the ONO layer, so as to prevent electron secondary injection. Also, a plurality of P-type ultra-shallow junctions is formed in the region of the substrate not covered by the bit line masks.

7. 发明授权

US06548425B2 Method for fabricating an ONO layer of an NROM 有权
公开(公告)号：US06548425B2
公开(公告)日：2003-04-15
申请号：US09851570
申请日：2001-05-10
申请人： Kent Kuohua Chang , Uway Tseng
发明人： Kent Kuohua Chang , Uway Tseng
IPC分类号： H01L2131
CPC分类号： H01L21/02238 , H01L21/02164 , H01L21/0217 , H01L21/02271 , H01L21/02332 , H01L21/02337 , H01L21/28282 , H01L21/3144 , H01L27/11568 , Y10S438/954
摘要： The present invention fabricates an oxide-nitride-oxide (ONO) layer of an NROM. A first oxide layer is formed on the surface of the substrate of a semiconductor wafer. Then two CVD processes are performed to respectively form a first nitride layer and a second nitride layer on the surface of the first oxide layer, and the boundary between the second nitride layer and the first nitride layer is so forming an interface. Thereafter, a second oxide layer is formed on the surface of the second nitride layer completing the process of manufacturing the ONO layer. The second nitride layer and the first nitride layer are used as a floating gate of the NROM, and the interface is used as a deep charge trapping center to improve the charge trapping efficiency, and furthermore, to improve the endurance and reliability of the NROM.

8. 发明授权

US06455890B1 Structure of fabricating high gate performance for NROM technology 有权
标题翻译： NROM技术制造高栅极性能的结构
公开(公告)号：US06455890B1
公开(公告)日：2002-09-24
申请号：US09945795
申请日：2001-09-05
申请人： Kent Kuohua Chang , Jen-Yuan Chiu
发明人： Kent Kuohua Chang , Jen-Yuan Chiu
IPC分类号： H01L29788
CPC分类号： H01L21/28273 , H01L29/42324 , H01L29/4916
摘要： A structure of fabricating high gate performance for NROM technology. The method at least includes the following steps. First of all, a tunnel oxide layer on the silicon substrate. Then, a amorphous silicon layer on the tunnel oxide layer, and a poly-SiGe layer (a polysilicon layer with doped germanium) on the amorphous silicon layer. Next, an interpoly dielectric layer on the poly-SiGe layer. Finally, a polysilicon layer on the interpoly dielectric layer.
摘要翻译： NROM技术制造高栅极性能的结构。该方法至少包括以下步骤。首先，硅衬底上的隧道氧化物层。然后，在非晶硅层上形成隧道氧化物层上的非晶硅层和多晶硅层（掺杂有锗的多晶硅层）。接下来，在多晶硅层上的多层介电层。最后，在多聚电介质层上的多晶硅层。

9. 发明授权

US06448136B1 Method of manufacturing flash memory 有权
标题翻译：闪存制造方法
公开(公告)号：US06448136B1
公开(公告)日：2002-09-10
申请号：US09777231
申请日：2001-02-05
申请人： Kent Kuohua Chang , Cheng-Chen Calvin Hsueh
发明人： Kent Kuohua Chang , Cheng-Chen Calvin Hsueh
IPC分类号： H01L218247
CPC分类号： H01L21/28017 , H01L21/28273 , Y10S438/908
摘要： A method of manufacturing flash memory. The method includes using a single wafer consecutive system process. A silicon wafer is placed inside one of the reaction chambers of a chemical vapor deposition station. Tunneling oxide layer, silicon nitride floating gate, silicon oxide layer and control gate are simultaneously formed over wafers inside the station. Breaking the vacuum inside the station and cleaning the wafer are unnecessary between various processing steps.
摘要翻译：一种制造闪存的方法。该方法包括使用单个晶片连续系统过程。将硅晶片放置在化学气相沉积站的一个反应室内。隧道内氧化物层，氮化硅浮栅，氧化硅层和控制栅极同时形成在工位内的晶片上。在各种处理步骤之间，不需要打破车站内的真空并清洁晶片。

10. 发明授权

US06355522B1 Effect of doped amorphous Si thickness on better poly 1 contact resistance performance for nand type flash memory devices 失效
标题翻译：掺杂非晶Si厚度对于n型闪存器件的更好的聚1接触电阻性能的影响
公开(公告)号：US06355522B1
公开(公告)日：2002-03-12
申请号：US09263699
申请日：1999-03-05
申请人： Kent Kuohua Chang , John Jianshi Wang , Yuesong He
发明人： Kent Kuohua Chang , John Jianshi Wang , Yuesong He
IPC分类号： H01L21336
CPC分类号： H01L21/28273 , H01L29/42324
摘要： In one embodiment, the present invention relates to a method of forming a flash memory cell, involving the steps of forming a tunnel oxide on a substrate; forming a first polysilicon layer over the tunnel oxide by chemical vapor deposition using a silicon containing gas and a mixture of a phosphorus containing gas and a carrier gas, the first polysilicon layer having a thickness from about 800 Å to about 1,000 Å; forming an insulating layer over the first polysilicon layer, the insulating layer comprising a first oxide layer over the first polysilicon layer, a nitride layer over the first oxide layer, and a second oxide layer over the nitride layer; forming a second polysilicon layer over the insulating layer; forming a tungsten silicide layer over the second polysilicon layer by chemical vapor deposition using WF6 and SiH2Cl2; etching at least the first polysilicon layer, the second polysilicon layer, the insulating layer, and the tungsten silicide layer thereby defining at least one stacked gate structure; and forming a source region and a drain region in the substrate, thereby forming at least one memory cell.
摘要翻译：在一个实施例中，本发明涉及一种形成闪速存储器单元的方法，包括在衬底上形成隧道氧化物的步骤; 通过使用含硅气体和含磷气体和载气的混合物通过化学气相沉积在隧道氧化物上形成第一多晶硅层，第一多晶硅层具有约800至约的厚度; 在所述第一多晶硅层上形成绝缘层，所述绝缘层包括所述第一多晶硅层上的第一氧化物层，所述第一氧化物层上的氮化物层和所述氮化物层上的第二氧化物层; 在所述绝缘层上形成第二多晶硅层; 通过使用WF 6和SiH 2 Cl 2的化学气相沉积在第二多晶硅层上形成硅化钨层; 至少蚀刻第一多晶硅层，第二多晶硅层，绝缘层和硅化钨层，从而限定至少一个堆叠栅极结构; 以及在衬底中形成源区和漏区，由此形成至少一个存储单元。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式