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1. 发明授权

US06831851B2 Mask ROM 有权
标题翻译：面具ROM
公开(公告)号：US06831851B2
公开(公告)日：2004-12-14
申请号：US10386554
申请日：2003-03-13
申请人： Fuh-Cheng Jong , Kent Kuohua Chang
发明人： Fuh-Cheng Jong , Kent Kuohua Chang
IPC分类号： G11C1700
CPC分类号： G11C17/12 , G11C7/18
摘要： The mask ROM of the present is comprises by a plurality of word lines arranged in a grid, a plurality of memory units arranged between the word lines, each memory unit having a drain corresponding, a plurality of first bit lines arranged in parallel and extending in a direction diagonal to the word lines and above the drains, a plurality of second bit lines arranged in parallel and extending in a direction diagonal to the word lines and above the drains, a plurality of first nodes alternately arranged on the first bit lines, a plurality of second nodes alternately arranged on the second bit lines and the second nodes and the first nodes are arranged alternately; a plurality of third bit lines joined to the first bit lines, and a plurality of fourth bit lines joined to the second bit lines.
摘要翻译：本发明的掩模ROM由排列成网格的多个字线，布置在字线之间的多个存储单元组成，每个存储单元具有对应的漏极，多个第一位线并行布置并且延伸与字线对应的方向和排水沟上方的方向，并列排列并沿与字线对角线方向并在排水沟上方延伸的多个第二位线，交替布置在第一位线上的多个第一节点，交替布置在第二位线上的多个第二节点和第二节点和第一节点交替布置; 连接到第一位线的多个第三位线，以及连接到第二位线的多个第四位线。

2. 发明授权

US06777742B2 Hexagonal gate structure for radiation resistant flash memory cell 有权
公开(公告)号：US06777742B2
公开(公告)日：2004-08-17
申请号：US10064882
申请日：2002-08-27
申请人： Fuh-cheng Jong , Kent Kuohua Chang
发明人： Fuh-cheng Jong , Kent Kuohua Chang
IPC分类号： H01L29792
CPC分类号： H01L29/66833 , H01L21/28282 , H01L29/42324 , H01L29/4238 , H01L29/792
摘要： A radiation resistant hexagonal gate flash memory cell. The flash memory cell includes a substrate, a source region, a drain region and a gate structure. A channel region is also formed in the substrate between the source region and the drain region. The gate structure is located above the substrate between the source region and the drain region. The gate structure further includes an oxide-nitride-oxide composite layer over the substrate. In a direction perpendicular to the channel, width of the gate structure increases gradually from the source region towards a pre-determined location and decreases towards the drain region thereafter. When the flash memory cell is subjected to radiation illumination, electron-hole pairs thus generated will be injected into the substrate without passing into the nitride layer. In a programming operation, a portion of the gate structure close to the source region serves as an equivalent source region having an area greater than the drain region so that second bit effect is greatly reduced.

3. 发明授权

US06762467B2 Nonvolatile memory cell for prevention of second bit effect 有权
标题翻译：用于防止第二位效应的非易失性存储单元
公开(公告)号：US06762467B2
公开(公告)日：2004-07-13
申请号：US10412592
申请日：2003-04-14
申请人： Fuh-Cheng Jong , Kent Kuohua Chang
发明人： Fuh-Cheng Jong , Kent Kuohua Chang
IPC分类号： H01L29792
CPC分类号： H01L29/7887 , H01L29/7923
摘要： A nonvolatile memory cell for prevention from second bit effect comprises a pair of source/drain regions arranged with a channel therebetween, a programmable layer above the channel, and a gate conductor above the programmable layer. The memory cell is characterized in that the programmable layer has a maximum width substantially larger than the boundary widths between the programmable layer and the source/drain regions. The programmable layer comprises a trapping dielectric layer inserted between two insulator layers, and the trapping dielectric preferably comprises a nitride or an oxide having buried polysilicon islands.
摘要翻译：用于防止第二位效应的非易失性存储单元包括一对排列成沟道的源极/漏极区域，通道上方的可编程层以及可编程层上方的栅极导体。存储单元的特征在于可编程层具有基本上大于可编程层与源极/漏极区之间的边界宽度的最大宽度。可编程层包括插入在两个绝缘体层之间的俘获电介质层，并且俘获电介质优选地包括具有掩埋多晶硅岛的氮化物或氧化物。

4. 发明授权

US06487114B2 Method of reading two-bit memories of NROM cell 有权
公开(公告)号：US06487114B2
公开(公告)日：2002-11-26
申请号：US09795937
申请日：2001-02-28
申请人： Fuh-Cheng Jong , Kent Kuohua Chang
发明人： Fuh-Cheng Jong , Kent Kuohua Chang
IPC分类号： G11C1604
CPC分类号： G11C16/26 , G11C16/0475
摘要： A method of reading two-bit information in Nitride Read only memory (NROM) cell simultaneously. According to outputted voltage in drain or source of the NROM, it can identify a logical two-bit combination massage of the NROM. The method includes: grounding the source of the NROM; inputting a voltage to the drain of the NROM; inputting a voltage to the gate of the NROM; measuring the outputted current of drain or source; and dividing the outputted current into four different zones, and each zone represents a specific logical two-bit information, which is “0 and 0”, “0 and 1”, “1 and 0”, or “1 and 1”.

5. 发明授权

US06538292B2 Twin bit cell flash memory device 有权
公开(公告)号：US06538292B2
公开(公告)日：2003-03-25
申请号：US09820294
申请日：2001-03-29
申请人： Kent Kuohua Chang , Fuh-Cheng Jong
发明人： Kent Kuohua Chang , Fuh-Cheng Jong
IPC分类号： H01L2976
CPC分类号： H01L21/28273 , H01L21/28282 , H01L29/7887
摘要： A semiconductor wafer comprises a semiconductor substrate of a first conductive type, a source and a drain of a second conductive type positioned in predetermined areas of the semiconductor substrate, and a channel positioned on the surface of the semiconductor substrate between the source and the drain. The memory device contains a first dielectric layer covering the surface of the channel. A conductive layer covers the surface of the first dielectric layer, the conductive layer containing an insulating region for separating the conductive layer so as to form two isolated conductive regions. A second dielectric layer covers the surface of the conductive layer. A gate covers the surface of the second dielectric layer. Each conductive region is used as a charge trapping layer so as to receive and store electrons injected into the conductive region, thus forming a twin bit cell flash memory device.

6. 发明授权

US06348381B1 Method for forming a nonvolatile memory with optimum bias condition 有权
标题翻译：用于形成具有最佳偏置条件的非易失性存储器的方法
公开(公告)号：US06348381B1
公开(公告)日：2002-02-19
申请号：US09788372
申请日：2001-02-21
申请人： Fuh-Cheng Jong , Kent Kuohua Chang
发明人： Fuh-Cheng Jong , Kent Kuohua Chang
IPC分类号： H01K218247
CPC分类号： H01L27/11568 , H01L27/115
摘要： A method for forming a nonvolatile memory with optimum bias condition is disclosed. Initially, an ONO structure is formed on the substrate wherein the ONO structure has a first oxide layer, a nitride layer and a second oxide layer. Afterwards, a plurality of openings is formed on the ONO structure and a portion of substrate is exposed. An optimum condition of a nonvolatile memory cell having a threshold voltage region wherein the threshold voltage region can be optimum by adjusting a lateral electric field between a drain and a gate to transfer a plurality of electrons into the ONO structure. Thereafter, an implant process is performed to form a plurality of bit lines on substrate. An oxide layer is formed on bit lines to create a bit lines oxide layer. Finally, a polysilicon is formed on bit lines oxide layer and the ONO structure to produce the nonvolatile memory cell. Alternatively, after a nonvolatile memory cell is made, the optimum threshold voltage region can be selected by adjusting a lateral electrical field between a drain and a gate to transfer a plurality of electrons into the ONO structure.
摘要翻译：公开了一种用于形成具有最佳偏置条件的非易失性存储器的方法。首先，在基板上形成ONO结构，其中ONO结构具有第一氧化物层，氮化物层和第二氧化物层。之后，在ONO结构上形成多个开口，并露出一部分基板。具有阈值电压区域的非易失性存储单元的最佳状态，其中通过调节漏极和栅极之间的横向电场来将阈值电压区域最优化，以将多个电子转移到ONO结构中。此后，执行注入工艺以在衬底上形成多个位线。在位线上形成氧化层以产生位线氧化物层。最后，在位线氧化层和ONO结构上形成多晶硅以产生非易失性存储单元。或者，在制造非易失性存储单元之后，可以通过调节漏极和栅极之间的横向电场来选择最佳阈值电压区域，以将多个电子转移到ONO结构中。

7. 发明授权

US06324092B1 Random access memory cell 有权
标题翻译：随机存取存储单元
公开(公告)号：US06324092B1
公开(公告)日：2001-11-27
申请号：US09781770
申请日：2001-02-12
申请人： Fuh-cheng Jong , Ming-Hung chou , Kent Kuohua Chang
发明人： Fuh-cheng Jong , Ming-Hung chou , Kent Kuohua Chang
IPC分类号： G11C700
CPC分类号： G11C11/404
摘要： A random access memory cell. The RAM cell includes a first transistor and a second transistor. A control gate of the first transistor is coupled to a control signal line. A data read terminal of the first transistor is coupled to a data read line. An earth terminal of the first transistor is connected to a ground. A floating gate terminal of the first transistor is located between a portion of a substrate and a portion of the control gate. A control gate of the second transistor is also coupled to the control signal line. The data write terminal of the second transistor is a data write line. A data transmission terminal of the second transistor is coupled to the floating gate of the first transistor. To write data into the RAM cell, a write control voltage is applied to the control signal line. Similarly, to read data from the RAM cell, a read control voltage is applied to the control signal line. The write control voltage is greater than the read control voltage.
摘要翻译：随机存取存储单元。 RAM单元包括第一晶体管和第二晶体管。第一晶体管的控制栅极耦合到控制信号线。第一晶体管的数据读取端子耦合到数据读取线。第一晶体管的接地端子连接到地。第一晶体管的浮置栅极位于基板的一部分和控制栅极的一部分之间。第二晶体管的控制栅极也耦合到控制信号线。第二晶体管的数据写入端子是数据写入线。第二晶体管的数据发送端子耦合到第一晶体管的浮置栅极。为了将数据写入RAM单元，向控制信号线施加写入控制电压。类似地，为了从RAM单元读取数据，读取控制电压被施加到控制信号线。写控制电压大于读控制电压。

8. 发明申请

US20120065741A1 GUIDED TISSUE REGENERATION MEMBRANE 审中-公开
标题翻译：指导组织再生膜
公开(公告)号：US20120065741A1
公开(公告)日：2012-03-15
申请号：US12880502
申请日：2010-09-13
申请人： Chao-Fu Chang , Kent Kuohua Chang
发明人： Chao-Fu Chang , Kent Kuohua Chang
IPC分类号： A61F2/02
CPC分类号： A61C8/0006 , A61L31/005 , A61L31/146
摘要： A guided tissue regeneration membrane has a top surface, a bottom surface and a plurality of through holes formed through the top and bottom surfaces. Each of the plurality of through holes has a base opening on the top surface and a tip opening on the bottom surface. The diameter of the base opening is larger than that of the tip opening. The guided tissue regeneration membrane is placed between a hard tissue and a soft tissue of gums with the top surface thereof facing the hard tissue so as to hinder the soft tissue from rapidly growing. The tip openings are available for the soft tissue to supply nutrient to the hard tissue therethrough. The hard tissue can grow from the base openings, through the corresponding through holes and to the soft tissue to repair periodontal tissue.
摘要翻译：引导组织再生膜具有顶表面，底表面和穿过顶表面和底表面形成的多个通孔。多个通孔中的每一个在顶表面上具有基部开口，在底面上具有顶端开口。基座开口的直径大于顶端开口的直径。引导组织再生膜置于硬组织和牙龈软组织之间，其顶表面面向硬组织，以阻止软组织迅速生长。尖端开口可用于软组织，以通过其中的硬组织提供营养。硬组织可以从基底开口，通过相应的通孔和软组织生长，以修复牙周组织。

9. 发明授权

US06706612B2 Fabrication method for shallow trench isolation 有权
标题翻译：浅沟槽隔离的制作方法
公开(公告)号：US06706612B2
公开(公告)日：2004-03-16
申请号：US10064370
申请日：2002-07-08
申请人： Szu-Tsun Ma , Kent Kuohua Chang
发明人： Szu-Tsun Ma , Kent Kuohua Chang
IPC分类号： H01L2176
CPC分类号： H01L21/76224
摘要： A method for fabricating a shallow trench isolation structure includes forming a hard mask layer over a substrate. An ion bombardment step is further performed on the surface of the hard mask layer, followed by forming a patterned photoresist layer on the surface of the hard mask layer. Thereafter, the hard mask layer is patterned using the photoresist layer as an etching mask. An etching process is further performed to form a trench in the substrate. The photoresist layer is then removed, followed by filling an insulation layer in the trench. After this, the hard mask is removed to complete the fabrication of a shallow trench isolation region.
摘要翻译：一种用于制造浅沟槽隔离结构的方法包括在衬底上形成硬掩模层。在硬掩模层的表面上进一步进行离子轰击步骤，然后在硬掩模层的表面上形成图案化的光致抗蚀剂层。此后，使用光致抗蚀剂层作为蚀刻掩模来对硬掩模层进行图案化。进一步进行蚀刻工艺以在衬底中形成沟槽。然后去除光致抗蚀剂层，然后在沟槽中填充绝缘层。之后，去除硬掩模以完成浅沟槽隔离区的制造。

10. 发明授权

US06599801B1 Method of fabricating NROM memory cell 有权
标题翻译：制造NROM记忆体的方法
公开(公告)号：US06599801B1
公开(公告)日：2003-07-29
申请号：US10178524
申请日：2002-06-25
申请人： Kent Kuohua Chang , Erh-Kun Lai
发明人： Kent Kuohua Chang , Erh-Kun Lai
IPC分类号： H01L21336
CPC分类号： H01L27/11568 , H01L27/105 , H01L27/115 , H01L27/11573
摘要： A method of fabricating NROM memory cell, wherein the NROM device comprises a memory array and a peripheral portion. The fabricating method comprising the steps of: providing a substrate which a oxide layer is formed thereon; forming a peripheral polysilicon layer on the oxide layer; defining a patterned peripheral polysilicon; forming an ONO layer over the substrate in the memory array and the peripheral portion; forming an array polysilicon layer on the ONO layer; and defining a patterned array polysilicon. The method of fabricating NROM memory cell according to the invention can solve the problems of top oxide loss, touch between nitride and polysilicon, and BD over-diffusion.
摘要翻译：一种制造NROM存储单元的方法，其中NROM器件包括存储器阵列和外围部分。该制造方法包括以下步骤：提供在其上形成氧化物层的衬底; 在所述氧化物层上形成外围多晶硅层; 限定图案化的外围多晶硅; 在存储器阵列和周边部分中的衬底上形成ONO层; 在ONO层上形成阵列多晶硅层; 并且限定图案化阵列多晶硅。根据本发明的制造NROM存储单元的方法可以解决顶部氧化物损失，氮化物和多晶硅之间的接触以及BD过度扩散的问题。

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