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61. 发明授权

US6116768A Three input arithmetic logic unit with barrel rotator 失效
标题翻译：三输入算术逻辑单元，带桶旋转器
公开(公告)号：US6116768A
公开(公告)日：2000-09-12
申请号：US160299
申请日：1993-11-30
申请人： Karl M. Guttag , Keith Balmer , Robert J. Gove , Christopher J. Read , Jeremiah E. Golston , Sydney W. Poland , Nicholas Ing-Simmons , Phillip Moyse
发明人： Karl M. Guttag , Keith Balmer , Robert J. Gove , Christopher J. Read , Jeremiah E. Golston , Sydney W. Poland , Nicholas Ing-Simmons , Phillip Moyse
IPC分类号： G06F5/01 , G06F9/302 , G06F9/305 , G06F9/308 , G06F9/315 , G06F9/32 , G06F12/02 , G06F7/36
CPC分类号： G06F9/30014 , G06F12/0284 , G06F5/015 , G06F9/30018 , G06F9/30029 , G06F9/30032 , G06F9/30036 , G06F9/30094 , G06F9/30167 , G06F9/325
摘要： A data processing apparatus includes a three input arithmetic logic unit (230) that generates a combination of the three inputs that is selected by a function signal. Data registers (200) store the three data inputs and the arithmetic logic unit output. The second input signal comes from a controllable barrel rotator (235). The rotate amount is a default rotate amount stored in a special data register, a predetermined set of bits of data recalled from a data register or zero. A one's constant source (236) is connected to the barrel rotator (235) to supply a multibit digital signal of "1". This permits generating a second input signal of the form 2.sup.N, with N being the rotate amount. The output of the barrel rotator (235) may be stored independently of the arithmetic logic unit (230) result. In the preferred embodiment of this invention, the three input arithmetic logic unit (230) is embodied in a data processor circuits as a part of a multiprocessor integrated circuit (100) used in image processing.
摘要翻译：数据处理装置包括产生由功能信号选择的三个输入的组合的三输入算术逻辑单元（230）。数据寄存器（200）存储三个数据输入和算术逻辑单元输出。第二输入信号来自可控筒旋转器（235）。旋转量是存储在特殊数据寄存器中的默认旋转量，从数据寄存器或零调用的预定数据位组。恒定源（236）连接到筒旋转器（235）以提供“1”的多位数字信号。这允许产生形式2N的第二输入信号，其中N是旋转量。桶旋转器（235）的输出可以独立于算术逻辑单元（230）的结果存储。在本发明的优选实施例中，三输入算术逻辑单元（230）被实现为作为在图像处理中使用的多处理器集成电路（100）的一部分的数据处理器电路。

62. 发明授权

US6070003A System and method of memory access in apparatus having plural processors and plural memories 失效
标题翻译：具有多个处理器和多个存储器的设备中的存储器访问的系统和方法
公开(公告)号：US6070003A
公开(公告)日：2000-05-30
申请号：US264582
申请日：1994-06-22
申请人： Robert J. Gove , Keith Balmer , Nicholas Kerin Ing-Simmons , Karl Marion Guttag
发明人： Robert J. Gove , Keith Balmer , Nicholas Kerin Ing-Simmons , Karl Marion Guttag
IPC分类号： G06F15/173 , G06F13/16
CPC分类号： G06F15/17375
摘要： There is disclosed a multi-processor system and method arranged, in one embodiment, as an image and graphics processor. The image processor is structured with several individual processors all having communication links to several memories. A crossbar switch serves to establish the processor memory links. The entire image processor, including the individual processors, the crossbar switch and the memories, is contained on a single silicon chip.
摘要翻译：已经公开了在一个实施例中将图像处理器和图形处理器设置为多处理器系统和方法。图像处理器被构造成具有几个单独的处理器，它们都具有到几个存储器的通信链路。交叉开关用于建立处理器存储器链路。整个图像处理器（包括各个处理器，交叉开关和存储器）都包含在单个硅芯片上。

63. 发明授权

US5961635A Three input arithmetic logic unit with barrel rotator and mask generator 失效
标题翻译：三输入算术逻辑单元，带筒式旋转器和面罩发生器
公开(公告)号：US5961635A
公开(公告)日：1999-10-05
申请号：US160111
申请日：1993-11-30
申请人： Karl M. Guttag , Keith Balmer , Robert J. Gove , Christopher J. Read , Jeremiah E. Golston , Sydney W. Poland , Nicholas Ing-Simmons , Phillip Moyse
发明人： Karl M. Guttag , Keith Balmer , Robert J. Gove , Christopher J. Read , Jeremiah E. Golston , Sydney W. Poland , Nicholas Ing-Simmons , Phillip Moyse
IPC分类号： G06F5/01 , G06F7/575 , G06F7/76 , G06F9/30
CPC分类号： G06F7/764 , G06F5/01 , G06F7/575
摘要： A three input arithmetic logic unit (230) that generates a combination of the three inputs that is selected by a function signal. The second input signal comes from a controllable barrel rotator (235). The rotate amount is a default rotate amount stored in a special data register, a predetermined set of bits of data recalled from a data register or zero. A one's constant source (236) is connected to the barrel rotator (235) to supply a multibit digital signal of "1". This permits generating a second input signal of the form 2.sup.N, with N being the rotate amount. The output of the barrel rotator (235) may be stored independently of the arithmetic logic unit (230) result. The third input signal comes from a multiplexer (233) that selects between an instruction specified immediate field, data recalled from a data register or a mask input from a mask generator (239). One preferred form of the mask has a number of right justified 1's corresponding to a mask input signal. This mask input signal may be the default barrel rotate amount or a predetermined number of the least significant bits of a third input signal as selected by a multiplexer. A second preferred form of the mask is selected one of the left most 1, the right most 1, the left most bit change or the right most bit change of a predetermined set of the least significant bits of data recalled from a data register.
摘要翻译：三输入算术逻辑单元（230），其生成由功能信号选择的三个输入的组合。第二输入信号来自可控筒旋转器（235）。旋转量是存储在特殊数据寄存器中的默认旋转量，从数据寄存器或零调用的预定数据位组。恒定源（236）连接到筒旋转器（235）以提供“1”的多位数字信号。这允许产生形式2N的第二输入信号，其中N是旋转量。桶旋转器（235）的输出可以独立于算术逻辑单元（230）的结果存储。第三输入信号来自多路复用器（233），其在指定的指令字段，从数据寄存器调用的数据或从掩码生成器输入的掩码（239）之间进行选择。掩模的一个优选形式具有对应于掩模输入信号的许多右对齐1。该掩模输入信号可以是由多路复用器选择的默认桶旋转量或第三输入信号的预定数量的最低有效位。选择掩模的第二优选形式是从数据寄存器回调的数据的最低有效位的预定集合的最左1，最右1，最左位变化或最右位变化中的一个。

64. 发明授权

US5761726A Base address generation in a multi-processing system having plural memories with a unified address space corresponding to each processor 失效
标题翻译：在具有与每个处理器对应的统一地址空间的多个存储器的多处理系统中产生基地址
公开(公告)号：US5761726A
公开(公告)日：1998-06-02
申请号：US479981
申请日：1995-06-07
申请人： Karl M. Guttag , Keith Balmer , Robert J. Gove , Christopher J. Read , Jeremiah E. Golston , Sydney W. Poland , Nicholas Ing-Simmons , Philip Moyse
发明人： Karl M. Guttag , Keith Balmer , Robert J. Gove , Christopher J. Read , Jeremiah E. Golston , Sydney W. Poland , Nicholas Ing-Simmons , Philip Moyse
IPC分类号： G06F5/01 , G06F9/302 , G06F9/305 , G06F9/308 , G06F9/315 , G06F9/32 , G06F12/02 , G06F12/00
CPC分类号： G06F9/30014 , G06F12/0284 , G06F5/015 , G06F9/30018 , G06F9/30029 , G06F9/30032 , G06F9/30036 , G06F9/30094 , G06F9/30167 , G06F9/325
摘要： A multi-processing system includes a plurality of memories and a plurality of processors. Each of the memories has a unique addressable memory portion of a single memory address space. Each processors has a predetermined plurality of corresponding memories. These corresponding memories have a corresponding base address within said single memory address space The processors generate addresses for read/write access to data stored within said plurality of memories in accordance with received instructions. A switch matrix connected to the memories and the processors responds to an address generated by a processor to selectively route data between that processor and a memories whose unique addressable memory portion encompasses that address. A base address instruction executing on any one of the processors generates the base address corresponding to that processor. The base address preferably is substituted for the contents of a base address register in an address unit including a set of base address registers, a set of index address registers and a full adder.
摘要翻译：多处理系统包括多个存储器和多个处理器。每个存储器具有单个存储器地址空间的唯一可寻址存储器部分。每个处理器具有预定的多个对应的存储器。这些相应的存储器在所述单个存储器地址空间内具有对应的基址。根据接收到的指令，处理器产生用于对存储在所述多个存储器中的数据进行读/写访问的地址。连接到存储器和处理器的开关矩阵响应由处理器产生的地址，以选择性地在该处理器与其唯一可寻址存储器部分包含该地址的存储器之间路由数据。在任一个处理器上执行的基地址指令产生与该处理器对应的基地址。基址优选地代替包括一组基地址寄存器，一组索引地址寄存器和全加器的地址单元中的基地址寄存器的内容。

65. 发明授权

US5758195A Register to memory data transfers with field extraction and zero/sign extension based upon size and mode data corresponding to employed address register 失效
标题翻译：根据对应于所采用的地址寄存器的大小和模式数据，对场提取和零/符号扩展进行存储器数据传输
公开(公告)号：US5758195A
公开(公告)日：1998-05-26
申请号：US487201
申请日：1995-06-07
申请人： Keith Balmer
发明人： Keith Balmer
IPC分类号： G06F9/30 , G06F9/312 , G06F9/315 , G06F9/318 , G06F9/355 , G06F9/38 , G06F12/04
CPC分类号： G06F9/30043 , G06F9/30032 , G06F9/30036 , G06F9/30087 , G06F9/30112 , G06F9/3013 , G06F9/30145 , G06F9/3016 , G06F9/30167 , G06F9/30192 , G06F9/321 , G06F9/325 , G06F9/355 , G06F9/3832 , G06F9/3885
摘要： A data processing system including a data-memory storing data words having a first data size, and a data processor having an address generator generating addresses pointing to data of a second data size smaller than the first data size. The data processing system enables a data transfer by supplying an address to the data memory with zeros substituted for a predetermined number of least significant bits. The data processor receives a data word of the first data size corresponding to the altered address. The data processor stores data of a selected processor data size into a selected data register. If the processor data size is smaller than the first data size, then the date register stores a selected a subset of bits of the data word dependent upon the processor data size and the predetermined number of least significant address bits of said address. The selected processor data size is stored in a qualifier register which may be one of a plurality of qualifier registers corresponding to an address register used to generate the address. The data memory includes a plurality of write strobe inputs. The data processor repeats data recalled from a selected data registers of the selected processor data size a number of times to fill a data word of the first data size. The data processor enables selected write strobes dependent upon the processor data size and the predetermined number of least significant bits of the address.
摘要翻译：一种数据处理系统，包括存储具有第一数据大小的数据字的数据存储器和具有地址生成器的数据处理器，该地址生成器产生指向小于第一数据大小的第二数据大小的数据的地址。数据处理系统通过用代替预定数量的最低有效位的零来向数据存储器提供地址来实现数据传输。数据处理器接收与改变的地址对应的第一数据大小的数据字。数据处理器将所选择的处理器数据大小的数据存储到所选择的数据寄存器中。如果处理器数据大小小于第一数据大小，则日期寄存器根据处理器数据大小和所述地址的预定数目的最低有效地址位来存储选定的数据字的位的子集。所选择的处理器数据大小存储在限定符寄存器中，限定符寄存器可以是与用于生成地址的地址寄存器相对应的多个限定符寄存器之一。数据存储器包括多个写选通输入。数据处理器重复从所选择的处理器数据大小的所选择的数据寄存器中召回的数据，以填充第一数据大小的数据字。数据处理器使得所选择的写入选通取决于处理器数据大小和地址的预定数量的最低有效位。

66. 发明授权

US5634065A Three input arithmetic logic unit with controllable shifter and mask generator 失效
标题翻译：三输入算术逻辑单元，带可控制移位器和掩码发生器
公开(公告)号：US5634065A
公开(公告)日：1997-05-27
申请号：US475134
申请日：1995-06-07
申请人： Karl M. Guttag , Keith Balmer , Robert J. Gove , Christopher J. Read , Jeremiah E. Golston , Sydney W. Poland , Nicholas Ing-Simmons , Philip Moyse
发明人： Karl M. Guttag , Keith Balmer , Robert J. Gove , Christopher J. Read , Jeremiah E. Golston , Sydney W. Poland , Nicholas Ing-Simmons , Philip Moyse
IPC分类号： G06F5/01 , G06F7/575 , G06F7/76 , G06F7/38
CPC分类号： G06F7/764 , G06F5/01 , G06F7/575
摘要： A three input arithmetic logic unit (230) that generates a combination of the three inputs that is selected by a function signal. The second input signal comes from a controllable barrel rotator (235). The rotate amount is a default rotate amount stored in a special data register, a predetermined set of bits of data recalled from a data register or zero. A one's constant source (236) is connected to the barrel rotator (235) to supply a multibit digital signal of "1". This permits generating a second input signal of the form 2.sup.N, with N being the rotate amount. The output of the barrel rotator (235) may be stored independently of the arithmetic logic unit (230) result. The third input signal comes from a multiplexer (233) that selects between an instruction specified immediate field, data recalled from a data register or a mask input from a mask generator (239). One preferred form of the mask has a number of right justified 1's corresponding to a mask input signal. This mask input signal may be the default barrel rotate amount or a predetermined number of the least significant bits of a third input signal as selected by a multiplexer. A second preferred form of the mask is selected one of the left most 1, the right most 1, the left most bit change or the right most bit change of a predetermined set of the least significant bits of data recalled from a data register.
摘要翻译：三输入算术逻辑单元（230），其生成由功能信号选择的三个输入的组合。第二输入信号来自可控筒旋转器（235）。旋转量是存储在特殊数据寄存器中的默认旋转量，从数据寄存器或零调用的预定数据位组。恒定源（236）连接到筒旋转器（235）以提供“1”的多位数字信号。这允许产生形式2N的第二输入信号，其中N是旋转量。桶旋转器（235）的输出可以独立于算术逻辑单元（230）的结果存储。第三输入信号来自多路复用器（233），其在指定的指令字段，从数据寄存器调用的数据或从掩码生成器输入的掩码（239）之间进行选择。掩模的一个优选形式具有对应于掩模输入信号的许多右对齐1。该掩模输入信号可以是由多路复用器选择的默认桶旋转量或第三输入信号的预定数量的最低有效位。选择掩模的第二优选形式是从数据寄存器回调的数据的最低有效位的预定集合的最左1，最右1，最左位变化或最右位变化中的一个。

67. 发明授权

US5600847A Three input arithmetic logic unit with mask generator 失效
标题翻译：三输入算术逻辑单元与掩码发生器
公开(公告)号：US5600847A
公开(公告)日：1997-02-04
申请号：US475162
申请日：1995-06-07
申请人： Karl M. Guttag , Keith Balmer , Robert J. Gove , Christopher J. Read , Jeremiah E. Golston , Sydney W. Poland , Nicholas Ing-Simmons , Philip Moyse
发明人： Karl M. Guttag , Keith Balmer , Robert J. Gove , Christopher J. Read , Jeremiah E. Golston , Sydney W. Poland , Nicholas Ing-Simmons , Philip Moyse
IPC分类号： G06F7/57 , G06F7/38
CPC分类号： G06F7/57
摘要： A data processing apparatus includes a three input arithmetic logic unit (230) that generates a combination of the three inputs that is selected by a function signal. Data registers (200) store the three data inputs and the arithmetic logic unit output. The second input signal comes from a controllable barrel rotator (235). The rotate amount is a default rotate amount stored in a special data register, a predetermined set of bits of data recalled from a data register or zero. A one's constant source (236) is connected to the barrel rotator (235) to supply a multibit digital signal of "1". This permits generating a second input signal of the form 2.sup.N, with N being the rotate amount. The output of the barrel rotator (235) may be stored independently of the arithmetic logic unit (230) result. A controllable shifter is an alternative to the barrel rotator (235). The third input signal comes from a multiplexer (233) that selects between an instruction specified immediate field, data recalled from a data register or a mask input from a mask generator (239). One preferred form of the mask has a number of right justified 1's corresponding to a mask input signal. This mask input signal may be the default barrel rotate amount or a predetermined number of the least significant bits of a third input signal as selected by a multiplexer. A second preferred form of the mask is selected one of the left most 1, the right most 1, the left most bit change or the right most bit change of a predetermined set of the least significant bits of data recalled from a data register. In the preferred embodiment of this invention, the three input arithmetic logic unit (230) is embodied in a data processor circuits as a part of a multiprocessor integrated circuit (100) used in image processing.
摘要翻译：数据处理装置包括产生由功能信号选择的三个输入的组合的三输入算术逻辑单元（230）。数据寄存器（200）存储三个数据输入和算术逻辑单元输出。第二输入信号来自可控筒旋转器（235）。旋转量是存储在特殊数据寄存器中的默认旋转量，从数据寄存器或零调用的预定数据位组。恒定源（236）连接到筒旋转器（235）以提供“1”的多位数字信号。这允许产生形式2N的第二输入信号，其中N是旋转量。桶旋转器（235）的输出可以独立于算术逻辑单元（230）的结果存储。可控制的换档器是桶旋转器（235）的替代品。第三输入信号来自多路复用器（233），其在指定的指令字段，从数据寄存器调用的数据或从掩码生成器输入的掩码（239）之间进行选择。掩模的一个优选形式具有对应于掩模输入信号的许多右对齐1。该掩模输入信号可以是由多路复用器选择的默认桶旋转量或第三输入信号的预定数量的最低有效位。选择掩模的第二优选形式是从数据寄存器回调的数据的最低有效位的预定集合的最左1，最右1，最左位变化或最右位变化中的一个。在本发明的优选实施例中，三输入算术逻辑单元（230）被实现为作为在图像处理中使用的多处理器集成电路（100）的一部分的数据处理器电路。

68. 发明授权

US5592405A Multiple operations employing divided arithmetic logic unit and multiple flags register 失效
标题翻译：多个操作采用分割算术逻辑单元和多个标志寄存器
公开(公告)号：US5592405A
公开(公告)日：1997-01-07
申请号：US484579
申请日：1995-06-07
申请人： Robert J. Gove , Karl M. Guttag , Keith Balmer , Nicholas K. Ing-Simmons
发明人： Robert J. Gove , Karl M. Guttag , Keith Balmer , Nicholas K. Ing-Simmons
IPC分类号： G06F15/167 , G06F12/02 , G06F12/06 , G06F15/173 , G06F15/80 , G06F7/38 , G06F7/00 , G06F7/50
CPC分类号： G06F15/17375 , G06F12/0284
摘要： A data processing apparatus includes an arithmetic logic unit is divided into a plurality of sections. Each section generates at a corresponding output a digital resultant signal representing a combination of respective subsets of first and second multibit digital inputs. The arithmetic logic unit includes a status detector generating a single bit status signal indicative of said digital resultant signal of a corresponding section of the arithmetic logic unit. These single bit status signals are stored in predetermined locations within a multiple flags register. An options register stores an indication of the number of sections selected from a plurality of possible number of sections into which the arithmetic logic unit is divided. The arithmetic logic unit is further connected to the multiple flags register so that each section selects for output either corresponding bits of the first multibit digital input or the second multibit digital input dependent upon the digital state of a corresponding single status bit in the multiple flags register. This technique permits a variety of functions such as add with saturation, maximum, pixel transparency and color expansion.
摘要翻译：一种数据处理装置，包括被分成多个部分的算术逻辑单元。每个部分在相应的输出处产生表示第一和第二多位数字输入的各个子集的组合的数字结果信号。算术逻辑单元包括状态检测器，其产生指示算术逻辑单元的相应部分的所述数字结果信号的单位状态信号。这些单位状态信号存储在多标志寄存器内的预定位置。选项寄存器存储从算术逻辑单元划分到的多个可能数量的区段中选择的区段数量的指示。算术逻辑单元还连接到多标志寄存器，使得每个部分选择输出第一多位数字输入或第二多位数字输入的对应位，取决于多标志寄存器中对应的单个状态位的数字状态。这种技术允许各种功能，如饱和度，最大值，像素透明度和颜色扩展等。

69. 发明授权

US5590350A Three input arithmetic logic unit with mask generator 失效
标题翻译：三输入算术逻辑单元与掩码发生器
公开(公告)号：US5590350A
公开(公告)日：1996-12-31
申请号：US159282
申请日：1993-11-30
申请人： Karl M. Guttag , Keith Balmer , Robert J. Gove , Christopher J. Read , Jeremiah E. Golston , Sydney W. Poland , Nicholas Ing-Simmons , Philip Moyse
发明人： Karl M. Guttag , Keith Balmer , Robert J. Gove , Christopher J. Read , Jeremiah E. Golston , Sydney W. Poland , Nicholas Ing-Simmons , Philip Moyse
IPC分类号： G06F7/57 , G06F9/00 , H03K19/00
CPC分类号： G06F7/57
摘要： A data processing apparatus includes a three input arithmetic logic unit (230) that generates a combination of the three inputs that is selected by a function signal. Data registers (200) store the three data inputs and the arithmetic logic unit output. The second input signal comes from a controllable barrel rotator (235). The rotate amount is a default rotate amount stored in a special data register, a predetermined set of bits of data recalled from a data register or zero. A one's constant source (236) is connected to the barrel rotator (235) to supply a multibit digital signal of "1". This permits generating a second input signal of the form 2.sup.N, with N being the rotate amount. The output of the barrel rotator (235) may be stored independently of the arithmetic logic unit (230) result. A controllable shifter is an alternative to the barrel rotator (235). The third input signal comes from a multiplexer (233) that selects between an instruction specified immediate field, data recalled from a data register or a mask input from a mask generator (239). One preferred form of the mask has a number of right justified 1's corresponding to a mask input signal. This mask input signal may be the default barrel rotate amount or a predetermined number of the least significant bits of a third input signal as selected by a multiplexer. A second preferred form of the mask is selected one of the left most 1, the right most 1, the left most bit change or the right most bit change of a predetermined set of the least significant bits of data recalled from a data register. In the preferred embodiment of this invention, the three input arithmetic logic unit (230) is embodied in a data processor circuits as a part of a multiprocessor integrated circuit (100) used in image processing.
摘要翻译：数据处理装置包括产生由功能信号选择的三个输入的组合的三输入算术逻辑单元（230）。数据寄存器（200）存储三个数据输入和算术逻辑单元输出。第二输入信号来自可控筒旋转器（235）。旋转量是存储在特殊数据寄存器中的默认旋转量，从数据寄存器或零调用的预定数据位组。恒定源（236）连接到筒旋转器（235）以提供“1”的多位数字信号。这允许产生形式2N的第二输入信号，其中N是旋转量。桶旋转器（235）的输出可以独立于算术逻辑单元（230）的结果存储。可控制的换档器是桶旋转器（235）的替代品。第三输入信号来自多路复用器（233），其在指定的指令字段，从数据寄存器调用的数据或从掩码生成器输入的掩码（239）之间进行选择。掩模的一个优选形式具有对应于掩模输入信号的许多右对齐1。该掩模输入信号可以是由多路复用器选择的默认桶旋转量或第三输入信号的预定数量的最低有效位。选择掩模的第二优选形式是从数据寄存器回调的数据的最低有效位的预定集合的最左1，最右1，最左位变化或最右位变化中的一个。在本发明的优选实施例中，三输入算术逻辑单元（230）被实现为作为在图像处理中使用的多处理器集成电路（100）的一部分的数据处理器电路。

70. 发明授权

US5487146A Plural memory access address generation employing guide table entries forming linked list 失效
标题翻译：使用指导表条目形成链表的多个存储器访问地址生成
公开(公告)号：US5487146A
公开(公告)日：1996-01-23
申请号：US209124
申请日：1994-03-08
申请人： Karl M. Guttag , Sydney W. Poland , Keith Balmer , Robert J. Gove , Christopher J. Read
发明人： Karl M. Guttag , Sydney W. Poland , Keith Balmer , Robert J. Gove , Christopher J. Read
IPC分类号： G06F13/28 , G09G5/393 , G06F12/06
CPC分类号： G06F13/28 , G09G5/393
摘要： A data processing device includes a memory, a control circuit, a guide table and an address generating circuit. The control circuit receives a packet transfer request and packet transfer parameters. The packet transfer parameters include a start address, dimension values defining a block of addresses, guide table having guide table entries and a table pointer. Each guide table entry has an address value. The table pointer initially points to a first guide table entry in the guide table. The address generating circuit forms a set of a block of addresses for memory access corresponding to each guide table entry, having a start address from a predetermined combination of the start address and the address value of the guide table entry. The block of addresses are formed from the dimension values. Following the memory accesses, the address generating circuit updates the table pointer to point to a next entry in the guide table. The address generating circuit may add the address value to the prior block starting address or add the guide table value to the starting address. The memory access may be a memory read from the block of addresses or a memory write to the block of addresses.
摘要翻译：数据处理装置包括存储器，控制电路，引导表和地址产生电路。控制电路接收分组传送请求和分组传送参数。分组传送参数包括起始地址，定义地址块的维度值，具有指导表条目的指南表和表指针。每个指南表项具有地址值。表指针最初指向指南表中的第一个指南表项。地址生成电路形成与每个指导表条目对应的用于存储器访问的地址块的集合，具有来自引导表条目的起始地址和地址值的预定组合的起始地址。地址块由维度值形成。在存储器访问之后，地址产生电路更新表指针以指向指南表中的下一条目。地址产生电路可以将地址值添加到先前块开始地址，或者将引导表值添加到起始地址。存储器访问可以是从地址块读取的存储器或写入地址块的存储器。

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