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61. 发明授权

US08927387B2 Robust isolation for thin-box ETSOI MOSFETS 有权
标题翻译：薄型ETSOI MOSFET的强大隔离性
公开(公告)号：US08927387B2
公开(公告)日：2015-01-06
申请号：US13442168
申请日：2012-04-09
申请人： Kangguo Cheng , Bruce B Doris , Balasubramanian S Haran , Sanjay Mehta , Stefan Schmitz
发明人： Kangguo Cheng , Bruce B Doris , Balasubramanian S Haran , Sanjay Mehta , Stefan Schmitz
IPC分类号： H01L27/088 , H01L21/336 , H01L21/762
CPC分类号： H01L21/84 , H01L21/76283 , H01L27/1203
摘要： A thin BOX ETSOI device with robust isolation and method of manufacturing. The method includes providing a wafer with at least a pad layer overlying a first semiconductor layer overlying an oxide layer overlying a second semiconductor layer, wherein the first semiconductor layer has a thickness of 10 nm or less. The process continues with etching a shallow trench into the wafer, extending partially into the second semiconductor layer and forming first spacers on the sidewalls of said shallow trench. After spacer formation, the process continues by etching an area directly below and between the first spacers, exposing the underside of the first spacers, forming second spacers covering all exposed portions of the first spacers, wherein the pad oxide layer is removed, and forming a gate structure over the first semiconductor wafer.
摘要翻译：薄型BOX ETSOI器件，具有强大的隔离性和制造方法。该方法包括提供晶片至少一覆盖在覆盖第二半导体层的氧化物层上的第一半导体层的焊盘层，其中第一半导体层具有10nm或更小的厚度。该过程继续蚀刻到晶片中的浅沟槽，部分地延伸到第二半导体层中并且在所述浅沟槽的侧壁上形成第一间隔物。在间隔物形成之后，该过程继续蚀刻直接在第一间隔物下面和之间的区域，暴露第一间隔物的下侧，形成覆盖第一间隔物的所有暴露部分的第二间隔区，其中除去氧化垫层，第一半导体晶片上的栅极结构。

62. 发明授权

US08889562B2 Double patterning method 有权
标题翻译：双重图案化方法
公开(公告)号：US08889562B2
公开(公告)日：2014-11-18
申请号：US13555306
申请日：2012-07-23
申请人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Ying Zhang
发明人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Ying Zhang
IPC分类号： H01L21/302
CPC分类号： H01L21/3086 , H01B13/00 , H01B19/04 , H01L21/0337 , H01L21/3081 , H01L21/32134 , H01L21/32137
摘要： Disclosed is an improved double patterning method for forming openings (e.g., vias or trenches) or mesas on a substrate. This method avoids the wafer topography effects seen in prior art double patterning techniques by ensuring that the substrate itself is only subjected to a single etch process. Specifically, in the method, a first mask layer is formed on the substrate and processed such that it has a doped region and multiple undoped regions within the doped region. Then, either the undoped regions or the doped region can be selectively removed in order to form a mask pattern above the substrate. Once the mask pattern is formed, an etch process can be performed to transfer the mask pattern into the substrate. Depending upon whether the undoped regions are removed or the doped region is removed, the mask pattern will form openings (e.g., vias or trenches) or mesas, respectively, on the substrate.
摘要翻译：公开了一种用于在基板上形成开口（例如，通孔或沟槽）或台面的改进的双重图案化方法。该方法通过确保衬底本身仅经历单次蚀刻工艺来避免现有技术的双重图案化技术中所见到的晶片形貌效应。具体地说，在该方法中，在衬底上形成第一掩模层并进行处理，使得其在掺杂区域内具有掺杂区域和多个未掺杂区域。然后，可以选择性地去除未掺杂区域或掺杂区域，以在衬底上方形成掩模图案。一旦形成掩模图案，就可以执行蚀刻工艺以将掩模图案转印到基板中。取决于未掺杂的区域是去除还是去除掺杂区域，掩模图案将分别在衬底上形成开口（例如，通孔或沟槽）或台面。

63. 发明授权

US08835250B2 FinFET trench circuit 有权
标题翻译： FinFET沟槽电路
公开(公告)号：US08835250B2
公开(公告)日：2014-09-16
申请号：US13613684
申请日：2012-09-13
申请人： Jonathan E. Faltermeier , Veeraraghavan S. Basker , Kangguo Cheng , Theodorus Eduardus Standaert
发明人： Jonathan E. Faltermeier , Veeraraghavan S. Basker , Kangguo Cheng , Theodorus Eduardus Standaert
IPC分类号： H01L21/8242 , H01L21/20 , H01L29/94 , H01L27/108 , H01L29/66
CPC分类号： H01L27/10829 , H01L21/845 , H01L27/10826 , H01L27/10832 , H01L27/10861 , H01L27/10867 , H01L27/10879 , H01L27/1207 , H01L27/1211 , H01L29/66181 , H01L29/945
摘要： A finFET trench circuit is disclosed. FinFETs are integrated with trench capacitors by employing a trench top oxide over a portion of the trench conductor. A passing gate is then disposed over the trench top oxide to form a larger circuit, such as a DRAM array. The trench top oxide is formed by utilizing different growth rates between polysilicon and single crystal silicon.
摘要翻译：公开了一种finFET沟槽电路。 FinFET通过在沟槽导体的一部分上采用沟槽顶部氧化物与沟槽电容器集成。然后将通过栅极设置在沟槽顶部氧化物上方以形成更大的电路，例如DRAM阵列。通过利用多晶硅和单晶硅之间的不同生长速率形成沟槽顶部氧化物。

64. 发明授权

US08803233B2 Junctionless transistor 有权
标题翻译：无结晶体晶体管
公开(公告)号：US08803233B2
公开(公告)日：2014-08-12
申请号：US13242861
申请日：2011-09-23
申请人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Pranita Kulkarni , Tak H. Ning
发明人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Pranita Kulkarni , Tak H. Ning
IPC分类号： H01L29/778
CPC分类号： H01L21/823807 , H01L27/0922 , H01L27/1203 , H01L29/78654 , H01L29/78696
摘要： A transistor includes a semiconductor layer, and a gate dielectric is formed on the semiconductor layer. A gate conductor is formed on the gate dielectric and an active area is located in the semiconductor layer underneath the gate dielectric. The active area includes a graded dopant region that has a higher doping concentration near a top surface of the semiconductor layer and a lower doping concentration near a bottom surface of the semiconductor layer. This graded dopant region has a gradual decrease in the doping concentration. The transistor also includes source and drain regions that are adjacent to the active region. The source and drain regions and the active area have the same conductivity type.
摘要翻译：晶体管包括半导体层，并且在半导体层上形成栅极电介质。栅极导体形成在栅极电介质上，并且有源区位于栅极电介质下方的半导体层中。有源区包括在半导体层的顶表面附近具有较高掺杂浓度的渐变掺杂区和在半导体层的底表面附近的较低的掺杂浓度。该渐变掺杂剂区域的掺杂浓度逐渐降低。晶体管还包括与有源区相邻的源区和漏区。源极和漏极区域和有源区域具有相同的导电类型。

65. 发明授权

US08772874B2 MOSFET including asymmetric source and drain regions 失效
标题翻译： MOSFET包括不对称的源极和漏极区域
公开(公告)号：US08772874B2
公开(公告)日：2014-07-08
申请号：US13216554
申请日：2011-08-24
申请人： Kangguo Cheng , Balasubramanian S. Haran , Shom Ponoth , Theodorus E. Standaert , Tenko Yamashita
发明人： Kangguo Cheng , Balasubramanian S. Haran , Shom Ponoth , Theodorus E. Standaert , Tenko Yamashita
IPC分类号： H01L27/01 , H01L27/12 , H01L31/0392
CPC分类号： H01L29/66477 , H01L21/26506 , H01L21/26513 , H01L21/26586 , H01L21/823418 , H01L21/84 , H01L29/66045 , H01L29/6656 , H01L29/66628 , H01L29/66659 , H01L29/66803 , H01L29/785
摘要： At least one drain-side surfaces of a field effect transistor (FET) structure, which can be a structure for a planar FET or a fin FET, is structurally damaged by an angled ion implantation of inert or electrically active dopants, while at least one source-side surface of the transistor is protected from implantation by a gate stack and a gate spacer. Epitaxial growth of a semiconductor material is retarded on the at least one structurally damaged drain-side surface, while epitaxial growth proceeds without retardation on the at least one source-side surface. A raised epitaxial source region has a greater thickness than a raised epitaxial drain region, thereby providing an asymmetric FET having lesser source-side external resistance than drain-side external resistance, and having lesser drain-side overlap capacitance than source-side overlap capacitance.
摘要翻译：作为平面FET或鳍式FET的结构的场效应晶体管（FET）结构的至少一个漏极侧表面在结构上被惰性或电活性掺杂剂的成角度的离子注入损坏，而至少一个保护晶体管的源极侧表面不被栅极堆叠和栅极间隔物的注入。半导体材料的外延生长在至少一个结构损坏的漏极侧表面上延迟，而外延生长在至少一个源极侧表面上没有延迟。凸起的外延源区域具有比凸起的外延漏极区域更大的厚度，从而提供具有比漏极侧外部电阻更小的源极侧外部电阻并且具有比源极重叠电容更少的漏极侧重叠电容的非对称FET。

66. 发明授权

US08754527B2 Self aligned borderless contact 有权
标题翻译：自对准无边界接触
公开(公告)号：US08754527B2
公开(公告)日：2014-06-17
申请号：US13562341
申请日：2012-07-31
申请人： Kangguo Cheng , Rahhavasimhan Sreenivasan
发明人： Kangguo Cheng , Rahhavasimhan Sreenivasan
IPC分类号： H01L23/48 , H01L21/20 , B44C1/22
CPC分类号： H01L21/76834 , H01L21/28518 , H01L21/76823 , H01L21/76843 , H01L21/76855 , H01L21/76897 , H01L2924/0002 , H01L2924/00
摘要： A method of fabricating a semiconductor structure having a borderless contact, the method including providing a first semiconductor device adjacent to a second semiconductor device, the first and second semiconductor devices being formed on a semiconductor substrate, depositing a non-conductive liner on top of the semiconductor substrate and the first and second semiconductor devices, depositing a contact level dielectric layer on top of the non-conductive liner, etching a contact hole in the contact-level dielectric between the first semiconductor device and the second semiconductor device, and selective to the non-conductive liner, converting a portion of the non-conductive liner exposed in the contact hole into a conductive liner; and forming a metal contact in the contact hole.
摘要翻译：一种制造具有无边界接触的半导体结构的方法，所述方法包括提供与第二半导体器件相邻的第一半导体器件，所述第一和第二半导体器件形成在半导体衬底上，在非导电衬底的顶部上沉积非导电衬垫半导体衬底和第一和第二半导体器件，在非导电衬垫的顶部上沉积接触电介质层，蚀刻第一半导体器件和第二半导体器件之间的接触电平电介质中的接触孔，并且对将非接触孔中暴露的非导电衬垫的一部分转换成导电衬垫; 并在接触孔中形成金属接触。

67. 发明授权

US08741701B2 Fin structure formation including partial spacer removal 有权
标题翻译：翅片结构形成包括部分间隔物去除
公开(公告)号：US08741701B2
公开(公告)日：2014-06-03
申请号：US13585395
申请日：2012-08-14
申请人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Chun-Chen Yeh
发明人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Chun-Chen Yeh
IPC分类号： H01L21/335 , H01L21/8232
CPC分类号： H01L21/32139 , H01L21/0337 , H01L21/3086 , H01L21/31144 , H01L29/66795
摘要： A method of forming a semiconductor device includes forming a mandrel on top of a substrate; forming a first spacer adjacent to the mandrel on top of the substrate; forming a cut mask over the first spacer and the mandrel, such that the first spacer is partially exposed by the cut mask; partially removing the partially exposed first spacer; and etching the substrate to form a fin structure corresponding to the partially removed first spacer in the substrate.
摘要翻译：形成半导体器件的方法包括：在基底的顶部上形成心轴; 在所述基板的顶部上形成邻近所述心轴的第一间隔件; 在第一间隔件和心轴上形成切割掩模，使得第一间隔件被切割掩模部分地暴露; 部分地去除部分暴露的第一间隔件; 并且蚀刻所述衬底以形成对应于所述衬底中部分移除的第一间隔物的翅片结构。

68. 发明授权

US08691697B2 Self-aligned devices and methods of manufacture 失效
标题翻译：自对准装置和制造方法
公开(公告)号：US08691697B2
公开(公告)日：2014-04-08
申请号：US12943956
申请日：2010-11-11
申请人： Roger A. Booth, Jr. , Kangguo Cheng , Joseph Ervin , Chengwen Pei , Ravi M. Todi , Geng Wang
发明人： Roger A. Booth, Jr. , Kangguo Cheng , Joseph Ervin , Chengwen Pei , Ravi M. Todi , Geng Wang
IPC分类号： H01L21/302 , B44C1/22
CPC分类号： H01L21/31056 , H01L21/0337 , H01L21/0338 , H01L21/32139
摘要： A method includes forming patterned lines on a substrate having a predetermined pitch. The method further includes forming spacer sidewalls on sidewalls of the patterned lines. The method further includes forming material in a space between the spacer sidewalls of adjacent patterned lines. The method further includes forming another patterned line from the material by protecting the material in the space between the spacer sidewalls of adjacent patterned lines while removing the spacer sidewalls. The method further includes transferring a pattern of the patterned lines and the another patterned line to the substrate.
摘要翻译：一种方法包括在具有预定间距的基底上形成图案线。该方法还包括在图案化线的侧壁上形成间隔壁。该方法还包括在相邻图案线的间隔壁侧壁之间的空间中形成材料。该方法还包括通过在相邻图案化线的间隔壁侧壁之间的空间中保护材料同时去除间隔壁侧壁而从该材料形成另一图案化线。该方法还包括将图案化线和另一图案化线的图案转移到衬底。

69. 发明申请

US20140070357A1 SOI DEVICE WITH EMBEDDED LINER IN BOX LAYER TO LIMIT STI RECESS 有权
标题翻译：具有嵌入式衬垫的SOI器件限制STI感染
公开(公告)号：US20140070357A1
公开(公告)日：2014-03-13
申请号：US13611182
申请日：2012-09-12
申请人： Kangguo Cheng , Balasubramanian S. Haran , Shom Ponoth
发明人： Kangguo Cheng , Balasubramanian S. Haran , Shom Ponoth
IPC分类号： H01L29/06 , H01L21/762
CPC分类号： H01L27/1203 , H01L21/31144 , H01L21/76283 , H01L21/84 , H01L29/06 , H01L29/66772 , H01L29/78654
摘要： A semiconductor substrate having an isolation region and method of forming the same. The method includes the steps of providing a substrate having a substrate layer, a buried oxide (BOX), a silicon on insulator (SOI) layer, a pad oxide layer, and a pad nitride layer, forming a shallow trench region, etching the pad oxide layer to form ears and etching the BOX layer to form undercuts, depositing a liner on the shallow trench region, depositing a soft mask over the surface of the shallow trench region, filling the shallow trench region, etching the soft mask so that it is recessed to the top of the BOX layer, etching the liner off certain regions, removing the soft mask, and filling and polishing the shallow trench region. The liner prevents shorting of the semiconductor device when the contacts are misaligned.
摘要翻译：具有隔离区域的半导体基板及其形成方法。该方法包括以下步骤：提供具有衬底层，掩埋氧化物（BOX），绝缘体上硅（SOI）层，衬垫氧化物层和衬垫氮化物层的衬底，形成浅沟槽区，蚀刻衬垫氧化层以形成耳朵并蚀刻BOX层以形成底切，在浅沟槽区域上沉积衬垫，在浅沟槽区域的表面上沉积软掩模，填充浅沟槽区域，蚀刻软掩模，使得它凹陷到BOX层的顶部，在某些区域蚀刻衬垫，去除软掩模，以及填充和抛光浅沟槽区域。当触点不对准时，衬垫防止半导体器件的短路。

70. 发明申请

US20140048804A1 FIN STRUCTURE FORMATION INCLUDING PARTIAL SPACER REMOVAL 审中-公开
公开(公告)号：US20140048804A1
公开(公告)日：2014-02-20
申请号：US13589427
申请日：2012-08-20
申请人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Chun-Chen Yeh
发明人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Chun-Chen Yeh
IPC分类号： H01L29/04
CPC分类号： H01L21/32139 , H01L21/0337 , H01L21/3086 , H01L21/31144 , H01L29/66795
摘要： A method of forming a semiconductor device includes forming a mandrel on top of a substrate; forming a first spacer adjacent to the mandrel on top of the substrate; forming a cut mask over the first spacer and the mandrel, such that the first spacer is partially exposed by the cut mask; partially removing the partially exposed first spacer; and etching the substrate to form a fin structure corresponding to the partially removed first spacer in the substrate.

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