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61. 发明授权

US06764906B2 Method for making trench mosfet having implanted drain-drift region 有权
标题翻译：制造具有注入漏极漂移区域的沟槽MOSFET的方法
公开(公告)号：US06764906B2
公开(公告)日：2004-07-20
申请号：US10317568
申请日：2002-12-12
申请人： Mohamed N. Darwish
发明人： Mohamed N. Darwish
IPC分类号： H02L21336
CPC分类号： H01L29/7813 , H01L21/2253 , H01L29/0634 , H01L29/0847 , H01L29/0878 , H01L29/1095 , H01L29/7811 , H01L2924/0002 , H01L2924/00
摘要： A trench MOSFET is formed in a structure which includes a P-type epitaxial layer overlying an N+ substrate. A trench is formed in the epitaxial layer. A deep implanted N layer is formed below the trench at the interface between the substrate and the epitaxial layer, and N-type dopant is implant through the bottom of the trench to form an N region in the epitaxial layer below the trench but above and separated from the deep N layer. The structure is heated to cause the N layer to diffuse upward and the N region to diffuse downward. The diffusions merge to form a continuous N-type drain-drift region extending from the bottom of the trench to the substrate. Alternatively, the drain-drift region may be formed by implanting N-type dopant through the bottom of the trench at different energies, creating a stack of N-type regions that extend from the bottom of the trench to the substrate.
摘要翻译：在包括覆盖在N +衬底上的P型外延层的结构中形成沟槽MOSFET。在外延层中形成沟槽。在衬底和外延层之间的界面处在沟槽下方形成深深注入的N层，并且N型掺杂剂通过沟槽的底部注入，以在沟槽下方的外延层中形成N区，但在上方并分离从深N层。加热结构使N层向上扩散，N区向下扩散。扩散合并形成从沟槽的底部延伸到衬底的连续的N型漏 - 漂移区。或者，可以通过在不同能量下通过沟槽的底部注入N型掺杂剂形成漏极 - 漂移区域，从而形成从沟槽的底部延伸到衬底的N型区域堆叠。

62. 发明授权

US06603188B1 Polysilicon-edge, low-power, high-frequency bipolar transistor and method of forming the transistor 有权
公开(公告)号：US06603188B1
公开(公告)日：2003-08-05
申请号：US10207628
申请日：2002-07-29
申请人： Mohamed N. Darwish , Alexei Sadovnikov , Reda Razouk
发明人： Mohamed N. Darwish , Alexei Sadovnikov , Reda Razouk
IPC分类号： H01L27082
CPC分类号： H01L29/66287 , H01L29/732
摘要： A low-power high-frequency bipolar transistor is formed to have a small self-aligned base region that reduces the base-to-collector capacitance, and small self-aligned base and emitter contacts that reduce the base-to-emitter capacitance and the base resistance. The base and emitter contacts are formed to have sub-lithographic feature sizes.

63. 发明授权

US08546878B2 Semiconductor device incorporating charge balancing 有权
标题翻译：并入电荷平衡的半导体器件
公开(公告)号：US08546878B2
公开(公告)日：2013-10-01
申请号：US13156848
申请日：2011-06-09
申请人： Mohamed N. Darwish
发明人： Mohamed N. Darwish
IPC分类号： H01L29/66
CPC分类号： H01L29/7802 , H01L21/02164 , H01L21/0217 , H01L21/02321 , H01L21/2003 , H01L21/265 , H01L21/2658 , H01L21/26586 , H01L21/28008 , H01L21/30604 , H01L21/324 , H01L21/76224 , H01L21/823885 , H01L29/0619 , H01L29/0634 , H01L29/0649 , H01L29/0653 , H01L29/0661 , H01L29/0692 , H01L29/0696 , H01L29/0847 , H01L29/0878 , H01L29/1095 , H01L29/408 , H01L29/4236 , H01L29/42368 , H01L29/66537 , H01L29/66666 , H01L29/66734 , H01L29/7809 , H01L29/7811 , H01L29/7813 , H01L29/7827 , H01L29/7835
摘要： A semiconductor device includes a semiconductor layer of a first conductivity type and a semiconductor layer of a second conductivity type formed thereon. The semiconductor layer of the second conductivity type is characterized by a first thickness. The semiconductor device includes a set of trenches having a predetermined depth and extending into the semiconductor layer of the second conductivity type, thereby defining interfacial regions disposed between the semiconductor layer of the second conductivity type and each of the trenches. The trenches comprises a distal portion consisting essentially of a dielectric material disposed therein and a proximal portion comprising the dielectric material and a gate material disposed interior to the dielectric material in the proximal portion of the trench. The semiconductor device further includes a source region coupled to the semiconductor layer of the second conductivity type.
摘要翻译：半导体器件包括形成在其上的第一导电类型的半导体层和第二导电类型的半导体层。第二导电类型的半导体层的特征在于第一厚度。半导体器件包括具有预定深度并延伸到第二导电类型的半导体层的一组沟槽，从而限定设置在第二导电类型的半导体层与每个沟槽之间的界面区域。沟槽包括基本上由布置在其中的介电材料组成的远端部分和包括电介质材料的近端部分和设置在沟槽的近端部分中的电介质材料内部的栅极材料。该半导体器件还包括耦合到第二导电类型的半导体层的源极区域。

64. 发明授权

US08330186B2 Lateral devices containing permanent charge 有权
标题翻译：包含永久充电的侧向装置
公开(公告)号：US08330186B2
公开(公告)日：2012-12-11
申请号：US12432917
申请日：2009-04-30
申请人： Mohamed N. Darwish , Amit Paul
发明人： Mohamed N. Darwish , Amit Paul
IPC分类号： H01L29/66
CPC分类号： H01L29/408 , H01L29/0634 , H01L29/0873 , H01L29/0886 , H01L29/42368 , H01L29/7816 , H01L29/7825 , H01L29/7835
摘要： A lateral device includes a gate region connected to a drain region by a drift layer. An insulation region adjoins the drift layer between the gate region and the drain region. Permanent charges are embedded in the insulation region, sufficient to cause inversion in the insulation region.
摘要翻译：横向器件包括通过漂移层连接到漏极区的栅极区域。绝缘区域与栅极区域和漏极区域之间的漂移层相邻。永久电荷嵌入在绝缘区域中，足以在绝缘区域引起反转。

65. 发明申请

US20110220998A1 Devices Containing Permanent Charge 有权
标题翻译：包含永久充电的设备
公开(公告)号：US20110220998A1
公开(公告)日：2011-09-15
申请号：US13114224
申请日：2011-05-24
申请人： Mohamed N. Darwish , Amit Paul
发明人： Mohamed N. Darwish , Amit Paul
IPC分类号： H01L29/78
CPC分类号： H01L29/7811 , H01L21/2256 , H01L21/2257 , H01L21/26506 , H01L21/26513 , H01L21/2658 , H01L21/26586 , H01L29/0615 , H01L29/0619 , H01L29/0638 , H01L29/0653 , H01L29/1095 , H01L29/402 , H01L29/408 , H01L29/41741 , H01L29/42368 , H01L29/66734 , H01L29/7813 , H01L29/7827
摘要： An edge termination structure includes a final dielectric trench containing permanent charge. The final dielectric trench is surrounded by first conductivity type semiconductor material (doped by lateral outdiffusion from the trenches), which in turn is laterally surrounded by second conductivity type semiconductor material.
摘要翻译：边缘终端结构包括包含永久电荷的最终介电沟槽。最终的电介质沟槽由第一导电类型的半导体材料（从沟槽的侧向外扩散掺杂）围绕，其又由第二导电型半导体材料横向包围。

66. 发明授权

US07435650B2 Process for manufacturing trench MIS device having implanted drain-drift region and thick bottom oxide 有权
标题翻译：用于制造具有注入漏极漂移区域和厚底部氧化物的沟槽MIS器件的工艺
公开(公告)号：US07435650B2
公开(公告)日：2008-10-14
申请号：US10872931
申请日：2004-06-21
申请人： Mohamed N. Darwish , Kyle W. Terrill , Jainhai Qi
发明人： Mohamed N. Darwish , Kyle W. Terrill , Jainhai Qi
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L21/2253 , H01L21/28185 , H01L21/28194 , H01L21/28211 , H01L21/823487 , H01L29/0634 , H01L29/0847 , H01L29/086 , H01L29/0878 , H01L29/1095 , H01L29/42368
摘要： A trench MIS device is formed in a P-epitaxial layer that overlies an N-epitaxial layer and an N+ substrate. In one embodiment, the device includes a thick oxide layer at the bottom of the trench and an N-type drain-drift region that extends from the bottom of the trench to the N-epitaxial layer. The thick insulating layer reduces the capacitance between the gate and the drain and therefore improves the ability of the device to operate at high frequencies. Preferably, the drain-drift region is formed at least in part by fabricating spacers on the sidewalls of the trench and implanting an N-type dopant between the sidewall spacers and through the bottom of the trench. The thick bottom oxide layer is formed on the bottom of the trench while the sidewall spacers are still in place. The drain-drift region can be doped more heavily than the conventional “drift region” that is formed in an N-epitaxial layer. Thus, the device has a low on-resistance. The N-epitaxial layer increases the breakdown voltage of the MIS device. In alternative embodiments, the thick bottom oxide layer can be omitted.
摘要翻译：沟槽MIS器件形成在覆盖在N外延层和N +衬底上的P外延层中。在一个实施例中，器件包括在沟槽底部的厚氧化物层和从沟槽的底部延伸到N外延层的N型漏 - 漂移区。厚的绝缘层减小了栅极和漏极之间的电容，从而提高了器件在高频下工作的能力。优选地，漏极漂移区域至少部分地通过在沟槽的侧壁上制造间隔物并且在侧壁间隔物之间并通过沟槽的底部注入N型掺杂剂而形成。厚的底部氧化物层形成在沟槽的底部，同时侧壁间隔物仍然在位。漏极漂移区可以比在N外延层中形成的常规“漂移区”更重的掺杂。因此，器件具有低导通电阻。 N外延层增加了MIS器件的击穿电压。在替代实施例中，可以省略厚的底部氧化物层。

67. 发明申请

US20080073707A1 Power MOSFET with recessed field plate 有权
标题翻译：功率MOSFET具有凹陷的场板
公开(公告)号：US20080073707A1
公开(公告)日：2008-03-27
申请号：US11903972
申请日：2007-09-25
申请人： Mohamed N. Darwish
发明人： Mohamed N. Darwish
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7813 , H01L21/26586 , H01L29/0696 , H01L29/1095 , H01L29/407 , H01L29/41766 , H01L29/42368 , H01L29/66734 , H01L29/7808 , H01L29/7809
摘要： A trench MOSFET contains a recessed field plate (RFP) trench adjacent the gate trench. The RFP trench contains an RFP electrode insulated from the die by a dielectric layer along the walls of the RFP trench. The gate trench has a thick bottom oxide layer, and the gate and RFP trenches are preferably formed in the same processing step and are of substantially the same depth. When the MOSFET operates in the third quadrant (with the source/body-to-drain junction forward-biased), the combined effect of the RFP and gate electrodes significantly reduces in the minority carrier diffusion current and reverse-recovery charge. The RFP electrode also functions as a recessed field plates to reduce the electric field in the channel regions when the MOSFET source/body to-drain junction reverse-biased.
摘要翻译：沟槽MOSFET包含与栅极沟槽相邻的凹陷场板（RFP）沟槽。 RFP沟槽包含沿着RFP沟槽的壁通过电介质层与裸片绝缘的RFP电极。栅极沟槽具有厚的底部氧化物层，并且栅极和RFP沟槽优选地在相同的处理步骤中形成并且具有基本上相同的深度。当MOSFET在第三象限（源极/体对漏极结正向偏置）中工作时，RFP和栅电极的组合效应在少数载流子扩散电流和反向恢复电荷中显着降低。当MOSFET源极/体对漏极结反向偏置时，RFP电极还用作凹陷场板，以减小沟道区域中的电场。

68. 发明授权

US07118953B2 Process of fabricating termination region for trench MIS device 有权
标题翻译：制造沟槽MIS器件端接区的工艺
公开(公告)号：US07118953B2
公开(公告)日：2006-10-10
申请号：US11141942
申请日：2005-06-01
申请人： Mohamed N. Darwish
发明人： Mohamed N. Darwish
IPC分类号： H01L21/8238 , H01L21/336
CPC分类号： H01L29/7813 , H01L29/0847 , H01L29/0878 , H01L29/0886 , H01L29/1095 , H01L29/407 , H01L29/41741 , H01L29/42368 , H01L29/7811
摘要： A trench MIS device is formed in a semiconductor die that contains a P-epitaxial layer that overlies an N+ substrate and an N-epitaxial layer. In one embodiment, the device includes a drain-drift region that extends from the bottom of the trench to the N-epitaxial layer. A termination region of the die includes a half-trench at an edge of the die and an N-type region that extends from a bottom of the half-trench to the substrate. An insulating layer and an overlying metal layer extend from the surface of the epitaxial layer into the half-trench. Preferably, the elements of the termination region are formed during the same process steps that are used to form the active elements of the device.
摘要翻译：沟槽MIS器件形成在包含覆盖在N +衬底和N外延层上的P外延层的半导体管芯中。在一个实施例中，器件包括从沟槽的底部延伸到N外延层的漏 - 漂移区。芯片的端接区域包括在管芯的边缘处的半沟槽和从半沟槽的底部延伸到衬底的N型区域。绝缘层和上覆金属层从外延层的表面延伸到半沟槽中。优选地，端接区域的元件在用于形成器件的有源元件的相同工艺步骤中形成。

69. 发明授权

US06903412B2 Trench MIS device with graduated gate oxide layer 有权
标题翻译：带渐变栅氧化层的沟槽MIS器件
公开(公告)号：US06903412B2
公开(公告)日：2005-06-07
申请号：US10106812
申请日：2002-03-26
申请人： Mohamed N. Darwish , Christiana Yue , Frederick P. Giles , Kam Hong Lui , Kuo-In Chen , Kyle Terrill , Deva N. Pattanayak
发明人： Mohamed N. Darwish , Christiana Yue , Frederick P. Giles , Kam Hong Lui , Kuo-In Chen , Kyle Terrill , Deva N. Pattanayak
IPC分类号： H01L21/28 , H01L21/336 , H01L29/06 , H01L29/08 , H01L29/423 , H01L29/49 , H01L29/51 , H01L29/78 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/7813 , H01L21/28185 , H01L21/28194 , H01L21/28211 , H01L21/28238 , H01L29/0634 , H01L29/0847 , H01L29/0878 , H01L29/42368 , H01L29/4983 , H01L29/512 , H01L29/518 , H01L29/66621 , H01L29/7834
摘要： The gate oxide layer of a trench MIS device includes a graduated transition region, where the thickness of the gate oxide layer decreases gradually from a thick section adjacent the bottom of the trench to a thin section adjacent the sidewall of the trench. The PN junction between the body and drain regions intersects the trench in the transition region. This structure allows for a greater margin of error in the placement of the PN junction during the manufacture of the device, since the intersection between the PN junction can be located anywhere in the transition region. The MIS device also has improved breakdown characteristics.
摘要翻译：沟槽MIS器件的栅极氧化层包括刻蚀过渡区域，其中栅极氧化物层的厚度从邻近沟槽底部的厚部分逐渐减小到邻近沟槽侧壁的薄部分。体区和漏区之间的PN结与过渡区中的沟槽相交。这种结构允许在器件制造期间在PN结的放置方面具有更大的误差余量，因为PN结的交点可位于过渡区域的任何地方。 MIS器件还具有改善的击穿特性。

70. 发明授权

US06600193B2 Trench MOSFET having implanted drain-drift region 有权
标题翻译：具有注入漏极漂移区的沟槽MOSFET
公开(公告)号：US06600193B2
公开(公告)日：2003-07-29
申请号：US10211438
申请日：2002-08-02
申请人： Mohamed N. Darwish
发明人： Mohamed N. Darwish
IPC分类号： H01L2976
CPC分类号： H01L29/7813 , H01L21/2253 , H01L29/0634 , H01L29/0847 , H01L29/0878 , H01L29/1095 , H01L29/7811
摘要： A trench MOSFET is formed in a structure which includes a P-type epitaxial layer overlying an N+ substrate. An N-type dopant is implanted through the bottom of the trench into the P-epitaxial layer to form a buried layer below the trench, and after a up-diffusion step a N drain-drift region extends between the N+ substrate and the bottom of the trench. The result is a more controllable doping profile of the N-type dopant below the trench. The body region may also be formed by implanting P-type dopant into the epitaxial layer, in which case the background doping of the epitaxial layer may be either lightly doped P- or N-type. A MOSFET constructed in accordance with this invention can have a reduced threshold voltage and on-resistance and an increased punchthrough breakdown voltage.
摘要翻译：在包括覆盖在N +衬底上的P型外延层的结构中形成沟槽MOSFET。通过沟槽的底部将N型掺杂剂注入到P外延层中以在沟槽下方形成掩埋层，并且在上扩散步骤之后，N漏极漂移区在N +衬底和底层之间延伸沟渠。结果是沟槽下方的N型掺杂剂的更可控的掺杂分布。体区也可以通过将P型掺杂剂注入到外延层中而形成，在这种情况下，外延层的背景掺杂可以是轻掺杂的P型或N型。根据本发明构造的MOSFET可以具有降低的阈值电压和导通电阻以及增加的穿通击穿电压。

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