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61. 发明授权

US06806551B2 Fuse construction for integrated circuit structure having low dielectric constant dielectric material 有权
标题翻译：具有低介电常数介电材料的集成电路结构的保险丝结构
公开(公告)号：US06806551B2
公开(公告)日：2004-10-19
申请号：US10376401
申请日：2003-02-28
申请人： Yauh-Ching Liu , Ruggero Castagnetti , Ramnath Venkatraman
发明人： Yauh-Ching Liu , Ruggero Castagnetti , Ramnath Venkatraman
IPC分类号： H01L2900
CPC分类号： H01L23/5258 , H01L23/5329 , H01L2224/05022 , H01L2924/01019
摘要： Fuses, and optionally metal pads, are formed over a layer of low k dielectric material structure having first openings lined with conductive barrier material and filled to form metal interconnects in the upper surface of the low k dielectric material. A dielectric layer is formed over the low k dielectric material and over the metal interconnects, and patterned to form second openings therein communicating with the metal interconnects. A conductive barrier layer is formed over this dielectric layer in contact with the metal interconnects, and patterned to form fuse portions between some of the metal interconnects, and a liner over one or more of the metal interconnects. A dielectric layer is then formed over the patterned conductive barrier layer to form a window above each fuse, and patterned to form openings over at least some of the conductive barrier liners filled with metal to form metal pads.
摘要翻译：保险丝和可选的金属焊盘形成在低k电介质材料结构的层上，其具有衬有导电阻挡材料的第一开口并且被填充以在低k电介质材料的上表面中形成金属互连。电介质层形成在低k电介质材料上方和金属互连之上，并被图案化以形成其中与金属互连连通的第二开口。导电阻挡层形成在与金属互连件接触的该电介质层上，并被图案化以在一些金属互连件之间形成熔丝部分，以及在一个或多个金属互连件上的衬垫。然后在图案化的导电阻挡层上方形成电介质层，以形成每个保险丝上方的窗口，并且图案化以在填充有金属的至少一些导电阻挡衬里上形成开口以形成金属焊盘。

62. 发明授权

US06566171B1 Fuse construction for integrated circuit structure having low dielectric constant dielectric material 有权
标题翻译：具有低介电常数介电材料的集成电路结构的保险丝结构
公开(公告)号：US06566171B1
公开(公告)日：2003-05-20
申请号：US09882404
申请日：2001-06-12
申请人： Yauh-Ching Liu , Ruggero Castagnetti , Ramnath Venkatraman
发明人： Yauh-Ching Liu , Ruggero Castagnetti , Ramnath Venkatraman
IPC分类号： H01L2182
CPC分类号： H01L23/5258 , H01L23/5329 , H01L2224/05022 , H01L2924/01019
摘要： Fuses, and optionally metal pads, are formed over a layer of low k dielectric material structure having first openings lined with conductive barrier material and filled to form metal interconnects in the upper surface of the low k dielectric material. A dielectric layer is formed over the low k dielectric material and over the metal interconnects, and patterned to form second openings therein communicating with the metal interconnects. A conductive barrier layer is formed over this dielectric layer in contact with the metal interconnects, and patterned to form fuse portions between some of the metal interconnects, and a liner over one or more of the metal interconnects. A dielectric layer is then formed over the patterned conductive barrier layer to form a window above each fuse, and patterned to form openings over at least some of the conductive barrier liners filled with metal to form metal pads.
摘要翻译：保险丝和可选的金属焊盘形成在低k电介质材料结构的层上，其具有衬有导电阻挡材料的第一开口并且被填充以在低k电介质材料的上表面中形成金属互连。电介质层形成在低k电介质材料上方和金属互连之上，并被图案化以形成其中与金属互连连通的第二开口。导电阻挡层形成在与金属互连件接触的该电介质层上，并被图案化以在一些金属互连件之间形成熔丝部分，以及在一个或多个金属互连件上的衬垫。然后在图案化的导电阻挡层上方形成电介质层，以形成每个保险丝上方的窗口，并且图案化以在填充有金属的至少一些导电阻挡衬里上形成开口以形成金属焊盘。

63. 发明授权

US06369418B1 Formation of a novel DRAM cell 失效
标题翻译：形成新型DRAM单元
公开(公告)号：US06369418B1
公开(公告)日：2002-04-09
申请号：US09112687
申请日：1998-07-09
申请人： Dung-Ching Perng , Yauh-Ching Liu
发明人： Dung-Ching Perng , Yauh-Ching Liu
IPC分类号： H01L27108
CPC分类号： H01L21/76237 , H01L27/10861 , H01L27/1087 , H01L28/55 , H01L29/66181
摘要： A DRAM cell capacitor is described. Capacitor formation and cell isolation methods are integrated by using support sidewalls to form vertical DRAM capacitors. Doped polysilicon adjacent to the vertical sidewalls of the support provides one DRAM cell capacitor plate. The DRAM capacitor also contains a dielectric material that contacts and partially covers the doped polysilicon capacitor plate. Doped epitaxial silicon that contacts a portion of the dielectric forms the second capacitor plate and completes the DRAM capacitor.
摘要翻译：描述DRAM单元电容器。通过使用支撑侧壁形成垂直DRAM电容器来集成电容器形成和电池隔离方法。与支撑体的垂直侧壁相邻的掺杂多晶硅提供一个DRAM单元电容器板。 DRAM电容器还包含接触并部分覆盖掺杂多晶硅电容器板的电介质材料。与电介质的一部分接触的掺杂的外延硅形成第二电容器板并完成DRAM电容器。

64. 发明授权

US5688700A Method of forming a field effect transistor 失效
标题翻译：形成场效应晶体管的方法
公开(公告)号：US5688700A
公开(公告)日：1997-11-18
申请号：US552855
申请日：1995-11-03
申请人： David Kao , Yauh-Ching Liu
发明人： David Kao , Yauh-Ching Liu
IPC分类号： H01L21/336 , H01L29/10 , H01L29/78 , H01L21/265
CPC分类号： H01L29/66583 , H01L29/1033 , H01L29/66553 , H01L29/7833 , H01L29/66537
摘要： A semiconductor processing method of forming a field effect transistor includes, a) providing a first layer of material over a substrate; b) providing a first opening through the first layer, the first opening having a width and a base; c) providing a second layer of material over the first layer and to within the first opening to a thickness which is less than one half the first opening width to less than completely fill the first opening and define a narrower second opening; d) anisotropically etching the second layer of material from outwardly of the first layer and from the first opening base to effectively provide inner sidewall spacers within the first opening; e) providing a gate dielectric layer within the second opening; f) providing a layer of electrically conductive gate material over the first layer and to within the second opening over the gate dielectric layer to fill the second opening with conductive gate material; g) without masking, planarize etching the conductive gate material layer substantially selective relative to the first layer to define a transistor gate within the second opening; and h) providing opposing source and drain regions relative to the transistor gate.
摘要翻译：形成场效应晶体管的半导体处理方法包括：a）在衬底上提供第一层材料; b）提供穿过第一层的第一开口，第一开口具有宽度和底部; c）在所述第一层之上提供第二层材料，并且在所述第一开口内提供厚度小于所述第一开口宽度的一半，以小于完全填充所述第一开口并限定较窄的第二开口; d）从所述第一层的外部和所述第一开口底部各向异性地蚀刻所述第二层材料，以有效地在所述第一开口内提供内部侧壁间隔物; e）在所述第二开口内提供栅极电介质层; f）在所述第一层上提供导电栅极材料层，并且在所述栅极介电层上方的所述第二开口内提供导电栅极材料层，以用导电栅极材料填充所述第二开口; g）没有掩蔽，平坦化蚀刻相对于第一层基本上选择性的导电栅极材料层，以在第二开口内限定晶体管栅极; 以及h）相对于所述晶体管栅极提供相对的源极和漏极区域。

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