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1. 发明授权

US5933738A Method of forming a field effect transistor 失效
标题翻译：形成场效应晶体管的方法
公开(公告)号：US5933738A
公开(公告)日：1999-08-03
申请号：US964779
申请日：1997-11-05
申请人： David Kao , Yauh-Ching Liu
发明人： David Kao , Yauh-Ching Liu
IPC分类号： H01L21/336 , H01L29/10 , H01L29/78 , H01L21/339
CPC分类号： H01L29/66583 , H01L29/1033 , H01L29/66553 , H01L29/7833 , H01L29/66537
摘要： A semiconductor processing method of forming a field effect transistor includes, a) providing a first layer of material over a substrate; b) providing a first opening through the first layer, the first opening having a width and a base; c) providing a second layer of material over the first layer and to within the first opening to a thickness which is less than one half the first opening width to less than completely fill the first opening and define a narrower second opening; d) anisotropically etching the second layer of material from outwardly of the first layer and from the first opening base to effectively provide inner sidewall spacers within the first opening; e) providing a gate dielectric layer within the second opening; f) providing a layer of electrically conductive gate material over the first layer and to within the second opening over the gate dielectric layer to fill the second opening with conductive gate material; g) without masking, planarize etching the conductive gate material layer substantially selective relative to the first layer to define a transistor gate within the second opening; and h) providing opposing source and drain regions relative to the transistor gate.
摘要翻译：形成场效应晶体管的半导体处理方法包括：a）在衬底上提供第一层材料; b）提供穿过第一层的第一开口，第一开口具有宽度和底部; c）在所述第一层之上提供第二层材料，并且在所述第一开口内提供厚度小于所述第一开口宽度的一半，以小于完全填充所述第一开口并限定较窄的第二开口; d）从所述第一层的外部和所述第一开口底部各向异性地蚀刻所述第二层材料，以有效地在所述第一开口内提供内部侧壁间隔物; e）在所述第二开口内提供栅极电介质层; f）在所述第一层上提供导电栅极材料层，并且在所述栅极介电层上方的所述第二开口内提供导电栅极材料层，以用导电栅极材料填充所述第二开口; g）没有掩蔽，平坦化蚀刻相对于第一层基本上选择性的导电栅极材料层，以在第二开口内限定晶体管栅极; 以及h）相对于所述晶体管栅极提供相对的源极和漏极区域。

2. 发明授权

US5688700A Method of forming a field effect transistor 失效
标题翻译：形成场效应晶体管的方法
公开(公告)号：US5688700A
公开(公告)日：1997-11-18
申请号：US552855
申请日：1995-11-03
申请人： David Kao , Yauh-Ching Liu
发明人： David Kao , Yauh-Ching Liu
IPC分类号： H01L21/336 , H01L29/10 , H01L29/78 , H01L21/265
CPC分类号： H01L29/66583 , H01L29/1033 , H01L29/66553 , H01L29/7833 , H01L29/66537
摘要： A semiconductor processing method of forming a field effect transistor includes, a) providing a first layer of material over a substrate; b) providing a first opening through the first layer, the first opening having a width and a base; c) providing a second layer of material over the first layer and to within the first opening to a thickness which is less than one half the first opening width to less than completely fill the first opening and define a narrower second opening; d) anisotropically etching the second layer of material from outwardly of the first layer and from the first opening base to effectively provide inner sidewall spacers within the first opening; e) providing a gate dielectric layer within the second opening; f) providing a layer of electrically conductive gate material over the first layer and to within the second opening over the gate dielectric layer to fill the second opening with conductive gate material; g) without masking, planarize etching the conductive gate material layer substantially selective relative to the first layer to define a transistor gate within the second opening; and h) providing opposing source and drain regions relative to the transistor gate.
摘要翻译：形成场效应晶体管的半导体处理方法包括：a）在衬底上提供第一层材料; b）提供穿过第一层的第一开口，第一开口具有宽度和底部; c）在所述第一层之上提供第二层材料，并且在所述第一开口内提供厚度小于所述第一开口宽度的一半，以小于完全填充所述第一开口并限定较窄的第二开口; d）从所述第一层的外部和所述第一开口底部各向异性地蚀刻所述第二层材料，以有效地在所述第一开口内提供内部侧壁间隔物; e）在所述第二开口内提供栅极电介质层; f）在所述第一层上提供导电栅极材料层，并且在所述栅极介电层上方的所述第二开口内提供导电栅极材料层，以用导电栅极材料填充所述第二开口; g）没有掩蔽，平坦化蚀刻相对于第一层基本上选择性的导电栅极材料层，以在第二开口内限定晶体管栅极; 以及h）相对于所述晶体管栅极提供相对的源极和漏极区域。

3. 发明授权

US06740821B1 Selectively configurable circuit board 有权
公开(公告)号：US06740821B1
公开(公告)日：2004-05-25
申请号：US10086956
申请日：2002-03-01
申请人： Tongbi Jiang , David Kao
发明人： Tongbi Jiang , David Kao
IPC分类号： H05K116
CPC分类号： H05K1/0293 , H01L2924/0002 , H05K1/029 , H05K1/095 , H05K2201/0129 , H05K2201/0305 , H05K2201/10689 , H05K2203/107 , H05K2203/1105 , H05K2203/173 , H01L2924/00
摘要： Embodiments of the invention provide thermally actuatable switches and selectively configurable circuit boards which may employ such switches. A circuit board of one embodiment includes a substrate having board leads and a plurality of electrical connectors arranged adjacent a component site. Selectively configurable circuitry may be carried by the substrate and adapted to selectively couple selected ones of the electrical connectors to selected ones of the board leads. One or more trace may be associated with each of the electrical connectors and one or more of these traces may include a thermally actuatable switch that can be selectively closed. The thermally actuatable switch may comprise a gap between two conductive lengths of the conductive trace, an exposed switch surface, and a thermally responsive member that may wet the exposed switch surface when selectively heated above an activation temperature.

4. 发明授权

US6005273A Transistors having controlled conductive spacers, uses of such transistors and methods of making such transistors 失效
标题翻译：具有受控导电间隔物的晶体管，这种晶体管的使用以及制造这种晶体管的方法
公开(公告)号：US6005273A
公开(公告)日：1999-12-21
申请号：US987819
申请日：1997-12-10
申请人： Fernando Gonzalez , David Kao
发明人： Fernando Gonzalez , David Kao
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8234 , H01L27/088 , H01L27/108 , H01L29/49 , H01L29/78
CPC分类号： H01L29/66484 , H01L21/28132 , H01L21/823468 , H01L27/088 , H01L27/108 , H01L29/4983 , H01L29/7831 , H01L21/28114
摘要： A transistor structure includes an insulated conductive gate spacer or a conductive layer under a nonconductive spacer, together forming a composite spacer, which contacted and driven separately from the conventional gate of the transistor. The gate spacer, conductive layer of a composite spacer or a portion or portions thereof serve as a control or controls for the transistors taking the form of a second gate or second and third gates for the transistors. The transistors may be used throughout an integrated circuit or it may be preferred to use the improved transistor only in critical speed paths of an integrated circuit. Delays within circuits including the improved transistors are reduced since the drain voltage can be higher than VCC and the BVDSS and subthreshold voltage are substantially higher than standard LDD transistors. When the improved transistors are used selectively within an integrated circuit, the remaining devices can be structured as standard LDD transistors, using the gate spacers in a conventional manner, and/or as conventional transistors.
摘要翻译：晶体管结构包括绝缘导电栅极间隔物或非导电间隔物下的导电层，一起形成与晶体管的常规栅极分开接触和驱动的复合间隔物。复合间隔物的栅极间隔物，导电层或其部分或部分用作晶体管的控制或控制，晶体管采取晶体管的第二栅极或第二和第三栅极的形式。晶体管可以在整个集成电路中使用，或者优选仅在集成电路的临界速度路径中使用改进的晶体管。包括改进的晶体管在内的电路中的延迟减小，因为漏极电压可以高于VCC，并且BVDSS和亚阈值电压显着高于标准LDD晶体管。当改进的晶体管被选择性地用于集成电路内时，其余的器件可以被构造为使用常规方式的栅极间隔物和/或常规晶体管的标准LDD晶体管。

5. 发明申请

US20050258535A1 Selectively configurable circuit board 审中-公开
标题翻译：可选配置的电路板
公开(公告)号：US20050258535A1
公开(公告)日：2005-11-24
申请号：US11190350
申请日：2005-07-26
申请人： Tongbi Jiang , David Kao
发明人： Tongbi Jiang , David Kao
IPC分类号： H01L23/34 , H05K1/00 , H05K1/09
CPC分类号： H05K1/0293 , H01L2924/0002 , H05K1/029 , H05K1/095 , H05K2201/0129 , H05K2201/0305 , H05K2201/10689 , H05K2203/107 , H05K2203/1105 , H05K2203/173 , H01L2924/00
摘要： Embodiments of the invention provide thermally actuatable switches and selectively configurable circuit boards which may employ such switches. A circuit board of one embodiment includes a substrate having board leads and a plurality of electrical connectors arranged adjacent a component site. Selectively configurable circuitry may be carried by the substrate and adapted to selectively couple selected ones of the electrical connectors to selected ones of the board leads. One or more trace may be associated with each of the electrical connectors and one or more of these traces may include a thermally actuatable switch that can be selectively closed. The thermally actuatable switch may comprise a gap between two conductive lengths of the conductive trace, an exposed switch surface, and a thermally responsive member that may wet the exposed switch surface when selectively heated above an activation temperature.
摘要翻译：本发明的实施例提供可热致动的开关和可以采用这种开关的选择性可配置的电路板。一个实施例的电路板包括具有板引线和布置在部件部位附近的多个电连接器的基板。可选配置的电路可以由衬底承载，并且适于选择性地将选定的电连接器耦合到选定的电路板引线。一个或多个迹线可以与每个电连接器相关联，并且这些迹线中的一个或多个迹线可以包括可以选择性地闭合的热致动开关。热致动开关可以包括在导电迹线的两个导电长度，暴露的开关表面和热响应部件之间的间隙，当选择性地加热到高于激活温度时，该热响应部件可以润湿暴露的开关表面。

6. 发明申请

US20050012174A1 Selectively doped trench device isolation 有权
标题翻译：选择性掺杂沟槽器件隔离
公开(公告)号：US20050012174A1
公开(公告)日：2005-01-20
申请号：US10920579
申请日：2004-08-17
申请人： David Kao , Rongsheng Yang
发明人： David Kao , Rongsheng Yang
IPC分类号： H01L21/763 , H01L21/765 , H01L29/00
CPC分类号： H01L21/823481 , H01L21/763 , H01L21/765
摘要： A selectively doped trench isolation device is provided. The trench isolation device of the preferred embodiment includes a semiconductor substrate having a trench. A thin field oxide layer is grown on the side walls of the trench, and the trench is filled with a heavily doped polysilicon. The work function difference between the substrate and the heavily doped polysilicon increases the field threshold voltage of the gated trench isolation device so that smaller isolation structures can be formed between adjacent active devices in higher density integrated circuits.
摘要翻译：提供了选择性掺杂沟槽隔离装置。优选实施例的沟槽隔离装置包括具有沟槽的半导体衬底。在沟槽的侧壁上生长薄的氧化物层，并且沟槽被重掺杂的多晶硅填充。衬底和重掺杂多晶硅之间的功函数差异增加了门控沟槽隔离器件的场阈值电压，使得可以在较高密度集成电路中的相邻有源器件之间形成更小的隔离结构。

7. 发明授权

US06580640B2 Non-volatile memory device with tunnel oxide 失效
公开(公告)号：US06580640B2
公开(公告)日：2003-06-17
申请号：US09801239
申请日：2001-03-07
申请人： David Kao
发明人： David Kao
IPC分类号： G11C1604
CPC分类号： G11C16/3418
摘要： A method and apparatus invention that relates to the reduction of leakage current through a tunnel oxide layer of a memory cell to improve data retention. One method of operating a non-volatile memory cell comprises placing electrons on a floating gate of the memory cell and then placing positive charge on a control gate of the memory cell to improve data retention. The positive charge causes the electrons on the floating gate to migrate away from a tunnel oxide layer of the memory cell. In one embodiment, a Flash memory device comprises a memory array of multiple memory cells. Each memory cell comprises a control gate, a floating gate, an inter-gate dielectric layer positioned between the control gate and the floating gate, a substrate, and a tunnel oxide layer positioned between the floating gate and the substrate. Control circuitry is used to control memory operations and couple a positive charge to the control gate of the memory cell to attract electrons on the floating gate of the memory cell away from the tunnel oxide layer of the memory cell.

8. 发明授权

US6011307A Anisotropic conductive interconnect material for electronic devices, method of use and resulting product 失效
标题翻译：用于电子设备的各向异性导电互连材料，使用方法和所得产品
公开(公告)号：US6011307A
公开(公告)日：2000-01-04
申请号：US909683
申请日：1997-08-12
申请人： Tongbi Jiang , Zhiqiang Wu , David Kao , Rongsheng Yang
发明人： Tongbi Jiang , Zhiqiang Wu , David Kao , Rongsheng Yang
IPC分类号： H01L21/60 , H01L23/498 , H01L29/43
CPC分类号： H01L24/12 , H01L23/49827 , H01L23/49883 , H01L24/11 , H01L24/16 , H01L24/29 , H01L24/81 , H01L24/83 , H01L2224/05568 , H01L2224/05573 , H01L2224/1147 , H01L2224/13099 , H01L2224/13111 , H01L2224/16 , H01L2224/29101 , H01L2224/29111 , H01L2224/2919 , H01L2224/2929 , H01L2224/29355 , H01L2224/29357 , H01L2224/2936 , H01L2224/29398 , H01L2224/29499 , H01L2224/83192 , H01L2224/838 , H01L2924/01005 , H01L2924/01006 , H01L2924/01011 , H01L2924/01013 , H01L2924/01022 , H01L2924/01025 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01039 , H01L2924/0104 , H01L2924/0105 , H01L2924/01056 , H01L2924/01082 , H01L2924/0132 , H01L2924/0133 , H01L2924/014 , H01L2924/0665 , H01L2924/0781 , H01L2924/14 , H01L2924/1579
摘要： Conductive interconnections are formed by depositing an adhesive material, made up of ferromagnetic particles dispersed within a matrix material, on a semiconductor substrate, such as an electronic component, and applying a magnetic field between an exposed surface of the adhesive material and an attached surface of the adhesive material (abutting the semiconductor substrate), such that a plurality of the ferromagnetic particles move and align within the matrix material under the influence of the magnetic field. One method of the present invention comprises depositing the adhesive material on a contact site of a first electronic component. A second electronic component having a contact site is aligned over the adhesive material and a magnetic field is applied between the first electronic component and the second electronic component. The first electronic component and the second electronic component are then pressed together such that a portion of the plurality of the ferromagnetic particles makes electrical contact with both the first electronic component bond pad and its corresponding second electronic component bond pad.
摘要翻译：导电互连通过将分散在基体材料中的铁磁粒子构成的粘合剂材料沉积在诸如电子部件的半导体衬底上并在粘合剂材料的暴露表面和附着表面之间施加磁场而形成粘合剂材料（邻接半导体衬底），使得多个铁磁性颗粒在磁场的影响下在基体材料内移动和对准。本发明的一种方法包括将粘合剂材料沉积在第一电子部件的接触部位上。具有接触位置的第二电子部件在粘合剂材料上对准，并且在第一电子部件和第二电子部件之间施加磁场。然后将第一电子部件和第二电子部件压在一起，使得多个铁磁性粒子的一部分与第一电子部件接合焊盘及其对应的第二电子部件接合焊盘进行电接触。

9. 发明授权

US07646213B2 On-die system and method for controlling termination impedance of memory device data bus terminals 有权
标题翻译：用于控制存储器件数据总线端子的终端阻抗的片上系统和方法
公开(公告)号：US07646213B2
公开(公告)日：2010-01-12
申请号：US11804176
申请日：2007-05-16
申请人： David Kao
发明人： David Kao
IPC分类号： H03K19/003
CPC分类号： H03K19/017545 , H04L25/0278 , H04L25/028
摘要： A system for controlling the termination impedance of memory device data bus terminals is fabricated on the same die as the memory device. The system includes a termination resistor connected to each data bus terminal, which is connected in parallel with several transistors that are selectively turned on to adjust the termination impedance. The transistors are controlled by a circuit that determines the resistance of the termination resistor and turns on the correct number of transistor to properly set the termination impedance. In one example, the resistance of the termination resistor is determined by directly measuring a resistor of the same type as the termination resistor. In another example, the resistance of the termination resistor is determined indirectly by measuring parameters that affect the resistance of the termination resistor. In either case, the system can maintain the termination impedance of the data bus terminals constant despite changes in the termination resistor.
摘要翻译：用于控制存储器件数据总线端子的端接阻抗的系统在与存储器件相同的芯片上制造。该系统包括连接到每个数据总线端子的终端电阻器，其与选择性地导通的几个晶体管并联连接以调整终端阻抗。晶体管由确定终端电阻的电阻的电路控制，并打开正确数量的晶体管以正确设置端接阻抗。在一个示例中，终端电阻器的电阻通过直接测量与终端电阻器相同类型的电阻器来确定。在另一个例子中，通过测量影响终端电阻电阻的参数间接确定终端电阻的电阻。在任一种情况下，尽管端接电阻器发生变化，系统仍能保持数据总线端子的终端阻抗恒定。

10. 发明申请

US20060220109A1 Selectively doped trench device isolation 审中-公开
标题翻译：选择性掺杂沟槽器件隔离
公开(公告)号：US20060220109A1
公开(公告)日：2006-10-05
申请号：US11417807
申请日：2006-05-03
申请人： David Kao , Rongsheng Yang
发明人： David Kao , Rongsheng Yang
IPC分类号： H01L29/94
CPC分类号： H01L21/823481 , H01L21/763 , H01L21/765
摘要： A selectively doped trench isolation device is provided. The trench isolation device of the preferred embodiment includes a semiconductor substrate having a trench. A thin field oxide layer is grown on the side walls of the trench, and the trench is filled with a heavily doped polysilicon. The work function difference between the substrate and the heavily doped polysilicon increases the field threshold voltage of the gated trench isolation device so that smaller isolation structures can be formed between adjacent active devices in higher density integrated circuits.
摘要翻译：提供了选择性掺杂沟槽隔离装置。优选实施例的沟槽隔离装置包括具有沟槽的半导体衬底。在沟槽的侧壁上生长薄的氧化物层，并且沟槽被重掺杂的多晶硅填充。衬底和重掺杂多晶硅之间的功函数差异增加了门控沟槽隔离器件的场阈值电压，使得可以在较高密度集成电路中的相邻有源器件之间形成更小的隔离结构。

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