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61. 发明授权

US07814343B2 Semiconductor integrated circuit for reducing power consumption and enhancing processing speed 失效
标题翻译：半导体集成电路，用于降低功耗并提高处理速度
公开(公告)号：US07814343B2
公开(公告)日：2010-10-12
申请号：US11605362
申请日：2006-11-29
申请人： Yusuke Kanno , Hiroyuki Mizuno , Naohiko Irie
发明人： Yusuke Kanno , Hiroyuki Mizuno , Naohiko Irie
IPC分类号： G06F1/00 , G06F1/26 , G06F1/32 , G06F12/00
CPC分类号： G06F1/3293 , G06F1/3203 , H01L21/823462 , Y02D10/122 , Y02D10/126
摘要： A semiconductor integrated circuit device which consumes less power and enables real-time processing. The semiconductor integrated circuit device includes thermal sensors which detect temperature and determine whether the detection result exceeds reference values and output the result, and a control block capable of controlling the operations of arithmetic blocks based on the output signals of the thermal sensors. The control block returns to an operation state from a suspended state with an interrupt signal based on the output signals of the thermal sensors and determines the operation conditions of the arithmetic blocks to ensure that the temperature conditions of the arithmetic blocks are satisfied. Thereby, power consumption is reduced and real-time processing efficiency is improved.
摘要翻译：一种半导体集成电路器件，其消耗较少功率并实现实时处理。半导体集成电路装置包括检测温度并确定检测结果是否超过参考值并输出结果的热传感器，以及能够基于热传感器的输出信号来控制运算块的操作的控制块。控制块基于热传感器的输出信号从具有中断信号的挂起状态返回到操作状态，并且确定运算块的操作条件，以确保运算块的温度条件得到满足。从而降低了功耗，提高了实时处理效率。

62. 发明申请

US20060291110A1 Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件
公开(公告)号：US20060291110A1
公开(公告)日：2006-12-28
申请号：US11447168
申请日：2006-06-06
申请人： Yusuke Kanno , Hiroyuki Mizuno , Yoshihiko Yasu , Kenji Hirose , Takahiro Irita
发明人： Yusuke Kanno , Hiroyuki Mizuno , Yoshihiko Yasu , Kenji Hirose , Takahiro Irita
IPC分类号： H02H7/00
CPC分类号： H01L27/11898 , G06F17/5068 , G06F17/5072 , G11C11/419 , H01L23/48 , H01L23/50 , H01L23/528 , H01L27/00 , H01L27/02 , H01L27/0203 , H01L27/0207 , H01L27/11807 , H01L29/7835 , H01L2027/11881 , H01L2924/0002 , H03K3/0315 , H03K3/0375 , H03K17/16 , H01L2924/00
摘要： A semiconductor integrated circuit device is provided, the circuit being capable of arranging a control signal system, avoiding a danger of failure to check an indefinite signal propagation prevention circuit or the like, further facilitating a check oriented to mounting on an automated tool, and facilitating power shutdown control inside of a chip. In the semiconductor integrated circuit device, power shutdown priorities are provided by independent power domains Area A to Area I. A rule is provided, the rule defining that, in the case where a circuit having a high priority is turned ON, a power domain having its lower priority cannot be turned OFF, thereby facilitating a designing method. In addition, areas capable of applying still another power supply are provided in the independent power areas Area A to Area I. In that area, a relay buffer (repeater) and a clock buffer or an information retaining latch for saving information are integrated. A layout may be provided in a direction vertical to a direction in which cells are arranged in a row direction for the purpose of dispersing a current of a light supply line.
摘要翻译：提供了一种半导体集成电路器件，该电路能够布置控制信号系统，避免不能检查不确定的信号传播防止电路等的危险，进一步便于针对安装在自动化工具上的检查，并且促进功率关断控制芯片内部。在半导体集成电路装置中，功率关闭优先级由独立的电源区域A至区域I提供。规定了在具有高优先级的电路被接通的情况下，规定了具有其较低优先级不能关闭，从而有助于设计方法。此外，在独立电源区域A至区域I中提供能够应用另一电源的区域。在该区域中，集成了用于保存信息的中继缓冲器（中继器）和时钟缓冲器或信息保持锁存器。为了分散供电线的电流，布置可以沿垂直于单元布置在行方向上的方向设置。

63. 发明申请

US20060102934A1 Semiconductor integrated circuit device 有权
公开(公告)号：US20060102934A1
公开(公告)日：2006-05-18
申请号：US11320751
申请日：2005-12-30
申请人： Yusuke Kanno , Hiroyuki Mizuno , Naohiko Irie
发明人： Yusuke Kanno , Hiroyuki Mizuno , Naohiko Irie
IPC分类号： H01L27/10
CPC分类号： G01R31/318572 , G11C5/063 , G11C11/417 , H01L27/0207 , H01L27/092 , H01L27/11807 , H01L2924/0002 , H03K3/356008 , H03K3/35625 , H03K19/0016 , H01L2924/00
摘要： In a low power consumption mode in which prior data is retained upon power shutdown, the return speed thereof is increased. While use of an existent data retaining flip-flop may be considered, this is not preferred since it increases area overhead such as enlargement of the size of a cell. A power line for data retention for power shutdown is formed with wirings finer than a usual main power line. Preferably, power lines for a data retention circuit are considered as signal lines and wired by automatic placing and mounting. For this purpose, terminals for the power line for data retention are previously designed by providing the terminals therefor for the cell in the same manner as in the existent signal lines. Additional layout for power lines is no longer necessary for the cell, which enables a decrease in the area and design by an existent placing and routing tool.

64. 发明授权

US07023058B2 Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US07023058B2
公开(公告)日：2006-04-04
申请号：US10921854
申请日：2004-08-20
申请人： Yusuke Kanno , Hiroyuki Mizuno , Naohiko Irie
发明人： Yusuke Kanno , Hiroyuki Mizuno , Naohiko Irie
IPC分类号： H01L29/76 , H01L23/48
CPC分类号： G01R31/318572 , G11C5/063 , G11C11/417 , H01L27/0207 , H01L27/092 , H01L27/11807 , H01L2924/0002 , H03K3/356008 , H03K3/35625 , H03K19/0016 , H01L2924/00
摘要： In a low power consumption mode in which prior data is retained upon power shutdown, the return speed thereof is increased. While use of an existent data retaining flip-flop may be considered, this is not preferred since it increases area overhead such as enlargement of the size of a cell. A power line for data retention for power shutdown is formed with wirings finer than a usual main power line. Preferably, power lines for a data retention circuit are considered as signal lines and wired by automatic placing and mounting. For this purpose, terminals for the power line for data retention are previously designed by providing the terminals therefor for the cell in the same manner as in the existent signal lines. Additional layout for power lines is no longer necessary for the cell, which enables a decrease in the area and design by an existent placing and routing tool.
摘要翻译：在功率关闭时保留先前数据的低功耗模式下，其返回速度增加。虽然可以考虑使用现有的数据保持触发器，但是这不是优选的，因为它增加了诸如扩大单元大小的面积开销。用于电源关闭的数据保持的电源线由比通常的主电源线更细的布线形成。优选地，用于数据保持电路的电力线被认为是信号线，并通过自动放置和安装进行布线。为此，先前通过以与现有信号线相同的方式为小区提供终端来设计用于数据保持的电力线的终端。电池线的附加布局不再需要，这使得现有的放置和布线工具能够减少面积和设计。

65. 发明授权

US06700429B2 Semiconductor device 失效
公开(公告)号：US06700429B2
公开(公告)日：2004-03-02
申请号：US10211565
申请日：2002-08-05
申请人： Yusuke Kanno , Hiroyuki Mizuno , Kazumasa Yanagisawa
发明人： Yusuke Kanno , Hiroyuki Mizuno , Kazumasa Yanagisawa
IPC分类号： H03L500
CPC分类号： H03K5/1534 , H03K3/356113 , H03K19/018521
摘要： A semiconductor device includes a differential level converter circuit that receives a first signal and outputs a second signal of greater amplitude. The differential level converter has a first MISFET pair for receiving the first signal, a second MISFET pair for enhancing the withstand voltage of the first MISFET pair, and a third MISFET pair with cross-coupled gates for latching the second signal from output. The film thickness of the gate insulating films of the second and third MISFET pairs is made thicker than that of the first MISFET pair, and the threshold voltages of the first and second MISFET pairs are made smaller than that of the third MISFET pair. This level converter circuit operates at high speed even if there is a large difference in the signal amplitude before and after level conversion.

66. 发明授权

US06848035B2 Semiconductor device with multi-bank DRAM and cache memory 失效
标题翻译：具有多组DRAM和高速缓冲存储器的半导体器件
公开(公告)号：US06848035B2
公开(公告)日：2005-01-25
申请号：US10164558
申请日：2002-06-10
申请人： Satoru Akiyama , Yusuke Kanno , Takao Watanabe
发明人： Satoru Akiyama , Yusuke Kanno , Takao Watanabe
IPC分类号： G06F12/08 , G11C11/401 , G11C11/403 , G11C11/406 , G11C11/41 , G06F12/00
CPC分类号： G11C11/40615 , G06F12/0893 , G06F2212/3042 , G11C11/406 , G11C2207/2245
摘要： A semiconductor device is designed to hide refresh operations even when the data width of a cache line differs from that of the external data bus in a memory that uses a cache memory and a DRAM with a plurality of banks. The semiconductor device includes a plurality of memory banks BANK0 to BANK127, each having a plurality of memory cells, as well as a cache memory CACHEMEM used to retain information read from the plurality of memory banks. The cache memory CACHEMEM includes a plurality of entries, each having a data memory DATAMEM and a tag memory TAGMEM. The data memory DATAMEM has a plurality of sub lines DATA0 to DATA3 and the tag memory TAGMEM has a plurality of valid bits V0 to V3 and a plurality of dirty bits D0 to D3.
摘要翻译：即使当高速缓存行的数据宽度与使用高速缓冲存储器的存储器和具有多个存储体的DRAM的外部数据总线的数据宽度不同时，半导体器件被设计为隐藏刷新操作。半导体器件包括多个存储器组BANK0至BANK127，每个存储器组具有多个存储器单元，以及用于保持从多个存储体读取的信息的高速缓冲存储器CACHEMEM。高速缓存存储器CACHEMEM包括多个条目，每个条目具有数据存储器DATAMEM和标签存储器TAGMEM。数据存储器DATAMEM具有多条副线DATA0至DATA3，标签存储器TAGMEM具有多个有效位V0至V3和多个脏位D0至D3。

67. 发明申请

US20050111284A1 Semiconductor device with multi-bank DRAM and cache memory 审中-公开
标题翻译：具有多组DRAM和高速缓冲存储器的半导体器件
公开(公告)号：US20050111284A1
公开(公告)日：2005-05-26
申请号：US11019269
申请日：2004-12-23
申请人： Satoru Akiyama , Yusuke Kanno , Takao Watanabe
发明人： Satoru Akiyama , Yusuke Kanno , Takao Watanabe
IPC分类号： G06F12/08 , G11C11/401 , G11C11/403 , G11C11/406 , G11C11/41 , G11C7/00
CPC分类号： G11C11/40615 , G06F12/0893 , G06F2212/3042 , G11C11/406 , G11C2207/2245
摘要： To provide means that can hide refresh operations even when the data width of a cache line differs from that of the external data bus in a memory that uses a cache memory and a DRAM consisting of a plurality of banks. A semiconductor device consisting of a plurality of memory banks BANK0 to BANK127, each consisting of a plurality of memory cells, as well as a cache memory CACHEMEM used to retain information read from the plurality of memory banks. The cache memory CACHEMEM consists of a plurality of entries, each having a data memory DATAMEM and a tag memory TAGMEM. The data memory DATAMEM consists of a plurality of sub lines DATA0 to DATA3 and the tag memory TAGMEM Consists of a plurality of valid bits V0 to V3 and a plurality of dirty bits D0 to D3. It is possible to realize a memory with excellent operability, causing no refresh operation to delay external accesses. In other words, it is possible to realize a memory compatible with an SRAM in which refresh operations are hidden from external.
摘要翻译：即使当高速缓存行的数据宽度与使用高速缓冲存储器的存储器和由多个存储体组成的DRAM的外部数据总线的数据宽度不同时，也可以隐藏刷新操作。由多个存储器组BANK 0至BANK 127组成的半导体器件，每个存储器组由多个存储器单元组成，以及用于保持从多个存储体读取的信息的高速缓冲存储器CACHEMEM。高速缓冲存储器CACHEMEM由多个条目组成，每个条目具有数据存储器DATAMEM和标签存储器TAGMEM。数据存储器DATAMEM由多条子线DATA 0至数据3组成，标签存储器TAGMEM由多个有效位V 0至V 3和多个脏位D 0至D 3组成。可以实现具有优异可操作性的存储器，不会引起刷新操作来延迟外部访问。换句话说，可以实现与其中刷新操作被外部隐藏的SRAM兼容的存储器。

68. 发明授权

US08183899B2 Semiconductor integrated circuit and control method for clock signal synchronization 失效
标题翻译：半导体集成电路和时钟信号同步控制方法
公开(公告)号：US08183899B2
公开(公告)日：2012-05-22
申请号：US12615607
申请日：2009-11-10
申请人： Yusuke Kanno , Makoto Saen , Shigenobu Komatsu , Masafumi Onouchi
发明人： Yusuke Kanno , Makoto Saen , Shigenobu Komatsu , Masafumi Onouchi
IPC分类号： H03L7/00
CPC分类号： H03L7/0814 , G06F1/10 , G06F1/3203 , G06F1/324 , G06F1/3296 , H03L7/0818 , H03L7/089 , Y02D10/126 , Y02D10/172
摘要： There is a need to ensure operation performance of a circuit region under DVFS control at low costs and highly precisely while a power-supply voltage change is made to the region. A first circuit (FVA) uses a first power-supply voltage (VDDA) for operation. A second circuit (NFVA) uses a second power-supply voltage (VDDB) for operation. A clock delay may be adjusted between paths for transmitting a clock to these circuits. When VDDA equals VDDB, a clock is distributed to FVA through a path that does not contain a delay device for phase adjustment. When the power-supply voltage for the FVA region is reduced, a clock is distributed to the FVA region based on a phase equivalent to one or two cycles of the clock displaced. Synchronization control is provided to synchronize clocks (CKAF and CKBF) and ensures operation so that a phase of two clocks to be compared fits in a range of design values while the power-supply voltage for the first circuit is changed.
摘要翻译：在对区域进行电源电压变化的情况下，需要以低成本和高精度地确保DVFS控制下的电路区域的操作性能。第一电路（FVA）使用第一电源电压（VDDA）进行操作。第二电路（NFVA）使用第二电源电压（VDDB）进行操作。可以在将时钟发送到这些电路的路径之间调整时钟延迟。当VDDA等于VDDB时，通过不包含用于相位调整的延迟装置的路径将时钟分配给FVA。当FVA区域的电源电压降低时，基于相当于时钟位移的一个或两个周期的相位，将时钟分配给FVA区域。提供同步控制以同步时钟（CKAF和CKBF）并确保操作，使得待比较的两个时钟的相位适合于设计值的范围，同时改变第一电路的电源电压。

69. 发明授权

US07954023B2 Semiconductor integrated circuit including power domains 有权
标题翻译：半导体集成电路包括电源域
公开(公告)号：US07954023B2
公开(公告)日：2011-05-31
申请号：US12342015
申请日：2008-12-22
申请人： Kazuo Otsuga , Kenichi Osada , Yusuke Kanno
发明人： Kazuo Otsuga , Kenichi Osada , Yusuke Kanno
IPC分类号： G01R31/28
CPC分类号： H03K19/0016
摘要： A scan chain configuration and a control method for the same are provided, which are optimized for the leakage current reduction technique by a vector input in SoC in which many functional blocks are mounted. The semiconductor integrated circuit includes: plural power domains (Area1-AreaN) which have plural functional blocks; power switches (PSW1-PSWN) which can supply a power source for operation to the power domains; a scan chain provided for every power domain, and a memory unit (VEC) which supplies, to a scan chain, a vector to enable shifting to a low-leakage state. By re-coupling the scan chain only to a non-operating functional block, it is possible to perform shifting to a low-leakage state for a short time.
摘要翻译：提供了一种扫描链配置及其控制方法，其通过SoC中的矢量输入针对泄漏电流降低技术进行了优化，其中安装了许多功能块。半导体集成电路包括：具有多个功能块的多个电力域（Area1-AreaN）电源开关（PSW1-PSWN），可以向电源区域提供运行的电源; 为每个功率域提供的扫描链，以及向扫描链提供矢量以使其能够转换到低泄漏状态的存储器单元（VEC）。通过将扫描链重新耦合到非操作功能块，可以在短时间内进行低泄漏状态的切换。

70. 发明申请

US20100301893A1 SEMICONDUCTOR INTEGRATED CIRCUIT AND CIRCUIT OPERATION METHOD 失效
标题翻译：半导体集成电路和电路操作方法
公开(公告)号：US20100301893A1
公开(公告)日：2010-12-02
申请号：US12787090
申请日：2010-05-25
申请人： Kazuo OTSUGA , Yusuke Kanno
发明人： Kazuo OTSUGA , Yusuke Kanno
IPC分类号： G01R31/26
CPC分类号： G01R31/31721
摘要： In a semiconductor integrated circuit wherein low-threshold-voltage and high-threshold-voltage transistors are disposed mixedly, the operating speed of each transistor can be properly controlled in speed control execution through regulation of a power supply voltage VDD. The semiconductor integrated circuit comprises an internal circuit and measuring circuits. The internal circuit comprises a low-threshold-voltage MOS transistor and a high-threshold-voltage MOS transistor, and the degree of threshold voltage variation of the low-threshold-voltage MOS transistor is larger than the degree of threshold voltage variation of the high-threshold-voltage MOS transistor. The measuring circuit detects which one of fast, typical, and slow states is taken by both the low-threshold-voltage MOS transistor and the high-threshold-voltage MOS transistor. When the result data detected indicates the fast state, the power supply voltage VDD is set to a lower power supply voltage level “VDD−ΔVDD” corresponding to a small variation gradient “β[V/σ]”. When the result data detected indicates the typical state, the power supply voltage VDD is set to an intermediate power supply voltage level “VDD±0”. When the result data detected indicates the slow state, the power supply voltage VDD is set to a higher power supply voltage level “VDD+ΔVDD” corresponding to a large variation gradient “α[V/σ]”.
摘要翻译：在其中低阈值电压和高阈值电压晶体管被混合地布置的半导体集成电路中，通过调节电源电压VDD可以在速度控制执行中适当地控制每个晶体管的工作速度。半导体集成电路包括内部电路和测量电路。内部电路包括低阈值电压MOS晶体管和高阈值电压MOS晶体管，并且低阈值电压MOS晶体管的阈值电压变化程度大于高阈值电压MOS晶体管的阈值电压变化的程度阈值电压MOS晶体管。测量电路检测低阈值电压MOS晶体管和高阈值电压MOS晶体管中的哪一个快速，典型和慢速状态。当检测到的结果数据指示快速状态时，电源电压VDD被设置为对应于小变化梯度“＆bgr; [V /＆sgr]]的较低电源电压电平”VDD-＆Dgr; VDD“。当检测到的结果数据表示典型状态时，将电源电压VDD设定为中间电源电压电平“VDD±0”。当检测到的结果数据表示慢速状态时，将电源电压VDD设定为与较大变化梯度“α[V /＆sgr”]对应的较高电源电压电平“VDD +＆Dgr; VDD”。

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