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1. 发明授权

US08829968B2 Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件
公开(公告)号：US08829968B2
公开(公告)日：2014-09-09
申请号：US12555143
申请日：2009-09-08
申请人： Hiroyuki Mizuno , Yusuke Kanno , Kazumasa Yanagisawa , Yoshihiko Yasu , Nobuhiro Oodaira
发明人： Hiroyuki Mizuno , Yusuke Kanno , Kazumasa Yanagisawa , Yoshihiko Yasu , Nobuhiro Oodaira
IPC分类号： H03L5/00
CPC分类号： H03K19/0016 , H01L23/5286 , H01L27/0207 , H01L27/092 , H01L27/0928 , H01L27/11898 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A semiconductor integrated circuit device provided with a first circuit block BLK1, a second circuit block DRV1 and a conversion circuit MIO1 for connecting the first circuit block to the second circuit block. The first circuit block includes a first mode for applying a supply voltage and a second mode for shutting off the supply voltage. The conversion circuit is provided with a function for maintaining the potential of an input node of the second circuit block at an operation potential, thereby suppressing a penetrating current flow when the first circuit block is in the second mode. The conversion circuit (MIO1 to MIO4) are commonly used for connecting circuit blocks.
摘要翻译：具有第一电路块BLK1，第二电路块DRV1和用于将第一电路块连接到第二电路块的转换电路MIO1的半导体集成电路器件。第一电路块包括用于施加电源电压的第一模式和用于关断电源电压的第二模式。转换电路具有将第二电路块的输入节点的电位维持在操作电位的功能，从而当第一电路块处于第二模式时抑制穿透电流流动。转换电路（MIO1〜MIO4）通常用于连接电路块。

2. 发明授权

US07254680B2 Semiconductor integrated circuit and data processing system 有权
标题翻译：半导体集成电路和数据处理系统
公开(公告)号：US07254680B2
公开(公告)日：2007-08-07
申请号：US11641808
申请日：2006-12-20
申请人： Kazushige Ayukawa , Seiji Miura , Jun Satoh , Takao Watanabe , Kazumasa Yanagisawa , Yusuke Kanno , Hiroyuki Mizuno
发明人： Kazushige Ayukawa , Seiji Miura , Jun Satoh , Takao Watanabe , Kazumasa Yanagisawa , Yusuke Kanno , Hiroyuki Mizuno
IPC分类号： G06F12/00 , G11C7/00
CPC分类号： G11C7/1006 , G06F12/0215 , G06F12/0893 , G06F13/161 , G06F2212/3042 , G11C7/065 , G11C11/4091 , G11C11/4093 , G11C2207/104 , G11C2207/2245
摘要： To enhance the speed of first access (read access different in word line from the previous access) to a multi-bank memory, multi-bank memory macro structures are used. Data are held in a sense amplifier for every memory bank. When access is hit to the held data, data latched by the sense amplifier are output to thereby enhance the speed of first access to the memory macro structures. Namely, each memory bank is made to function as a sense amplifier cache. To enhance the hit ratio of such a sense amplifier cache more greatly, an access controller self-prefetches the next address (an address to which a predetermined offset has been added) after access to a memory macro structure so that data in the self-prefetched address are preread by a sense amplifier in another memory bank.
摘要翻译：为了提高第一次访问的速度（从先前访问的字线读取访问）到多存储体存储器，使用多存储体存储器宏结构。数据保存在每个存储体的读出放大器中。当对保持的数据进行访问时，输出由读出放大器锁存的数据，从而提高对存储器宏结构的首次访问的速度。即，使每个存储体用作读出放大器高速缓存。为了更好地提高这种感测放大器高速缓存的命中率，访问控制器在访问存储器宏结构之后自我预取下一个地址（已经添加了预定偏移量的地址），以便自我预取中的数据地址由另一个存储体中的读出放大器预读。

3. 发明授权

US06381671B1 Semiconductor integrated circuit and data processing system 有权
标题翻译：半导体集成电路和数据处理系统
公开(公告)号：US06381671B1
公开(公告)日：2002-04-30
申请号：US09342240
申请日：1999-06-29
申请人： Kazushige Ayukawa , Seiji Miura , Jun Satoh , Takao Watanabe , Kazumasa Yanagisawa , Yusuke Kanno , Hiroyuki Mizuno
发明人： Kazushige Ayukawa , Seiji Miura , Jun Satoh , Takao Watanabe , Kazumasa Yanagisawa , Yusuke Kanno , Hiroyuki Mizuno
IPC分类号： G06F1200
CPC分类号： G11C7/1006 , G06F12/0215 , G06F12/0893 , G06F13/161 , G06F2212/3042 , G11C7/065 , G11C11/4091 , G11C11/4093 , G11C2207/104 , G11C2207/2245
摘要： To enhance the speed of first access (read access different in word line from the previous access) to a multi-bank memory, multi-bank memory macro structures are used. Data are held in a sense amplifier for every memory bank. When access is hit to the held data, data latched by the sense amplifier are output to thereby enhance the speed of first access to the memory macro structures. Namely, each memory bank is made to function as a sense amplifier cache. To enhance the hit ratio of such a sense amplifier cache more greatly, an access controller self-prefetches the next address (an address to which a predetermined offset has been added) after access to a memory macro structure so that data in the self-prefetched address are preread by a sense amplifier in another memory bank.
摘要翻译：为了提高第一次访问的速度（从先前访问的字线读取访问）到多存储体存储器，使用多存储体存储器宏结构。数据保存在每个存储体的读出放大器中。当对保持的数据进行访问时，输出由读出放大器锁存的数据，从而提高对存储器宏结构的首次访问的速度。即，使每个存储体用作读出放大器高速缓存。为了更好地提高这种感测放大器高速缓存的命中率，访问控制器在访问存储器宏结构之后自我预取下一个地址（已经添加了预定偏移量的地址），以便自我预取中的数据地址由另一个存储体中的读出放大器预读。

4. 发明授权

US08063691B2 Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件
公开(公告)号：US08063691B2
公开(公告)日：2011-11-22
申请号：US13020169
申请日：2011-02-03
申请人： Hiroyuki Mizuno , Yusuke Kanno , Kazumasa Yanagisawa , Yoshihiko Yasu , Nobuhiro Oodaira
发明人： Hiroyuki Mizuno , Yusuke Kanno , Kazumasa Yanagisawa , Yoshihiko Yasu , Nobuhiro Oodaira
IPC分类号： H03L5/00
CPC分类号： H03K19/0016 , H01L23/5286 , H01L27/0207 , H01L27/092 , H01L27/0928 , H01L27/11898 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A semiconductor integrated circuit device provided with a first circuit block BLK1, a second circuit block DRV1 and a conversion circuit MIO1 for connecting the first circuit block to the second circuit block. The first circuit block includes a first mode for applying a supply voltage and a second mode for shutting off the supply voltage. The conversion circuit is provided with a function for maintaining the potential of an input node of the second circuit block at an operation potential, thereby suppressing a penetrating current flow when the first circuit block is in the second mode. The conversion circuit (MIO1 to MIO4) are commonly used for connecting circuit blocks.
摘要翻译：具有第一电路块BLK1，第二电路块DRV1和用于将第一电路块连接到第二电路块的转换电路MIO1的半导体集成电路器件。第一电路块包括用于施加电源电压的第一模式和用于关断电源电压的第二模式。转换电路具有将第二电路块的输入节点的电位维持在操作电位的功能，从而当第一电路块处于第二模式时抑制穿透电流流动。转换电路（MIO1〜MIO4）通常用于连接电路块。

5. 发明申请

US20060091942A1 Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件
公开(公告)号：US20060091942A1
公开(公告)日：2006-05-04
申请号：US11296442
申请日：2005-12-08
申请人： Hiroyuki Mizuno , Yusuke Kanno , Kazumasa Yanagisawa , Yoshihiko Yasu , Nobuhiro Oodaira
发明人： Hiroyuki Mizuno , Yusuke Kanno , Kazumasa Yanagisawa , Yoshihiko Yasu , Nobuhiro Oodaira
IPC分类号： H01L25/00
CPC分类号： H03K19/0016 , H01L23/5286 , H01L27/0207 , H01L27/092 , H01L27/0928 , H01L27/11898 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A semiconductor integrated circuit device provided with a first circuit block BLK1, a second circuit block DRV1 and a conversion circuit MIO1 for connecting the first circuit block to the second circuit block. The first circuit block includes a first mode for applying a supply voltage and a second mode for shutting off the supply voltage. The conversion circuit is provided with a function for maintaining the potential of an input node of the second circuit block at an operation potential, thereby suppressing a penetrating current flow when the first circuit block is in the second mode. The conversion circuit (MIO1 to MIO4) are commonly used for connecting circuit blocks.
摘要翻译：具有第一电路块BLK1，第二电路块DRV1和用于将第一电路块连接到第二电路块的转换电路MIO 1的半导体集成电路器件。第一电路块包括用于施加电源电压的第一模式和用于关断电源电压的第二模式。转换电路具有将第二电路块的输入节点的电位维持在操作电位的功能，从而当第一电路块处于第二模式时抑制穿透电流流动。转换电路（MIO 1〜MIO 4）通常用于连接电路块。

6. 发明授权

US06985022B2 Semiconductor device 失效
公开(公告)号：US06985022B2
公开(公告)日：2006-01-10
申请号：US10757593
申请日：2004-01-15
申请人： Yusuke Kanno , Hiroyuki Mizuno , Kazumasa Yanagisawa
发明人： Yusuke Kanno , Hiroyuki Mizuno , Kazumasa Yanagisawa
IPC分类号： H03L5/00
CPC分类号： H03K5/1534 , H03K3/356113 , H03K19/018521
摘要： A semiconductor device includes a differential level converter circuit that receives a first signal and outputs a second signal of greater amplitude. The differential level converter has a first MISFET pair for receiving the first signal, a second MISFET pair for enhancing the withstand voltage of the first MISFET pair, and a third MISFET pair with cross-coupled gates for latching the second signal from output. The film thickness of the gate insulating films of the second and third MISFET pairs is made thicker than that of the first MISFET pair, and the threshold voltages of the first and second MISFET pairs are made smaller than that of the third MISFET pair. This level converter circuit operates at high speed even if there is a large difference in the signal amplitude before and after level conversion.

7. 发明授权

US06888395B2 Semiconductor integrated circuit device 有权
公开(公告)号：US06888395B2
公开(公告)日：2005-05-03
申请号：US10351320
申请日：2003-01-27
申请人： Hiroyuki Mizuno , Yusuke Kanno , Kazumasa Yanagisawa , Yoshihiko Yasu , Nobuhiro Oodaira
发明人： Hiroyuki Mizuno , Yusuke Kanno , Kazumasa Yanagisawa , Yoshihiko Yasu , Nobuhiro Oodaira
IPC分类号： H01L27/04 , H01L21/82 , H01L21/822 , H01L23/528 , H01L27/092 , H03K19/00 , H03K19/0944 , H03L5/00
CPC分类号： H03K19/0016 , H01L23/5286 , H01L27/0207 , H01L27/092 , H01L27/0928 , H01L27/11898 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A semiconductor integrated circuit device provided with a first circuit block BLK1, a second circuit block DRV1 and a conversion circuit MIO1 for connecting the first circuit block to the second circuit block. The first circuit block includes a first mode for applying a supply voltage and a second mode for shutting off the supply voltage. The conversion circuit is provided with a function for maintaining the potential of an input node of the second circuit block at an operation potential, thereby suppressing a penetrating current flow when the first circuit block is in the second mode. The conversion circuit (MIO1 to MIO4) are commonly used for connecting circuit blocks.

8. 发明申请

US20050285659A1 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US20050285659A1
公开(公告)日：2005-12-29
申请号：US11202279
申请日：2005-08-12
申请人： Yusuke Kanno , Hiroyuki Mizuno , Kazumasa Yanagisawa
发明人： Yusuke Kanno , Hiroyuki Mizuno , Kazumasa Yanagisawa
IPC分类号： H01L21/822 , H01L21/82 , H01L21/8234 , H01L27/04 , H01L27/088 , H03K3/356 , H03K5/1534 , H03K19/0175 , H03K19/0185
CPC分类号： H03K5/1534 , H03K3/356113 , H03K19/018521
摘要： A semiconductor device includes a differential level converter circuit that receives a first signal and outputs a second signal of greater amplitude. The differential level converter has a first MISFET pair for receiving the first signal, a second MISFET pair for enhancing the withstand voltage of the first MISFET pair, and a third MISFET pair with cross-coupled gates for latching the second signal from output. The film thickness of the gate insulating films of the second and third MISFET pairs is made thicker than that of the first MISFET pair, and the threshold voltages of the first and second MISFET pairs are made smaller than that of the third MISFET pair. This level converter circuit operates at high speed even if there is a large difference in the signal amplitude before and after level conversion.
摘要翻译：半导体器件包括差分电平转换器电路，其接收第一信号并输出更大振幅的第二信号。差分电平转换器具有用于接收第一信号的第一MISFET对，用于增强第一MISFET对的耐受电压的第二MISFET对以及具有用于锁存来自输出的第二信号的交叉耦合门的第三MISFET对。使第二MISFET对和第三MISFET对的栅极绝缘膜的膜厚比第一MISFET对的膜厚薄，并且使第一MISFET对和第二MISFET对的阈值电压小于第三MISFET对的阈值电压。即使在电平转换之前和之后的信号幅度有较大的差异，该电平转换器电路也以高速工作。

9. 发明申请

US20050146953A1 Semiconductor integrated circuit device 审中-公开
标题翻译：半导体集成电路器件
公开(公告)号：US20050146953A1
公开(公告)日：2005-07-07
申请号：US11040033
申请日：2005-01-24
申请人： Hiroyuki Mizuno , Yusuke Kanno , Kazumasa Yanagisawa , Yoshihiko Yasu , Nobuhiro Oodaira
发明人： Hiroyuki Mizuno , Yusuke Kanno , Kazumasa Yanagisawa , Yoshihiko Yasu , Nobuhiro Oodaira
IPC分类号： H01L27/04 , H01L21/82 , H01L21/822 , H01L23/528 , H01L27/092 , H03K19/00 , H03K19/0944 , G11C7/00
CPC分类号： H03K19/0016 , H01L23/5286 , H01L27/0207 , H01L27/092 , H01L27/0928 , H01L27/11898 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A semiconductor integrated circuit device provided with a first circuit block BLK1, a second circuit block DRV1 and a conversion circuit MIO1 for connecting the first circuit block to the second circuit block. The first circuit block includes a first mode for applying a supply voltage and a second mode for shutting off the supply voltage. The conversion circuit is provided with a function for maintaining the potential of an input node of the second circuit block at an operation potential, thereby suppressing a penetrating current flow when the first circuit block is in the second mode. The conversion circuit (MIO1 to MIO4) are commonly used for connecting circuit blocks.
摘要翻译：具有第一电路块BLK1，第二电路块DRV1和用于将第一电路块连接到第二电路块的转换电路MIO 1的半导体集成电路器件。第一电路块包括用于施加电源电压的第一模式和用于关断电源电压的第二模式。转换电路具有将第二电路块的输入节点的电位维持在操作电位的功能，从而当第一电路块处于第二模式时抑制穿透电流流动。转换电路（MIO 1〜MIO 4）通常用于连接电路块。

10. 发明授权

US07375574B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US07375574B2
公开(公告)日：2008-05-20
申请号：US11202279
申请日：2005-08-12
申请人： Yusuke Kanno , Hiroyuki Mizuno , Kazumasa Yanagisawa
发明人： Yusuke Kanno , Hiroyuki Mizuno , Kazumasa Yanagisawa
IPC分类号： H03L5/00
CPC分类号： H03K5/1534 , H03K3/356113 , H03K19/018521
摘要： A semiconductor device includes a differential level converter circuit that receives a first signal and outputs a second signal of greater amplitude. The differential level converter has a first MISFET pair for receiving the first signal, a second MISFET pair for enhancing the withstand voltage of the first MISFET pair, and a third MISFET pair with cross-coupled gates for latching the second signal from output. The film thickness of the gate insulating films of the second and third MISFET pairs is made thicker than that of the first MISFET pair, and the threshold voltages of the first and second MISFET pairs are made smaller than that of the third MISFET pair. This level converter circuit operates at high speed even if there is a large difference in the signal amplitude before and after level conversion.
摘要翻译：半导体器件包括差分电平转换器电路，其接收第一信号并输出更大振幅的第二信号。差分电平转换器具有用于接收第一信号的第一MISFET对，用于增强第一MISFET对的耐受电压的第二MISFET对以及具有用于锁存来自输出的第二信号的交叉耦合门的第三MISFET对。使第二MISFET对和第三MISFET对的栅极绝缘膜的膜厚比第一MISFET对的膜厚薄，并且使第一MISFET对和第二MISFET对的阈值电压小于第三MISFET对的阈值电压。即使在电平转换之前和之后的信号幅度有较大的差异，该电平转换器电路也以高速工作。

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