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1. 发明申请

US20100301893A1 SEMICONDUCTOR INTEGRATED CIRCUIT AND CIRCUIT OPERATION METHOD 失效
标题翻译：半导体集成电路和电路操作方法
公开(公告)号：US20100301893A1
公开(公告)日：2010-12-02
申请号：US12787090
申请日：2010-05-25
申请人： Kazuo OTSUGA , Yusuke Kanno
发明人： Kazuo OTSUGA , Yusuke Kanno
IPC分类号： G01R31/26
CPC分类号： G01R31/31721
摘要： In a semiconductor integrated circuit wherein low-threshold-voltage and high-threshold-voltage transistors are disposed mixedly, the operating speed of each transistor can be properly controlled in speed control execution through regulation of a power supply voltage VDD. The semiconductor integrated circuit comprises an internal circuit and measuring circuits. The internal circuit comprises a low-threshold-voltage MOS transistor and a high-threshold-voltage MOS transistor, and the degree of threshold voltage variation of the low-threshold-voltage MOS transistor is larger than the degree of threshold voltage variation of the high-threshold-voltage MOS transistor. The measuring circuit detects which one of fast, typical, and slow states is taken by both the low-threshold-voltage MOS transistor and the high-threshold-voltage MOS transistor. When the result data detected indicates the fast state, the power supply voltage VDD is set to a lower power supply voltage level “VDD−ΔVDD” corresponding to a small variation gradient “β[V/σ]”. When the result data detected indicates the typical state, the power supply voltage VDD is set to an intermediate power supply voltage level “VDD±0”. When the result data detected indicates the slow state, the power supply voltage VDD is set to a higher power supply voltage level “VDD+ΔVDD” corresponding to a large variation gradient “α[V/σ]”.
摘要翻译：在其中低阈值电压和高阈值电压晶体管被混合地布置的半导体集成电路中，通过调节电源电压VDD可以在速度控制执行中适当地控制每个晶体管的工作速度。半导体集成电路包括内部电路和测量电路。内部电路包括低阈值电压MOS晶体管和高阈值电压MOS晶体管，并且低阈值电压MOS晶体管的阈值电压变化程度大于高阈值电压MOS晶体管的阈值电压变化的程度阈值电压MOS晶体管。测量电路检测低阈值电压MOS晶体管和高阈值电压MOS晶体管中的哪一个快速，典型和慢速状态。当检测到的结果数据指示快速状态时，电源电压VDD被设置为对应于小变化梯度“＆bgr; [V /＆sgr]]的较低电源电压电平”VDD-＆Dgr; VDD“。当检测到的结果数据表示典型状态时，将电源电压VDD设定为中间电源电压电平“VDD±0”。当检测到的结果数据表示慢速状态时，将电源电压VDD设定为与较大变化梯度“α[V /＆sgr”]对应的较高电源电压电平“VDD +＆Dgr; VDD”。

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