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61. 发明授权

US06399446B1 Process for fabricating high density memory cells using a metallic hard mask 有权
标题翻译：使用金属硬掩模制造高密度记忆单元的方法
公开(公告)号：US06399446B1
公开(公告)日：2002-06-04
申请号：US09429722
申请日：1999-10-29
申请人： Bharath Rangarajan , David K. Foote , Fei Wang , Dawn M. Hopper , Stephen K. Park , Jack Thomas , Mark Chang , Mark Ramsbey
发明人： Bharath Rangarajan , David K. Foote , Fei Wang , Dawn M. Hopper , Stephen K. Park , Jack Thomas , Mark Chang , Mark Ramsbey
IPC分类号： H01L218247
CPC分类号： H01L27/11568 , H01L27/115 , Y10S438/945
摘要： A process for fabricating a memory cell in a two-bit EEPROM device including forming an ONO layer overlying a semiconductor substrate, depositing a hard mask overlying the ONO layer, and patterning the hard mask. The hard mask is made from tungsten, titanium, or titanium nitride. The process further includes doping the semiconductor substrate with boron causing p-type regions to form in the semiconductor substrate, and doping the semiconductor substrate with n-type dopants, such as arsenic, causing n-type regions to form in the semiconductor substrate. The exposed ONO layer is then etched to expose part of the semiconductor substrate, and a bit-line oxide region is formed overlying the semiconductor substrate. The hard mask is then stripped, preferably using an H2O2 solution.
摘要翻译：一种用于在二位EEPROM器件中制造存储单元的方法，包括形成覆盖在半导体衬底上的ONO层，沉积覆盖在ONO层上的硬掩模，以及对该硬掩模进行构图。硬掩模由钨，钛或氮化钛制成。该工艺还包括用硼掺杂导致在半导体衬底中形成p型区域的半导体衬底，并且用诸如砷的n型掺杂剂掺杂半导体衬底，从而在半导体衬底中形成n型区域。然后对暴露的ONO层进行蚀刻以暴露半导体衬底的一部分，并且在半导体衬底上形成位线氧化物区域。然后将硬掩模剥离，优选使用H 2 O 2溶液。

62. 发明授权

US06365505B1 Method of making a slot via filled dual damascene structure with middle stop layer 有权
标题翻译：通过具有中间停止层的填充双镶嵌结构制作槽的方法
公开(公告)号：US06365505B1
公开(公告)日：2002-04-02
申请号：US09780531
申请日：2001-02-21
申请人： Fei Wang , Lynne A. Okada , Ramkumar Subramanian , Calvin T. Gabriel
发明人： Fei Wang , Lynne A. Okada , Ramkumar Subramanian , Calvin T. Gabriel
IPC分类号： H01L214763
CPC分类号： H01L21/76835 , H01L21/76808
摘要： A method of forming an interconnect structure in which an inorganic low k dielectric material is deposited over a conductive layer to form a first dielectric layer. An etch stop layer is formed on the first dielectric layer. The etch stop layer and the first dielectric layer are etched to form a slot via in the first dielectric layer. The slot via is longer than the width of a subsequently formed trench. An organic low k dielectric material is deposited within the slot via and over the etch stop layer to form a second dielectric layer over the slot via and the etch stop layer. The re-filled slot via is simultaneously etched with the second dielectric layer in which a trench is formed. The entire width of the trench is directly over the via. The re-opened via and the trench are filled with a conductive material.
摘要翻译：一种形成互连结构的方法，其中无机低k电介质材料沉积在导电层上以形成第一介电层。在第一电介质层上形成蚀刻停止层。蚀刻停止层和第一介电层被蚀刻以在第一介电层中形成槽通孔。狭缝通孔比随后形成的沟槽的宽度长。有机低k电介质材料通过蚀刻停止层上方和上方沉积在槽内，以在缝隙通孔和蚀刻停止层上形成第二电介质层。再填充的槽通孔与其中形成沟槽的第二电介质层同时蚀刻。沟槽的整个宽度直接在通孔上方。重新打开的通孔和沟槽填充有导电材料。

63. 发明授权

US06319834B1 Method and apparatus for improved planarity metallization by electroplating and CMP 有权
标题翻译：通过电镀和CMP改善平面度金属化的方法和装置
公开(公告)号：US06319834B1
公开(公告)日：2001-11-20
申请号：US09639812
申请日：2000-08-17
申请人： Darrell M. Erb , Steven C. Avanzino , Fei Wang
发明人： Darrell M. Erb , Steven C. Avanzino , Fei Wang
IPC分类号： H01L2144
CPC分类号： H01L21/3212 , H01L21/2885 , H01L21/7684 , H01L21/76877 , H01L21/76879
摘要： A pattern of in-laid conductors is formed by a method utilizing electroplating and chemical-mechanical polishing (CMP). Embodiments include a first step of selectively filling recesses formed in the surface of a substrate with a metal by localized electroplating at a reduced thickness, planar-surfaced overburden or blanket layer thereon, and planarizing the surface by CMP utilizing a relatively soft CMP pad. Embodiments also include an apparatus comprising a porous pad applicator for selectively electroplating recesses formed in the surface of a workpiece.
摘要翻译：通过使用电镀和化学机械抛光（CMP）的方法形成嵌入导体的图案。实施例包括第一步骤，通过局部电镀在其上以薄的局部电镀，平面表面覆盖层或覆盖层选择性地填充形成在衬底的表面中的凹陷，并且通过使用相对较软的CMP衬垫的CMP来平坦化表面。实施例还包括一种包括用于选择性地电镀在工件表面中形成的凹槽的多孔垫施加器的装置。

64. 发明授权

US06313018B1 Process for fabricating semiconductor device including antireflective etch stop layer 有权
标题翻译：用于制造包括抗反射蚀刻停止层的半导体器件的工艺
公开(公告)号：US06313018B1
公开(公告)日：2001-11-06
申请号：US09504449
申请日：2000-02-16
申请人： Fei Wang , David K. Foote , Myron R. Cagan , Subhash Gupta
发明人： Fei Wang , David K. Foote , Myron R. Cagan , Subhash Gupta
IPC分类号： H01L2120
CPC分类号： H01L21/0214 , H01L21/02126 , H01L21/02129 , H01L21/02164 , H01L21/0217 , H01L21/02274 , H01L21/0276 , H01L21/3121 , H01L21/3144 , H01L21/3145 , H01L21/76802 , H01L21/76834 , H01L21/76895 , H01L21/76897 , H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： A microelectronic device such as a Metal-Oxide-Semiconductor (MOS) transistor is formed on a semiconductor substrate. A tungsten damascene interconnect for the device is formed using an etch stop layer of silicon nitride, silicon oxynitride or silicon oxime having a high silicon content of approximately 40% to 50% by weight. The etch stop layer has high etch selectivity relative to overlying insulator materials such as silicon dioxide, tetraethylorthosilicate (TEOS) glass and borophosphosilicate glass (BPSG). The etch stop layer also has a high index of refraction and is anti-reflective, thereby improving critical dimension control during photolithographic imaging.
摘要翻译：在半导体衬底上形成诸如金属氧化物半导体（MOS）晶体管的微电子器件。用于器件的钨镶嵌互连使用具有大约40％至50％重量的硅含量的氮化硅，氮氧化硅或硅肟的蚀刻停止层形成。蚀刻停止层相对于上覆绝缘体材料如二氧化硅，原硅酸四乙酯（TEOS）玻璃和硼磷硅酸盐玻璃（BPSG）具有高蚀刻选择性。蚀刻停止层还具有高折射率并且是抗反射性的，从而改善光刻成像期间的临界尺寸控制。

65. 发明授权

US06297167B1 In-situ etch of multiple layers during formation of local interconnects 失效
标题翻译：在局部互连形成期间原位蚀刻多层
公开(公告)号：US06297167B1
公开(公告)日：2001-10-02
申请号：US08924574
申请日：1997-09-05
申请人： Fei Wang , James K. Kai , William G. En
发明人： Fei Wang , James K. Kai , William G. En
IPC分类号： H01L21027
CPC分类号： H01L21/31116 , H01L21/76802 , H01L21/76895
摘要： An in-situ etching process for creating local interconnects in a semiconductor device includes using a single etching tool to: etch through a masked dielectric layer to a stop layer using a mixture of C4F8/CH3F/Ar gasses; etch away the mask layer using a mixture of O2/Ar gasses; and etch through the stop layer using a mixture of CH3F/O2 gasses. The semiconductor device is not removed from the etching tool between the different etchings. The method then includes depositing conductive material to form local interconnects within the openings that were etched.
摘要翻译：用于在半导体器件中产生局部互连的原位蚀刻工艺包括使用单个蚀刻工具：使用C4F8 / CH3F / Ar气体的混合物将掩模的介电层蚀刻到停止层; 使用O 2 / Ar气体的混合物蚀刻掩模层; 并使用CH3F / O2气体的混合物蚀刻通过停止层。在不同蚀刻之间，半导体器件不会从蚀刻工具中移除。该方法然后包括沉积导电材料以在被蚀刻的开口内形成局部互连。

66. 发明授权

US06235628B1 Method of forming dual damascene arrangement for metal interconnection with low k dielectric constant materials and oxide middle etch stop layer 有权
标题翻译：形成用于具有低k介电常数材料和氧化物中间蚀刻停止层的金属互连的双镶嵌布置的方法
公开(公告)号：US06235628B1
公开(公告)日：2001-05-22
申请号：US09225545
申请日：1999-01-05
申请人： Fei Wang , Jerry Cheng
发明人： Fei Wang , Jerry Cheng
IPC分类号： H01L214763
CPC分类号： H01L21/76835 , H01L21/76807
摘要： A method of forming a dual damascene structure in a semiconductor device arrangement forms a first low k dielectric material over an underlying metal interconnect layer, such as a copper interconnect layer. An oxide etch stop layer is formed on the first low k dielectric layer, and a second low k dielectric layer is formed on the oxide etch stop layer. A via is etched into the first low k dielectric layer, and a trench is then etched into the second low k dielectric layer. The first and second low k dielectric materials are different from one another so that they have different sensitivity to at least one etchant chemistry. Undercutting in the first dielectric layer is thereby prevented during the etching of the trench in the second dielectric layer by employing an etch chemistry that etches only the second low k dielectric material and not the first low k dielectric material.
摘要翻译：在半导体器件布置中形成双镶嵌结构的方法在下面的金属互连层（例如铜互连层）上形成第一低k电介质材料。在第一低k电介质层上形成氧化物蚀刻停止层，在氧化物蚀刻停止层上形成第二低k电介质层。将通孔蚀刻到第一低k电介质层中，然后将沟槽蚀刻到第二低k电介质层中。第一和第二低k电介质材料彼此不同，使得它们对至少一种蚀刻剂化学物质具有不同的灵敏度。因此，在蚀刻第二介质层中沟槽的过程中，通过采用只刻蚀第二低k电介质材料而不是第一低k电介质材料的蚀刻化学法来防止第一介质层中的底切。

67. 发明授权

US06211071B1 Optimized trench/via profile for damascene filling 有权
标题翻译：用于镶嵌填料的优化沟槽/通孔型材
公开(公告)号：US06211071B1
公开(公告)日：2001-04-03
申请号：US09296552
申请日：1999-04-22
申请人： Todd P. Lukanc , Fei Wang , Steven C. Avanzino
发明人： Todd P. Lukanc , Fei Wang , Steven C. Avanzino
IPC分类号： H01L214763
CPC分类号： H01L21/76873 , H01L21/2885 , H01L21/31133 , H01L21/76804 , H01L21/76829 , H01L21/76831 , H01L21/76843 , H01L21/76877
摘要： In-laid metallization patterns, e.g., of copper or copper alloy, are formed in the surface of a dielectric layer with significantly improve reliability by voidlessly filling recesses formed in the dielectric layer surface by electroplating. Embodiments include preventing “pinching-off” of the recess opening due to overhanging nucleation/seed layer deposits at the corners of the opening as a result of localized increased rates of deposition. Further embodiments include providing a dual-layered dielectric layer comprising different dielectric materials and performing a first, isotropic etching process of the upper lamina of the dielectric layer for selectively tapering the width of the recess mouth opening to provide a wider opening at the substrate surface, followed by a second, anisotropic etching process for extending the recess at a substantially constant width for a predetermined depth into the lower lamina of the dielectric layer. The tapered width profile of the recess effectively prevents formation of overhanging deposits thereat which can result in occlusion and void formation during electroplating for filling the recesses.
摘要翻译：在电介质层的表面形成例如铜或铜合金的成网金属化图案，通过电镀无孔地填充形成在电介质层表面的凹槽，从而显着提高可靠性。实施例包括由于局部增加的沉积速率而导致由于在开口的角部处的悬垂成核/种子层沉积而导致的凹陷开口的“夹断”。另外的实施例包括提供包括不同介电材料的双层电介质层，并执行电介质层的上层的第一，各向同性蚀刻工艺，用于选择性地使凹口开口的宽度变窄，以在衬底表面提供更宽的开口，随后进行第二种各向异性蚀刻工艺，用于将凹槽以基本上恒定的宽度延伸到介电层的下层中的预定深度。凹陷的锥形宽度轮廓有效地防止了在其中形成悬垂沉积物，这可能导致电镀期间的闭塞和空隙形成以填充凹部。

68. 发明授权

US6156658A Ultra-thin resist and silicon/oxide hard mask for metal etch 有权
标题翻译：用于金属蚀刻的超薄抗蚀剂和硅/氧化物硬掩模
公开(公告)号：US6156658A
公开(公告)日：2000-12-05
申请号：US203774
申请日：1998-12-02
申请人： Fei Wang , Christopher F. Lyons , Khanh B. Nguyen , Scott A. Bell , Harry J. Levinson , Chih Yuh Yang
发明人： Fei Wang , Christopher F. Lyons , Khanh B. Nguyen , Scott A. Bell , Harry J. Levinson , Chih Yuh Yang
IPC分类号： H01L21/027 , H01L21/3213 , H01L21/44 , H01L21/302 , H01L21/461
CPC分类号： H01L21/32139 , H01L21/0274 , H01L21/32136
摘要： In one embodiment, the present invention relates to a method of forming a metal line, involving the steps of providing a semiconductor substrate comprising a metal layer, an oxide layer over the metal layer, and a silicon layer over the oxide layer; depositing an ultra-thin photoresist over the silicon layer, the ultra-thin photoresist having a thickness less than about 2,000 .ANG.; irradiating the ultra-thin photoresist with electromagnetic radiation having a wavelength of about 250 nm or less; developing the ultra-thin photoresist exposing a portion of the silicon layer; etching the exposed portion of the silicon layer exposing a portion of the oxide layer; etching the exposed portion of the oxide layer exposing a portion of the metal layer; and etching the exposed portion of the metal layer thereby forming the metal line.
摘要翻译：在一个实施例中，本发明涉及一种形成金属线的方法，包括以下步骤：提供包括金属层的半导体衬底，金属层上的氧化物层和氧化物层上的硅层; 在硅层上沉积超薄光致抗蚀剂，超薄光致抗蚀剂的厚度小于约2,000安培; 用波长约250nm或更小的电磁辐射照射超薄光致抗蚀剂; 开发暴露一部分硅层的超薄光刻胶; 蚀刻暴露出氧化物层的一部分的硅层的暴露部分; 蚀刻暴露出金属层的一部分的氧化物层的暴露部分; 并且蚀刻金属层的暴露部分从而形成金属线。

69. 发明授权

US6117782A Optimized trench/via profile for damascene filling 有权
标题翻译：用于镶嵌填料的优化沟槽/通孔型材
公开(公告)号：US6117782A
公开(公告)日：2000-09-12
申请号：US296556
申请日：1999-04-22
申请人： Todd P. Lukanc , Fei Wang , Steven C. Avanzino
发明人： Todd P. Lukanc , Fei Wang , Steven C. Avanzino
IPC分类号： H01L21/768 , H01L21/00
CPC分类号： H01L21/76873 , H01L21/76804 , H01L21/7684 , H01L21/76843 , H01L21/7688
摘要： In-laid metallization patterns, e.g., of copper or copper alloy, are formed in the surface of a dielectric layer with significantly improved reliability by voidlessly filling recesses formed in the dielectric layer surface by electroplating. Embodiments include preventing "pinching-off" of the recess opening due overhanging nucleation/seed layer deposits at the corners of the opening as a result of localized increased rates of deposition. Embodiments also include providing a dual-layered dielectric layer comprising different dielectric materials and performing a first, isotropic etching process of the upper (sacrificial) lamina of the dielectric layer for selectively tapering the width of the recess mouth opening to provide a wider opening at the substrate surface, followed by a second, anisotropic etching process for extending the recess at a substantially constant width for a predetermined depth into the lower lamina of the dielectric layer. The tapered width profile of the recess effectively prevents formation of overhanging deposits thereat which can result in occlusion and void formation during electroplating for filling the recesses. After electroplating, the recess-filled, plated surface is subjected to planarization processing, as by CMP, wherein the entire thickness of the second, upper lamina of the dielectric layer is removed.
摘要翻译：在电介质层的表面上形成例如铜或铜合金的嵌入式金属化图案，通过电镀无孔地填充在电介质层表面中形成的凹槽，从而显着提高了可靠性。实施例包括由于局部增加的沉积速率，在开口的角部处由于突出的成核/种子层沉积而阻止凹口的“夹断”。实施例还包括提供包括不同电介质材料的双层电介质层，并且执行电介质层的上（牺牲）层的第一，各向同性蚀刻工艺，用于选择性地使凹口开口的宽度变窄，从而在衬底表面，随后进行第二种各向异性蚀刻工艺，用于以基本上恒定的宽度将凹槽延伸到介电层的下层中的预定深度。凹陷的锥形宽度轮廓有效地防止了在其中形成悬垂沉积物，这可能导致电镀期间的闭塞和空隙形成以填充凹部。在电镀之后，通过CMP对凹陷填充的镀覆表面进行平坦化处理，其中去除介电层的第二上层的整个厚度。

70. 发明授权

US6107208A Nitride etch using N.sub.2 /Ar/CHF.sub.3 chemistry 失效
标题翻译：氮化物蚀刻使用N2 / Ar / CHF3化学
公开(公告)号：US6107208A
公开(公告)日：2000-08-22
申请号：US90670
申请日：1998-06-04
申请人： Jerry Cheng , Fei Wang
发明人： Jerry Cheng , Fei Wang
IPC分类号： H01L21/311 , H01L21/768 , H01L23/532 , H01L21/05
CPC分类号： H01L21/76802 , H01L21/31116 , H01L21/76829 , H01L23/53233 , H01L23/53238 , H01L2924/0002
摘要： In one embodiment, the present invention relates to a method of etching silicon nitride disposed over a copper containing layer by etching at least a portion of the silicon nitride using a nitride etch gas mixture comprising from about 5 sccm to about 15 sccm of CHF.sub.3, about 5 sccm to about 15 sccm of nitrogen and about 80 sccm to about 120 sccm of a carrier gas. In another embodiment, the present invention relates to a method of processing a semiconductor substrate comprising silicon nitride disposed over a copper containing layer, involving etching at least a portion of the silicon nitride using a nitride etch gas mixture comprising CHF.sub.3, nitrogen and Ar.
摘要翻译：在一个实施例中，本发明涉及一种通过使用包含约5sccm至约15sccm的CHF 3的氮化物蚀刻气体混合物蚀刻至少一部分氮化硅而蚀刻设置在含铜层上方的氮化硅的方法，约 5sccm至约15sccm的氮气和约80sccm至约120sccm的载气。在另一个实施例中，本发明涉及一种处理半导体衬底的方法，该半导体衬底包括设置在含铜层上的氮化硅，包括使用包含CHF 3，氮和Ar的氮化物蚀刻气体混合物蚀刻至少一部分氮化硅。

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