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61. 发明授权

US06204689B1 Input/output interconnect circuit for FPGAs 有权
标题翻译： FPGA的输入/输出互连电路
公开(公告)号：US06204689B1
公开(公告)日：2001-03-20
申请号：US09321513
申请日：1999-05-27
申请人： Andrew K. Percey , Trevor J. Bauer , Steven P. Young
发明人： Andrew K. Percey , Trevor J. Bauer , Steven P. Young
IPC分类号： H01L2500
CPC分类号： H03K19/1737 , H03K19/17704 , H03K19/17736 , H03K19/17796
摘要： An input/output interconnect (IOI) circuit is provided for coupling input/output (IO) blocks to an array of configurable logic tiles in a field programmable gate array (FPGA). Each of the tiles includes a configurable logic block and a programmable interconnect structure that includes a plurality of intermediate-length buses. The intermediate-length buses are staggered, such that only a subset of the intermediate-length buses routed by a logic block is connected to the logic block. The IOI circuit includes routing circuits at the perimeter of the array for terminating the intermediate-length buses. In one embodiment, the routing circuits connect various ends of unidirectional intermediate-length buses in a U-turn configuration, thereby making use of all of the intermediate-length buses, and maintaining a regular pattern of intermediate-length buses in the tiles. In another embodiment, various ends of bi-directional intermediate-length buses are terminated to long lines through programmable interconnection points (PIPs). In another embodiment, PIPs are provided to enable horizontal long lines to be connected to horizontal intermediate-length buses, which in turn, can be connected to vertical long lines, thereby providing a low-skew, high fanout routing network.
摘要翻译：提供输入/输出互连（IOI）电路用于将输入/输出（IO）块耦合到现场可编程门阵列（FPGA）中的可配置逻辑块阵列。每个瓦片包括可配置逻辑块和包括多个中长度总线的可编程互连结构。中间长度总线是交错的，使得只有由逻辑块路由的中间长度总线的子集连接到逻辑块。 IOI电路包括用于终止中长度总线的阵列周边的路由电路。在一个实施例中，路由电路将单向中长度总线的各端连接在U形结构中，从而利用所有的中长度总线，并在瓦片中保持中长度总线的规则图案。在另一个实施例中，双向中间长度总线的各个端点通过可编程互连点（PIP）终止于长行。在另一个实施例中，提供PIP以使得水平长线能够连接到水平中间长度总线，其又可以连接到垂直长线，从而提供低偏移，高扇出路由网络。

62. 发明授权

US06201410B1 Wide logic gate implemented in an FPGA configurable logic element 有权
标题翻译：宽逻辑门在FPGA可配置逻辑元件中实现
公开(公告)号：US06201410B1
公开(公告)日：2001-03-13
申请号：US09374470
申请日：1999-08-13
申请人： Bernard J. New , Steven P. Young , Shekhar Bapat , Kamal Chaudhary , Trevor J. Bauer , Roman Iwanczuk
发明人： Bernard J. New , Steven P. Young , Shekhar Bapat , Kamal Chaudhary , Trevor J. Bauer , Roman Iwanczuk
IPC分类号： H01L2500
CPC分类号： H03K19/17736 , H03K19/1737 , H03K19/17704 , H03K19/17728 , H03K19/1778
摘要： The invention allows the implementation of common wide logic functions using only two function generators of a field programmable gate array. One embodiment of the invention provides a structure for implementing a wide AND-gate in an FPGA configurable logic element (CLE) or portion thereof that includes no more than two function generators. First and second function generators are configured as AND-gates, the output signals (first and second AND signals) being combined in a 2-to-1 multiplexer controlled by the first AND signal, “0” selecting the first AND signal and “1” selecting the second AND signal. Therefore, a wide AND-gate is provided having a number of input signals equal to the total number of input signals for the two function generators. In another embodiment, a wide OR-gate is provided by configuring the function generators as OR-gates and controlling the multiplexer using the second OR signal.
摘要翻译：本发明允许仅使用现场可编程门阵列的两个函数发生器实现普通的宽逻辑功能。本发明的一个实施例提供了一种用于在FPGA可配置逻辑元件（CLE）或其部分中实现宽的与门的结构，其包括不超过两个功能发生器。第一和第二功能发生器被配置为与门，输出信号（第一和第二AND信号）被组合在由第一AND信号控制的2对1多路复用器中，选择第一AND信号为“0”和“1” “选择第二个AND信号。因此，提供了具有等于两个功能发生器的输入信号的总数的多个输入信号的宽AND门。在另一个实施例中，通过将功能发生器配置为OR门并使用第二OR信号来控制多路复用器来提供宽的或门。

63. 发明授权

US6051992A Configurable logic element with ability to evaluate five and six input functions 有权
标题翻译：可配置逻辑元件，具有评估五个和六个输入功能的能力
公开(公告)号：US6051992A
公开(公告)日：2000-04-18
申请号：US283472
申请日：1999-04-01
申请人： Steven P. Young , Shekhar Bapat , Kamal Chaudhary , Trevor J. Bauer , Roman Iwanczuk
发明人： Steven P. Young , Shekhar Bapat , Kamal Chaudhary , Trevor J. Bauer , Roman Iwanczuk
IPC分类号： H01L25/00 , H03K19/173 , H03K19/177
CPC分类号： H03K19/17728 , H03K19/1737 , H03K19/17704
摘要： The invention provides a Configurable Logic Element (CLE) preferably included in each of an array of identical tiles. A CLE according to the invention has four function generators. The outputs of two function generators are combined with a fifth independent input in a five-input-function multiplexer or function generator to produce an output that can be any function of five inputs, or some functions of up to nine inputs. The outputs of the other two function generators are similarly combined. The outputs of the two five-input-function multiplexers or function generators are then combined with a sixth independent input in a six-input-function multiplexer or function generator. The six-input-function multiplexer or function generator therefore produces an output that can be any function of up to six inputs. Some functions of up to nineteen inputs can also be generated in a single CLE.
摘要翻译：本发明提供了优选地包括在相同瓦片的阵列中的每一个中的可配置逻辑元件（CLE）。根据本发明的CLE具有四个功能发生器。两个功能发生器的输出与五输入功能多路复用器或函数发生器中的第五个独立输入组合，以产生可以是五个输入或多达九个输入的一些功能的输出。其他两个功能发生器的输出类似地组合。然后，两个五输入功能多路复用器或函数发生器的输出与六输入函数多路复用器或函数发生器中的第六个独立输入相组合。因此，六输入功能多路复用器或函数发生器产生的输出可以是多达六个输入的任何功能。也可以在单个CLE中生成多达十九个输入的某些功能。

64. 发明授权

US5844844A FPGA memory element programmably triggered on both clock edges 失效
标题翻译：可编程地在两个时钟沿触发FPGA存储单元
公开(公告)号：US5844844A
公开(公告)日：1998-12-01
申请号：US890951
申请日：1997-07-09
申请人： Trevor J. Bauer , Stephen M. Trimberger , Steven P. Young
发明人： Trevor J. Bauer , Stephen M. Trimberger , Steven P. Young
IPC分类号： G11C11/41 , G11C11/412 , G11C7/00
CPC分类号： G11C11/412 , G11C11/41
摘要： A programmable memory element clocks in new data on both rising and falling edges of the clock, thereby optionally operating at twice the frequency of the distributed clock. The circuit according to the invention comprises two latches, one rising edge triggered and one falling edge triggered. One of these latches, each time the clock changes state, latches in a new value. When configured as a dual-edge flip-flop, the output of the inactive latch is fed forward to drive the output of the memory element. In one embodiment, the outputs of the two latches are multiplexed together and the clock selects the active output. According to a first embodiment of the invention, the memory element is used in an FPGA and can be programmed to function as either a latch or a dual-edge flip-flop. A second embodiment of the invention comprises a third latch. Based on the contents of a configuration memory cell, two of the three latches are selected to form a flip-flop. One such flip-flop is dual-edge, the other is single-edge. Further embodiments incorporate programmable variations of latches and flip-flops responsive to either or both clock edges.
摘要翻译：可编程存储器元件在时钟的上升沿和下降沿的新数据中进行时钟，从而可选地以分布式时钟的两倍的频率工作。根据本发明的电路包括两个锁存器，一个上升沿触发和一个下降沿触发。这些锁存器中的一个，每当时钟改变状态时，锁存一个新的值。当配置为双边沿触发器时，非活动锁存器的输出向前馈送以驱动存储器元件的输出。在一个实施例中，两个锁存器的输出被多路复用在一起，并且时钟选择有效输出。根据本发明的第一实施例，存储器元件在FPGA中使用，并且可以被编程为用作锁存器或双边沿触发器。本发明的第二实施例包括第三锁存器。基于配置存储单元的内容，选择三个锁存器中的两个形成触发器。一个这样的触发器是双边缘的，另一个是单边缘。另外的实施例结合了一个或两个时钟沿的锁存器和触发器的可编程变化。

65. 发明授权

US09002915B1 Circuits for shifting bussed data 有权
标题翻译：用于转换总线数据的电路
公开(公告)号：US09002915B1
公开(公告)日：2015-04-07
申请号：US12417048
申请日：2009-04-02
申请人： Steven P. Young , Brian C. Gaide
发明人： Steven P. Young , Brian C. Gaide
IPC分类号： G06F7/00 , G06F15/00 , G06F5/01
CPC分类号： G06F5/015 , H03K19/17736
摘要： A circuit for shifting bussed data includes a first column of shift blocks, a compare block, and a second column of multiplexer blocks. The first column shifts the bussed data by a number of bits specified by first bits of a shift control input. The compare block determines the value of a second bit of the shift control input and creates an output reflecting that value. The second column has a control input coupled to the output of the compare block, shifts the data by one byte when the second bit of the shift control input has a first value, and does not shift the data when the second bit has a second value. The shift, compare, and multiplexer blocks can be substantially similar logic blocks programmable to perform any of these functions, can include N-bit data inputs and outputs, and can operate on the bussed data as an N-bit bus.
摘要翻译：用于移位总线数据的电路包括第一列移位块，比较块和第二列复用器块。第一列将总线数据移位由移位控制输入的第一位指定的位数。比较块确定移位控制输入的第二位的值，并创建反映该值的输出。第二列具有耦合到比较块的输出的控制输入，当移位控制输入的第二位具有第一值时将数据移位一个字节，并且当第二位具有第二值时不移位数据。移位，比较和多路复用器块可以是基本相似的可编程以执行这些功能的逻辑块，可以包括N位数据输入和输出，并且可以作为N位总线对总线数据进行操作。

66. 发明授权

US07902863B1 Methods and apparatus for device-specific configuration of a programmable integrated circuit 有权
标题翻译：可编程集成电路器件特定配置的方法和装置
公开(公告)号：US07902863B1
公开(公告)日：2011-03-08
申请号：US12049189
申请日：2008-03-14
申请人： David E. Tetzlaff , Daniel J. Ferris, III , Steven P. Young
发明人： David E. Tetzlaff , Daniel J. Ferris, III , Steven P. Young
IPC分类号： H03K19/173
CPC分类号： H03K19/17748 , G06F17/5054
摘要： Methods and apparatus for configuring a programmable integrated circuit are described. In one example, a configuration stream having first data for programming first locations in a configuration memory and an instruction for referencing circuitry in the programmable integrated circuit is received. Second data is obtained from the circuitry based on the instruction. Second locations in the configuration memory are programmed in response to the second data.
摘要翻译：描述用于配置可编程集成电路的方法和装置。在一个示例中，接收具有用于对配置存储器中的第一位置进行编程的第一数据和用于参考可编程集成电路中的电路的指令的配置流。基于该指令的电路获得第二数据。响应于第二数据对配置存储器中的第二位置进行编程。

67. 发明授权

US07895509B1 Error checking parity and syndrome of a block of data with relocated parity bits 有权
标题翻译：错误检查具有重定位奇偶校验位的数据块的奇偶校验和校验
公开(公告)号：US07895509B1
公开(公告)日：2011-02-22
申请号：US12188935
申请日：2008-08-08
申请人： Warren E. Cory , David P. Schultz , Steven P. Young
发明人： Warren E. Cory , David P. Schultz , Steven P. Young
IPC分类号： G06F11/00 , H03M13/00
CPC分类号： H03M13/27 , H03M13/19 , H03M13/45
摘要： Method and apparatus for error checking information is described. Configuration data includes data bits and parity bits. Notably, parity bits may be relocated for determining a syndrome value. Syndrome bits are determined by computing a partial syndrome value for each word serially transmitted of the configuration data, where the configuration data includes one or more data vectors. Location of each word of the configuration data is identified. It is determined whether a partial syndrome value is an initial partial syndrome value or other partial syndrome value responsive to word location. An initial partial syndrome value is stored, and subsequent partial syndrome values are cumulatively added for each word of a data vector to arrive at a syndrome value for the data vector.
摘要翻译：描述了用于错误检查信息的方法和装置。配置数据包括数据位和奇偶校验位。值得注意的是，可以重新定位奇偶校验位以确定校正子值。通过对配置数据的串行发送的每个字计算部分校正子值来确定综合征位，其中配置数据包括一个或多个数据向量。识别配置数据的每个单词的位置。确定部分综合征值是否是初始部分综合征值或响应于词位置的其他部分综合征值。存储初始部分综合征值，并且随后的部分综合征值被累积地添加到数据向量的每个单词以得到数据向量的校正子值。

68. 发明授权

US07746106B1 Circuits for enabling feedback paths in a self-timed integrated circuit 有权
标题翻译：用于在自定时集成电路中启用反馈路径的电路
公开(公告)号：US07746106B1
公开(公告)日：2010-06-29
申请号：US12417040
申请日：2009-04-02
申请人： Brian C. Gaide , Steven P. Young
发明人： Brian C. Gaide , Steven P. Young
IPC分类号： H03K19/173
CPC分类号： H03K19/1736 , H03K19/17728 , H03K19/17736
摘要： Circuits enabling feedback paths in a self-timed integrated circuit. Each of a plurality of interconnected logic blocks includes a logic circuit having first and second outputs, and means for placing, during an initial cycle, a self-timed first data signal on the second output onto a logic block output, and for placing, during subsequent cycles, a self-timed second data signal on a selected one of the first or second outputs onto the logic block output. Initially, an output token is provided only when valid new data is received on the second output and on a select signal. Subsequently, the output token is provided only when either the first output of the logic circuit is selected, and valid new data is received on the first output and on the select signal; or the second output of the logic circuit is selected, and valid new data is received on the first and second outputs and on the select signal.
摘要翻译：在自定时集成电路中实现反馈路径的电路。多个相互连接的逻辑块中的每一个包括具有第一和第二输出的逻辑电路，以及用于在初始周期期间将第二输出上的自定时第一数据信号放置在逻辑块输出上并用于在随后的周期中，在逻辑块输出上的第一或第二输出中的所选择的一个上的自定时第二数据信号。最初，仅当在第二输出和选择信号上接收到有效的新数据时才提供输出令牌。随后，仅当逻辑电路的第一输出被选择并且在第一输出和选择信号上接收到有效的新数据时才提供输出令牌; 或选择逻辑电路的第二输出，并在第一和第二输出和选择信号上接收有效的新数据。

69. 发明授权

US07489152B2 Characterizing circuit performance by separating device and interconnect impact on signal delay 有权
标题翻译：通过分离器件和互连对信号延迟的影响来表征电路性能
公开(公告)号：US07489152B2
公开(公告)日：2009-02-10
申请号：US11498371
申请日：2006-08-03
申请人： Xiao-Jie Yuan , Michael J. Hart , Zicheng G. Ling , Steven P. Young
发明人： Xiao-Jie Yuan , Michael J. Hart , Zicheng G. Ling , Steven P. Young
IPC分类号： G01R31/28
CPC分类号： G01R31/2882 , G01R31/318511 , G01R31/318516 , G01R31/3187
摘要： An integrated circuit (IC) includes multiple embedded test circuits that all include a ring oscillator coupled to a test load. The test load either is a direct short in the ring oscillator or else is a interconnect load that is representative of one of the interconnect layers in the IC. A model equation is defined for each embedded test circuit, with each model equation specifying the output delay of its associated embedded test circuit as a function of Front End OF the Line (FEOL) and Back End Of the Line (BEOL) parameters. The model equations are then solved for the various FEOL and BEOL parameters as functions of the test circuit output delays. Finally, measured output delay values are substituted in to these parameter equations to generate actual values for the various FEOL and BEOL parameters, thereby allowing any areas of concern to be quickly and accurately identified.
摘要翻译：集成电路（IC）包括多个嵌入式测试电路，其中都包括耦合到测试负载的环形振荡器。测试负载在环形振荡器中是直接短路，或者是表示IC中互连层之一的互连负载。为每个嵌入式测试电路定义一个模型方程，每个模型方程式将其相关嵌入式测试电路的输出延迟指定为线路前端（FEOL）和线路后端（BEOL）参数的函数。然后，对于各种FEOL和BEOL参数求解模型方程，作为测试电路输出延迟的函数。最后，将测量的输出延迟值替换为这些参数方程，以生成各种FEOL和BEOL参数的实际值，从而允许快速准确地识别任何关注的领域。

70. 发明授权

US07314174B1 Method and system for configuring an integrated circuit 有权
标题翻译：用于配置集成电路的方法和系统
公开(公告)号：US07314174B1
公开(公告)日：2008-01-01
申请号：US10970964
申请日：2004-10-22
申请人： Vasisht Mantra Vadi , David P. Schultz , Steven P. Young , Jennifer Wong
发明人： Vasisht Mantra Vadi , David P. Schultz , Steven P. Young , Jennifer Wong
IPC分类号： G06K7/10 , G06K9/36 , G06K9/80
CPC分类号： H03K19/177
摘要： A system for programming configuration memory cells in an integrated circuit. The system includes: a set of data registers, wherein a member of the set has a temporary storage for a fixed number of configuration bits; and a plurality of rows, each row has a plurality of columns, wherein configuration memory cells in a selected column and in a selected row are programmed using the fixed number of configuration bits.
摘要翻译：一种用于在集成电路中编程配置存储单元的系统。该系统包括：一组数据寄存器，其中该组的成员具有固定数量的配置位的临时存储; 和多行，每行具有多个列，其中使用固定数量的配置位对所选列和所选行中的配置存储单元进行编程。

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