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61. 发明授权

US07459743B2 Dual port gain cell with side and top gated read transistor 有权
标题翻译：双端口增益单元，具有侧和顶栅控读取晶体管
公开(公告)号：US07459743B2
公开(公告)日：2008-12-02
申请号：US11161962
申请日：2005-08-24
申请人： Jack A. Mandelman , Kangguo Cheng , Ramachandra Divakaruni , Carl J. Radens , Geng Wang
发明人： Jack A. Mandelman , Kangguo Cheng , Ramachandra Divakaruni , Carl J. Radens , Geng Wang
IPC分类号： H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L27/108 , H01L27/10829 , H01L27/10867 , H01L27/1203
摘要： A DRAM memory cell and process sequence for fabricating a dense (20 or 18 square) layout is fabricated with silicon-on-insulator (SOI) CMOS technology. Specifically, the present invention provides a dense, high-performance SRAM cell replacement that is compatible with existing SOI CMOS technologies. Various gain cell layouts are known in the art. The present invention improves on the state of the art by providing a dense layout that is fabricated with SOI CMOS. In general terms, the memory cell includes a first transistor provided with a gate, a source, and a drain respectively; a second transistor having a first gate, a second gate, a source, and a drain respectively; and a capacitor having a first terminal, wherein the first terminal of said capacitor and the second gate of said second transistor comprise a single entity.
摘要翻译：使用绝缘体上硅（SOI）CMOS技术制造用于制造致密（20或18平方）布局的DRAM存储单元和工艺顺序。具体地，本发明提供了与现有SOI CMOS技术兼容的致密的高性能SRAM单元替换。各种增益单元布局在本领域中是已知的。本发明通过提供利用SOI CMOS制造的致密布局来改善现有技术的状态。通常，存储单元包括分别设置有栅极，源极和漏极的第一晶体管; 分别具有第一栅极，第二栅极，源极和漏极的第二晶体管; 以及具有第一端子的电容器，其中所述电容器的第一端子和所述第二晶体管的第二栅极包括单个实体。

62. 发明授权

US06869846B2 Forming electronic structures having dual dielectric thicknesses and the structure so formed 失效
标题翻译：形成具有双介电厚度的电子结构和如此形成的结构
公开(公告)号：US06869846B2
公开(公告)日：2005-03-22
申请号：US10411850
申请日：2003-04-10
申请人： Louis L. Hsu , Jack A. Mandelman , Carl J. Radens , Richard A. Strub , William R. Tonti
发明人： Louis L. Hsu , Jack A. Mandelman , Carl J. Radens , Richard A. Strub , William R. Tonti
IPC分类号： H01L21/8239 , H01L21/334 , H01L21/8234 , H01L21/8242 , H01L29/94
CPC分类号： H01L29/66181 , H01L21/823462 , H01L27/10861 , H01L27/10894 , H01L29/945
摘要： A structure including a first device and a second device, wherein the second device has a dielectric thickness greater than the dielectric thickness of the first device, and the method of so forming the structure.
摘要翻译：一种包括第一装置和第二装置的结构，其中所述第二装置的电介质厚度大于所述第一装置的电介质厚度，以及形成所述结构的方法。

63. 发明授权

US06806534B2 Damascene method for improved MOS transistor 失效
标题翻译：改进MOS晶体管的镶嵌方法
公开(公告)号：US06806534B2
公开(公告)日：2004-10-19
申请号：US10342423
申请日：2003-01-14
申请人： Omer H. Dokumaci , Bruce B. Doris , Oleg Gluschenkov , Jack A. Mandelman , Carl J. Radens
发明人： Omer H. Dokumaci , Bruce B. Doris , Oleg Gluschenkov , Jack A. Mandelman , Carl J. Radens
IPC分类号： H01L2976
CPC分类号： H01L29/66583 , H01L21/26586 , H01L21/28114 , H01L29/665 , H01L29/66553
摘要： A MOSFET fabrication methodology and device structure, exhibiting improved gate activation characteristics. The gate doping that may be introduced while the source drain regions are protected by a damascene mandrel to allow for a very high doping in the gate conductors, without excessively forming deep source/drain diffusions. The high gate conductor doping minimizes the effects of electrical depletion of carriers in the gate conductor. The MOSFET fabrication methodology and device structure further results in a device having a lower gate conductor width less than the minimum lithographic minimum image, and a wider upper gate conductor portion width which may be greater than the minimum lithographic image. Since the effective channel length of the MOSFET is defined by the length of the lower gate portion, and the line resistance is determined by the width of the upper gate portion, both short channel performance and low gate resistance are satisfied simultaneously.
摘要翻译： MOSFET制造方法和器件结构，表现出改进的栅极激活特性。当源极漏极区域被镶嵌心轴保护以允许栅极导体中的非常高的掺杂而不会过度地形成深的源极/漏极扩散时，可以引入栅极掺杂。高栅极导体掺杂最大限度地减小了栅极导体中载流子的电耗损的影响。 MOSFET制造方法和器件结构进一步导致具有小于最小光刻最小图像的较低栅极导体宽度的器件，以及可能大于最小光刻图像的较宽上部栅极导体部分宽度。由于MOSFET的有效沟道长度由下栅极部分的长度限定，并且线路电阻由上部栅极部分的宽度决定，所以同时满足短沟道性能和低栅极电阻。

64. 发明授权

US06724029B2 Twin-cell flash memory structure and method 有权
标题翻译：双电池闪存结构及方法
公开(公告)号：US06724029B2
公开(公告)日：2004-04-20
申请号：US09683831
申请日：2002-02-21
申请人： Louis L. Hsu , Chung H. Lam , Jack A. Mandelman , Carl J. Radens , William R. Tonti
发明人： Louis L. Hsu , Chung H. Lam , Jack A. Mandelman , Carl J. Radens , William R. Tonti
IPC分类号： H01L27108
CPC分类号： H01L27/11521 , G11C16/0441 , H01L27/115
摘要： A programmable memory cell structure that includes a pair of memory cells is provided. Each pair of memory cells includes a shared control gate and first and second floating gates present about the shared control gate. The first and second floating gates have respective gate regions disposed on respective sides of the control gate. Dielectric structures are present between the control gate and respective ones of the gate regions of the floating gates. The control gate and gates of the first and second floating gates are formed within a single lithographic square.
摘要翻译：提供了包括一对存储单元的可编程存储单元结构。每对存储单元包括共享控制栅极和围绕共享控制栅极存在的第一和第二浮动栅极。第一和第二浮栅具有设置在控制栅极的相应侧上的各自的栅极区域。电介质结构存在于控制栅极和浮动栅极的各个栅极区域之间。第一和第二浮动栅极的控制栅极和栅极形成在单个光刻平面内。

65. 发明授权

US06693041B2 Self-aligned STI for narrow trenches 失效
标题翻译：用于窄沟槽的自对准STI
公开(公告)号：US06693041B2
公开(公告)日：2004-02-17
申请号：US09885790
申请日：2001-06-20
申请人： Ramachandra Divakaruni , Jack A. Mandelman , Carl J. Radens
发明人： Ramachandra Divakaruni , Jack A. Mandelman , Carl J. Radens
IPC分类号： H01L21311
CPC分类号： H01L27/10867 , H01L21/76232 , H01L21/76235 , H01L27/0207 , H01L27/10864
摘要： A self-aligned shallow trench isolation region for a memory cell array is formed by etching a plurality of vertical deep trenches in a substrate and coating the trenches with an oxidation barrier layer. The oxidation barrier layer is recessed in portions of the trenches to expose portions of the substrate in the trenches. The exposed portions of the substrate are merged by oxidization into thermal oxide regions to form the self-aligned shallow trench isolation structure which isolates adjacent portions of substrate material. The merged oxide regions are self-aligned as they automatically aligned to the edges of the deep trenches when merged together to define the location of the isolation region within the memory cell array during IC fabrication. The instant self-aligned shallow trench isolation structure avoids the need for an isolation mask to separate or isolate the plurality of trenches within adjacent active area rows on a single substrate.
摘要翻译：通过蚀刻衬底中的多个垂直深沟槽并用氧化阻挡层涂覆沟槽，形成用于存储单元阵列的自对准浅沟槽隔离区。氧化阻挡层凹陷在沟槽的部分中以暴露沟槽中的衬底的部分。衬底的暴露部分通过氧化合并成热氧化物区域，以形成隔离衬底材料的相邻部分的自对准浅沟槽隔离结构。合并的氧化物区域是自对准的，因为它们在合成时自动对准深沟槽的边缘，以在IC制造期间限定存储单元阵列内的隔离区域的位置。瞬时自对准浅沟槽隔离结构避免了需要隔离掩模以在单个衬底上的相邻有效区域行内分离或隔离多个沟槽。

66. 发明授权

US06566191B2 Forming electronic structures having dual dielectric thicknesses and the structure so formed 失效
公开(公告)号：US06566191B2
公开(公告)日：2003-05-20
申请号：US09731148
申请日：2000-12-05
申请人： Louis L. Hsu , Jack A. Mandelman , Carl J. Radens , Richard A. Strub , William R. Tonti
发明人： Louis L. Hsu , Jack A. Mandelman , Carl J. Radens , Richard A. Strub , William R. Tonti
IPC分类号： H01L218242
CPC分类号： H01L29/66181 , H01L21/823462 , H01L27/10861 , H01L27/10894 , H01L29/945
摘要： A structure including a first device and a second device, wherein the second device has a dielectric thickness greater than the dielectric thickness of the first device, and the method of so forming the structure.

67. 发明授权

US06541815B1 High-density dual-cell flash memory structure 失效
标题翻译：高密度双单元闪存结构
公开(公告)号：US06541815B1
公开(公告)日：2003-04-01
申请号：US09974968
申请日：2001-10-11
申请人： Jack A. Mandelman , Louis L. Hsu , Chung H. Lam , Carl J. Radens
发明人： Jack A. Mandelman , Louis L. Hsu , Chung H. Lam , Carl J. Radens
IPC分类号： H01L29788
CPC分类号： H01L29/66825 , H01L21/28273 , H01L27/115 , H01L27/11556 , H01L29/7885
摘要： A 2F2 flash memory cell structure and a method of fabricating the same are provided. The 2F2 flash memory cell structure includes a Si-containing substrate having a plurality of trenches formed therein. Each trench has sidewalls that extend to a bottom wall, a length and individual segments that include two memory cell elements per segment. Each memory cell element comprises (i) a floating gate region having L-shaped gates formed on a portion of each trench sidewall; (ii) a program line overlapping one side of the L-shaped gates present at the bottom wall of each trench and extending along the entire length of the plurality of trenches; and (iii) a control gate region overlying the floating gate region. The control gate region includes gates formed on portions of the sidewalls of the trenches that are coupled to the floating gate regions. The memory cell structure further includes bitline diffusion regions formed in the Si-containing semiconductor substrate abutting each trench segment; and wordlines that lay orthogonal to the trenches. The wordlines are in contact with a top surface of each control gate region.
摘要翻译：提供了一种2F2闪存单元结构及其制造方法。 2F2闪存单元结构包括其中形成有多个沟槽的含Si衬底。每个沟槽具有延伸到底壁，长度和包括每个段的两个存储单元元件的单独段的侧壁。每个存储单元元件包括（i）具有形成在每个沟槽侧壁的一部分上的L形栅极的浮栅区域; （ii）重叠在每个沟槽的底壁处的L形门的一侧并沿多个沟槽的整个长度延伸的程序线; 和（iii）覆盖浮栅区域的控制栅极区域。控制栅极区域包括形成在沟槽的侧壁的与浮动栅极区域耦合的部分上的栅极。所述存储单元结构还包括形成在所述含Si半导体衬底中的位线邻接每个沟槽段的位线扩散区; 和与沟槽正交的字线。字线与每个控制栅极区域的顶表面接触。

68. 发明授权

US06452224B1 Method for manufacture of improved deep trench eDRAM capacitor and structure produced thereby 失效
标题翻译：用于制造改进的深沟槽eDRAM电容器的方法和由此产生的结构
公开(公告)号：US06452224B1
公开(公告)日：2002-09-17
申请号：US09910981
申请日：2001-07-23
申请人： Jack A. Mandelman , Carl J. Radens
发明人： Jack A. Mandelman , Carl J. Radens
IPC分类号： H01L2994
CPC分类号： H01L27/10864 , H01L27/10841 , H01L27/10867 , H01L29/945
摘要： A capacitor is formed in a trench in a well/substrate doped with a first polarity. A dielectric isolation collar formed on trench sidewalls is recessed below the trench top and is spaced from the trench bottom. Therebelow, a counterdoped plate electrode region surrounds the trench and a node dielectric covers the exposed sidewalls. A counterdoped conductive buffer layer or region covers the node dielectric. A conductive, lower diffusion barrier covers the buffer. A first polarity doped node conductor, which is formed over the lower diffusion barrier, is covered by a conductive, upper diffusion barrier. A counterdoped cap covers the upper diffusion barrier. A counterdoped strap region formed by outdiffusion into the substrate is juxtaposed with the edge of the cap.
摘要翻译：在掺杂有第一极性的阱/衬底的沟槽中形成电容器。形成在沟槽侧壁上的介电隔离套环凹陷在沟槽顶部下方并与沟槽底部间隔开。此后，反向平板电极区域围绕沟槽，并且节点电介质覆盖暴露的侧壁。反向导电缓冲层或区域覆盖节点电介质。导电的下扩散阻挡层覆盖缓冲区。形成在下部扩散阻挡层上的第一极性掺杂节点导体被导电的上扩散阻挡层覆盖。反向盖覆盖上部扩散屏障。通过向外扩散形成的对向带区域与盖的边缘并置。

69. 发明授权

US06451648B1 Process for buried-strap self-aligned to deep storage trench 失效
标题翻译：埋层自对准深沟槽工艺
公开(公告)号：US06451648B1
公开(公告)日：2002-09-17
申请号：US09233887
申请日：1999-01-20
申请人： Ulrike Gruening , Jack A. Mandelman , Carl J. Radens
发明人： Ulrike Gruening , Jack A. Mandelman , Carl J. Radens
IPC分类号： H01L218242
CPC分类号： H01L27/10861
摘要： A process for forming a buried strap self-aligned to a deep storage trench. Spacers are formed on walls of a recess over a filled deep trench capacitor and a substrate. A plug is formed in a region between the spacers. Photoresist is deposited over the spacers, the plug, and material surrounding the spacers of the plug. The photoresist is patterned, thereby exposing portions of the plug, the spacers, and the surrounding material. The spacers in the surrounding material not covered by the photoresist are selectively etched, leaving a remaining portion of the spacers. The substrate and the portion of the filled deep trench exposed by the spacer removal are selectively etched. An isolation region is formed in a space created by etching of the spacers, surrounding material, substrate, and filled deep trench.
摘要翻译：一种用于形成与深存储沟槽自对准的掩埋带的工艺。垫片形成在填充的深沟槽电容器和衬底上的凹部的壁上。插塞形成在间隔件之间的区域中。光刻胶沉积在隔离物，插塞和围绕插塞间隔物的材料上。对光致抗蚀剂进行图案化，从而暴露插头，间隔件和周围材料的部分。不被光致抗蚀剂覆盖的周围材料中的间隔物被选择性地蚀刻，留下间隔物的剩余部分。通过间隔物去除暴露的衬底和填充的深沟槽的部分被选择性地蚀刻。隔离区形成在通过蚀刻间隔物，周围的材料，衬底和填充的深沟槽而产生的空间中。

70. 发明授权

US06426526B1 Single sided buried strap 失效
标题翻译：单面埋地带
公开(公告)号：US06426526B1
公开(公告)日：2002-07-30
申请号：US09870068
申请日：2001-05-30
申请人： Ramachandra Divakaruni , Jack A. Mandelman , Gary B. Bronner , Carl J. Radens
发明人： Ramachandra Divakaruni , Jack A. Mandelman , Gary B. Bronner , Carl J. Radens
IPC分类号： H01L27108
CPC分类号： H01L27/10864
摘要： An easily manufactured connecting structure from a node conductor of trench capacitor device is characterized at least in part by the presence of an isolation collar located above the node conductor, at least a portion of the collar having an exterior surface which is substantially conformal with at least a portion of an adjacent wall of the trench, a buried strap region in the trench above the node conductor, the strap region being bounded laterally by the isolation collar except at an opening in the collar. The connecting structure is preferably formed by a method involving clearing an isolation collar from a first interior surface of a deep trench at a location above a storage capacitor while leaving the isolation collar at other surfaces of the deep trench.
摘要翻译：至少部分地由位于节点导体上方的隔离套管的存在而将来自沟槽电容器装置的节点导体的容易制造的连接结构的特征在于，所述套环的至少一部分具有至少基本上保形的外表面沟槽的相邻壁的一部分，在节点导体上方的沟槽中的掩埋带区域，除了在套环的开口处之外，带区域被隔离套环侧向限定。连接结构优选地通过一种方法来形成，该方法包括在存储电容器上方的位置处从深沟槽的第一内表面清除隔离套环，同时将隔离套环留在深沟槽的其他表面。

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