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61. 发明授权

US06753271B2 Atomic layer deposition methods 有权
标题翻译：原子层沉积法
公开(公告)号：US06753271B2
公开(公告)日：2004-06-22
申请号：US10222282
申请日：2002-08-15
申请人： Demetrius Sarigiannis , Garo J. Derderian , Cem Basceri , Gurtej S. Sandhu , F. Daniel Gealy , Chris M. Carlson
发明人： Demetrius Sarigiannis , Garo J. Derderian , Cem Basceri , Gurtej S. Sandhu , F. Daniel Gealy , Chris M. Carlson
IPC分类号： H01L2144
CPC分类号： H01L21/32051 , C23C16/4404 , C23C16/4405 , C23C16/45531 , C23C16/45534 , H01L21/02178 , H01L21/02186 , H01L21/0228 , H01L21/28562 , H01L21/3141 , H01L21/31616
摘要： The invention includes an atomic layer deposition method of forming a layer of a deposited composition on a substrate. The method includes positioning a semiconductor substrate within an atomic layer deposition chamber. On the substrate, an intermediate composition monolayer is formed, followed by a desired deposited composition from reaction with the intermediate composition, collectively from flowing multiple different composition deposition precursors to the substrate within the deposition chamber. A material adheres to a chamber internal component surface from such sequentially forming. After such sequentially forming, a reactive gas flows to the chamber which is different in composition from the multiple different deposition precursors and which is effective to react with such adhering material. After the reactive gas flowing, such sequentially forming is repeated. Further implementations are contemplated.
摘要翻译：本发明包括在基板上形成沉积的组合物层的原子层沉积方法。该方法包括将半导体衬底定位在原子层沉积室内。在基材上形成中间组合物单层，随后是与中间体组合物反应所需的沉积组合物，统称为将多种不同的组合物沉积前体流到沉积室内的基底。材料粘附到室内部件表面，从而依次形成。在这种顺序形成之后，反应性气体流入到与多种不同的沉积前体不同的组合物中，并有效地与这种粘附材料反应。在反应气体流动之后，重复这种顺序形成。考虑进一步的实现。

62. 发明授权

US06673701B1 Atomic layer deposition methods 有权
标题翻译：原子层沉积法
公开(公告)号：US06673701B1
公开(公告)日：2004-01-06
申请号：US10229887
申请日：2002-08-27
申请人： Eugene Marsh , Brian Vaartstra , Paul J. Castrovillo , Cem Basceri , Garo J. Derderian , Gurtej S. Sandhu
发明人： Eugene Marsh , Brian Vaartstra , Paul J. Castrovillo , Cem Basceri , Garo J. Derderian , Gurtej S. Sandhu
IPC分类号： C30B2502
CPC分类号： C30B25/14 , C23C16/45527 , C30B25/02
摘要： An atomic layer deposition method includes positioning a semiconductor substrate within an atomic layer deposition chamber. A first precursor gas is flowed to the substrate within the atomic layer deposition chamber effective to form a first monolayer on the substrate. The first precursor gas flowing comprises a plurality of first precursor gas pulses. The plurality of first precursor gas pulses comprises at least one total period of time between two immediately adjacent first precursor gas pulses when no gas is fed to the chamber. After forming the first monolayer on the substrate, a second precursor gas different in composition from the first is flowed to the substrate within the deposition chamber effective to form a second monolayer on the first monolayer. Other aspects and implementations are contemplated.
摘要翻译：原子层沉积方法包括将半导体衬底定位在原子层沉积室内。第一前体气体流到原子层沉积室内的衬底，有效地在衬底上形成第一单层。第一前体气体流动包括多个第一前体气体脉冲。多个第一前体气体脉冲包括当没有气体被供给到腔室时在两个紧邻的第一前体气体脉冲之间的至少一个总时间段。在衬底上形成第一单层之后，组成不同于第一衬底的第二前体气体流入沉积室内的衬底，有效地在第一单层上形成第二单层。考虑了其他方面和实现。

63. 发明授权

US06586796B2 Capacitor with high dielectric constant materials 有权
标题翻译：具有高介电常数材料的电容器
公开(公告)号：US06586796B2
公开(公告)日：2003-07-01
申请号：US10115340
申请日：2002-04-02
申请人： Cem Basceri , Gurtej S. Sandhu , Sam Yang
发明人： Cem Basceri , Gurtej S. Sandhu , Sam Yang
IPC分类号： H01L31119
CPC分类号： H01L28/75 , H01L21/02178 , H01L21/02183 , H01L21/02197 , H01L21/02271 , H01L21/31604 , H01L21/31683 , H01L27/10811 , H01L28/55
摘要： A stabilized capacitor using non-oxide electrodes and high dielectric constant oxide dielectric materials is provided. The stabilized capacitor comprises a non-oxide electrode with an oxidized upper surface. A high dielectric constant oxide dielectric material is adjacent to the oxidized upper surface of the non-oxide electrode. An upper layer electrode is adjacent to the high dielectric constant oxide dielectric material.
摘要翻译：提供了使用非氧化物电极和高介电常数氧化物介电材料的稳定电容器。稳定电容器包括具有氧化的上表面的非氧化物电极。高介电常数氧化物介电材料与非氧化物电极的氧化的上表面相邻。上层电极与高介电常数氧化物电介质材料相邻。

64. 发明授权

US06586285B1 Plasma enhanced chemical vapor deposition method of forming titanium silicide comprising layers 有权
标题翻译：等离子体增强化学气相沉积法形成含硅化钛的层
公开(公告)号：US06586285B1
公开(公告)日：2003-07-01
申请号：US10094017
申请日：2002-03-06
申请人： Cem Basceri , Irina Vasilyeva , Ammar Derraa , Philip H. Campbell , Gurtej S. Sandhu
发明人： Cem Basceri , Irina Vasilyeva , Ammar Derraa , Philip H. Campbell , Gurtej S. Sandhu
IPC分类号： H01L2184
CPC分类号： C23C16/4407 , C23C16/14 , C23C16/42 , C23C16/4404
摘要： A first cleaning is conducted on a plasma enhanced chemical vapor deposition chamber at room ambient pressure. After the first cleaning, elemental titanium comprising layers are chemical vapor deposited on a first plurality of substrates within the chamber using at least TiCl4. Thereafter, titanium silicide comprising layers are plasma enhanced chemical vapor deposited on a second plurality of substrates within the chamber using at least TiCl4 and a silane. Thereafter, a second cleaning is conducted on the chamber at ambient room pressure. In one implementation after the first cleaning, an elemental titanium comprising layer is chemical vapor deposited over internal surfaces of the chamber while no semiconductor substrate is received within the chamber. In another implementation, a titanium silicide comprising layer is chemical vapor deposited over internal surfaces of the chamber while no semiconductor substrate is received within the chamber.
摘要翻译：在室内环境压力下，在等离子体增强化学气相沉积室上进行第一次清洗。在第一次清洁之后，使用至少TiCl 4，在室内的第一组多个衬底上化学气相沉积包含层的元素钛。此后，包含层的硅化钛是使用至少TiCl 4和硅烷沉积在室内的第二多个基板上的等离子体增强化学气相。此后，在室内在室内进行第二清洗。在第一次清洁之后的一个实施方案中，元素钛包含层在室的内表面上化学气相沉积，而在室内没有接收半导体衬底。在另一个实施方案中，包含硅化钛的层在室的内表面上化学气相沉积，而在腔室内不接收半导体衬底。

65. 发明授权

US06566147B2 Method for controlling deposition of dielectric films 有权
公开(公告)号：US06566147B2
公开(公告)日：2003-05-20
申请号：US09776217
申请日：2001-02-02
申请人： Cem Basceri , Dan Gealy , Gurtej S. Sandhu
发明人： Cem Basceri , Dan Gealy , Gurtej S. Sandhu
IPC分类号： H01L2100
CPC分类号： H01L21/02271 , C23C16/409 , C23C16/52 , H01L21/02197 , H01L21/31691
摘要： A method for controlling stoichiometry of dielectric films, e.g., BST films, preferably formed at low deposition temperatures. A deposition process may use an adjustment in oxidizer flow and/or partial pressure, the provision of a hydrogen-containing component, an adjustment in hydrogen-containing component flow and/or partial pressure, an adjustment in deposition pressure, and/or a modification of system component parameters (e.g., heating a shower head or adjusting a distance between a shower head of the deposition system and a wafer upon which the film is to be deposited), to control the characteristics of the dielectric film, e.g., film stoichiometry.

66. 发明授权

US06558517B2 Physical vapor deposition methods 有权
公开(公告)号：US06558517B2
公开(公告)日：2003-05-06
申请号：US10003575
申请日：2001-10-29
申请人： Cem Basceri
发明人： Cem Basceri
IPC分类号： C23C1424
CPC分类号： C23C16/45523 , C23C14/088 , C23C14/3492 , C23C16/409 , C23C16/45557 , H01L28/55
摘要： The invention includes chemical vapor deposition and physical vapor deposition methods of forming high k ABO3 comprising dielectric layers on a substrate, where “A” is selected from the group consisting of Group IIA and Group IVB elements and mixtures thereof, and where “B” is selected from the group consisting of Group IVA metal elements and mixtures thereof. In one implementation, a plurality of precursors comprising A, B and O are fed to a chemical vapor deposition chamber having a substrate positioned therein under conditions effective to deposit a high k ABO3 comprising dielectric layer over the substrate. During the feeding, pressure within the chamber is varied effective to produce different concentrations of A at different elevations in the deposited layer and where higher comparative pressure produces greater concentration of B in the deposited layer. In one implementation, a subatmospheric physical vapor deposition method of forming a high k ABO3 comprising dielectric layer on a substrate includes providing a sputtering target comprising ABO3 and a substrate to be deposited upon within a physical vapor deposition chamber. A sputtering gas is fed to the chamber under conditions effective to sputter the target and deposit a high k ABO3 comprising dielectric layer over the substrate. During the feeding, pressure is varied within the chamber effective to produce different concentrations of B at different elevations in the deposited layer and where higher comparative pressure produces greater concentration of B in the deposited layer.

67. 发明授权

US06492241B1 Integrated capacitors fabricated with conductive metal oxides 有权
标题翻译：用导电金属氧化物制成的集成电容器
公开(公告)号：US06492241B1
公开(公告)日：2002-12-10
申请号：US09546492
申请日：2000-04-10
申请人： Howard E. Rhodes , Mark Visokay , Tom Graettinger , Dan Gealy , Gurtej Sandhu , Cem Basceri , Steve Cummings
发明人： Howard E. Rhodes , Mark Visokay , Tom Graettinger , Dan Gealy , Gurtej Sandhu , Cem Basceri , Steve Cummings
IPC分类号： H01L2972
CPC分类号： H01L28/60 , C23C16/40 , H01L28/55 , H01L28/90
摘要： A capacitor for a memory device is formed with a conductive oxide for a bottom electrode. The conductive oxide (RuOx) is deposited under low temperatures as an amorphous film. As a result, the film is conformally deposited over a three dimensional, folding structure. Furthermore, a subsequent polishing step is easily performed on the amorphous film, increasing wafer throughput. After deposition and polishing, the film is crystallized in a non-oxidizing ambient.
摘要翻译：用于存储器件的电容器形成有用于底部电极的导电氧化物。导电氧化物（RuOx）在低温下作为非晶膜沉积。结果，膜被共形沉积在三维折叠结构上。此外，随后的研磨步骤容易地在非晶膜上进行，提高了晶片生产量。沉积和抛光后，膜在非氧化环境中结晶。

68. 发明授权

US09620670B2 Solid state lighting dies with quantum emitters and associated methods of manufacturing 有权
公开(公告)号：US09620670B2
公开(公告)日：2017-04-11
申请号：US12874360
申请日：2010-09-02
申请人： Cem Basceri , Casey Kurth , Thomas Gehrke , Kevin Tetz
发明人： Cem Basceri , Casey Kurth , Thomas Gehrke , Kevin Tetz
IPC分类号： H01L21/77 , H01L33/12 , H01L33/00 , H01L33/08 , H01L33/02
CPC分类号： H01L33/007 , H01L33/02 , H01L33/08 , H01L2924/0002 , H01L2924/00
摘要： Solid state lighting dies and associated methods of manufacturing are disclosed herein. In one embodiment, a solid state lighting die includes a substrate material, a first semiconductor material, a second semiconductor material, and an active region between the first and second semiconductor materials. The second semiconductor material has a surface facing away from the substrate material. The solid state lighting die also includes a plurality of openings extending from the surface of the second semiconductor material toward the substrate material.

69. 发明授权

US08786005B2 One-transistor composite-gate memory 有权
标题翻译：单晶体管复合栅极存储器
公开(公告)号：US08786005B2
公开(公告)日：2014-07-22
申请号：US13554577
申请日：2012-07-20
申请人： Cem Basceri , Gurtej S. Sandhu
发明人： Cem Basceri , Gurtej S. Sandhu
IPC分类号： H01L29/792
CPC分类号： G11C11/5671 , G11C8/12 , G11C16/0416 , G11C16/0466 , H01L29/513 , H01L29/792
摘要： One-transistor memory devices facilitate nonvolatile data storage through the manipulation of oxygen vacancies within a trapping layer of a field-effect transistor (FET), thereby providing control and variation of threshold voltages of the transistor. Various threshold voltages may be assigned a data value, providing the ability to store one or more bits of data in a single memory cell. To control the threshold voltage, the oxygen vacancies may be manipulated by trapping electrons within the vacancies, freeing trapped electrons from the vacancies, moving the vacancies within the trapping layer and annihilating the vacancies.
摘要翻译：单晶体管存储器件通过操纵场效应晶体管（FET）的俘获层内的氧空位来促进非易失性数据存储，从而提供晶体管的阈值电压的控制和变化。可以为各种阈值电压分配数据值，提供将一个或多个位数据存储在单个存储器单元中的能力。为了控制阈值电压，可以通过在空位内捕获电子来操纵氧空位，从空位释放被俘获的电子，移动捕获层内的空位并湮灭空位。

70. 发明授权

US08409933B2 Methods of forming conductive contacts to source/drain regions and methods of forming local interconnects 有权
公开(公告)号：US08409933B2
公开(公告)日：2013-04-02
申请号：US13302231
申请日：2011-11-22
申请人： Cem Basceri , Gurtej S. Sandhu , H. Montgomery Manning
发明人： Cem Basceri , Gurtej S. Sandhu , H. Montgomery Manning
IPC分类号： H01L21/82 , H01L21/338 , H01L21/326
CPC分类号： H01L21/76823 , H01L21/28512 , H01L21/76895 , Y10T428/12542
摘要： The invention comprises methods of forming a conductive contact to a source/drain region of a field effect transistor, and methods of forming local interconnects. In one implementation, a method of forming a conductive contact to a source/drain region of a field effect transistor includes providing gate dielectric material intermediate a transistor gate and a channel region of a field effect transistor. At least some of the gate dielectric material extends to be received over at least one source/drain region of the field effect transistor. The gate dielectric material received over the one source/drain region is exposed to conditions effective to change it from being electrically insulative to being electrically conductive and in conductive contact with the one source/drain region. Other aspects and implementations are contemplated.

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