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61. 发明授权

US08099556B2 Cache miss detection in a data processing apparatus 有权
标题翻译：数据处理装置中的缓存未命中检测
公开(公告)号：US08099556B2
公开(公告)日：2012-01-17
申请号：US11990394
申请日：2005-09-13
申请人： Mrinmoy Ghosh , Emre Özer , Stuart David Biles
发明人： Mrinmoy Ghosh , Emre Özer , Stuart David Biles
IPC分类号： G06F12/08
CPC分类号： G06F9/3851 , G06F9/383 , G06F12/0802 , G06F12/0897
摘要： A data processing apparatus and method are provided for detecting cache misses. The data processing apparatus has processing logic for executing a plurality of program threads, and a cache for storing data values for access by the processing logic. When access to a data value is required while executing a first program thread, the processing logic issues an access request specifying an address in memory associated with that data value, and the cache is responsive to the address to perform a lookup procedure to determine whether the data value is stored in the cache. Indication logic is provided which in response to an address portion of the address provides an indication as to whether the data value is stored in the cache, this indication being produced before a result of the lookup procedure is available, and the indication logic only issuing an indication that the data value is not stored in the cache if that indication is guaranteed to be correct. Control logic is then provided which, if the indication indicates that the data value is not stored in the cache, uses that indication to control a process having an effect on a program thread other than the first program thread.
摘要翻译：提供了一种用于检测高速缓存未命中的数据处理装置和方法。数据处理装置具有用于执行多个程序线程的处理逻辑，以及用于存储由处理逻辑进行访问的数据值的高速缓存。当执行第一程序线程时需要访问数据值时，处理逻辑发出指定与该数据值相关联的存储器中的地址的访问请求，并且高速缓冲存储器响应于该地址执行查找过程以确定是否数据值存储在缓存中。指示逻辑被提供，其响应于地址的地址部分提供关于数据值是否存储在高速缓存中的指示，该指示在查找过程的结果可用之前产生，并且指示逻辑仅发出指示如果该指示保证正确，则数据值不存储在高速缓存中。然后提供控制逻辑，如果该指示指示数据值未被存储在高速缓存中，则使用该指示来控制对除第一程序线程之外的程序线程有影响的进程。

62. 发明授权

US08055872B2 Data processor with hardware accelerator, accelerator interface and shared memory management unit 有权
标题翻译：具有硬件加速器，加速器接口和共享内存管理单元的数据处理器
公开(公告)号：US08055872B2
公开(公告)日：2011-11-08
申请号：US12071505
申请日：2008-02-21
申请人： Stuart David Biles , Nigel Charles Paver , Chander Sudanthi
发明人： Stuart David Biles , Nigel Charles Paver , Chander Sudanthi
IPC分类号： G06F13/40
CPC分类号： G06F13/1668 , G06F2213/0038
摘要： A data processing system in the form of an integrated circuit includes a general purpose programmable processor and a hardware accelerator. A shared memory management unit provides memory management operations on behalf of both of the processor core and the hardware accelerator. The processor and the hardware accelerator share a memory system. A first communication channel between the processor and the hardware accelerator communicates at least control signals therebetween. A second communication channel coupling the hardware accelerator and the memory system allows the hardware accelerator to perform its own data access operations upon the memory system.
摘要翻译：集成电路形式的数据处理系统包括通用可编程处理器和硬件加速器。共享存储器管理单元代表处理器核和硬件加速器两者提供存储器管理操作。处理器和硬件加速器共享一个内存系统。处理器和硬件加速器之间的第一通信信道至少与其间通信控制信号。耦合硬件加速器和存储器系统的第二通信通道允许硬件加速器在存储器系统上执行其自己的数据访问操作。

63. 发明授权

US08041930B2 Data processing apparatus and method for controlling thread access of register sets when selectively operating in secure and non-secure domains 有权
标题翻译：当选择性地在安全和非安全域中操作时，用于控制寄存器组的线程访问的数据处理装置和方法
公开(公告)号：US08041930B2
公开(公告)日：2011-10-18
申请号：US11919757
申请日：2005-05-11
申请人： David Hennah Mansell , Stuart David Biles , David Michael Gilday , Daniel Kershaw
发明人： David Hennah Mansell , Stuart David Biles , David Michael Gilday , Daniel Kershaw
IPC分类号： G06F9/00
CPC分类号： G06F9/30123 , G06F9/3012 , G06F9/3851
摘要： The data processing apparatus has processing logic for performing data processing operations and a register bank for storing data associated with the processing logic. The register bank has at least one register group, each register group having a plurality of register sets. The processing logic has an operating state associated with each register group defining how that register group is used, a first operating state being a state in which each register set in the register group is used to support an independent execution thread of the processing logic, and a second operating state being a state in which the register sets of the register group are collectively used to support a single execution thread of the processing logic. Control logic is provided to control how the register sets of each register group are used dependent on the operating state associated with that register group.
摘要翻译：数据处理装置具有用于执行数据处理操作的处理逻辑和用于存储与处理逻辑相关联的数据的寄存器组。寄存器组具有至少一个寄存器组，每个寄存器组具有多个寄存器组。处理逻辑具有与定义如何使用该寄存器组的每个寄存器组相关联的操作状态，第一操作状态是其中在寄存器组中设置的每个寄存器用于支持处理逻辑的独立执行线程的状态，以及第二操作状态是将寄存器组的寄存器组集中用于支持处理逻辑的单个执行线程的状态。提供控制逻辑以根据与该寄存器组相关联的操作状态来控制如何使用每个寄存器组的寄存器组。

64. 发明授权

US07865675B2 Controlling cleaning of data values within a hardware accelerator 有权
标题翻译：控制硬件加速器中数据值的清理
公开(公告)号：US07865675B2
公开(公告)日：2011-01-04
申请号：US12000005
申请日：2007-12-06
申请人： Nigel Charles Paver , Stuart David Biles
发明人： Nigel Charles Paver , Stuart David Biles
IPC分类号： G06F12/00 , G06F15/76
CPC分类号： G06F12/0804 , G06F9/3879 , G06F12/0815 , G06F12/1027
摘要： A data processing apparatus 2 includes a programmable general purpose processor 10 coupled to a hardware accelerator 12. A memory system 14, 6, 8 is shared by the processor 10 and the hardware accelerator 12. Memory system monitoring circuitry 16 is responsive to one or more predetermined operations performed by the processor 10 upon the memory system 14, 6, 8 to generate a trigger to the hardware accelerator 12 for it to halt its processing operations and clean any data values held as temporary variables within registers 20 of the hardware accelerator back to the memory system 14, 6, 8.
摘要翻译：数据处理装置2包括耦合到硬件加速器12的可编程通用处理器10.存储器系统14,6,8由处理器10和硬件加速器12共享。存储器系统监视电路16响应于一个或多个由处理器10在存储器系统14,6,8上执行的预定操作，以产生对硬件加速器12的触发，以使其停止其处理操作，并清除作为硬件加速器的寄存器20内的临时变量所保持的任何数据值。存储器系统14,6,8。

65. 发明授权

US07743238B2 Accessing items of architectural state from a register cache in a data processing apparatus when performing branch prediction operations for an indirect branch instruction 有权
标题翻译：当对间接分支指令进行分支预测操作时，从数据处理装置中的寄存器高速缓冲存取建筑状态项
公开(公告)号：US07743238B2
公开(公告)日：2010-06-22
申请号：US10434367
申请日：2003-05-09
申请人： Stuart David Biles
发明人： Stuart David Biles
IPC分类号： G06F9/00
CPC分类号： G06F9/383 , G06F9/30098 , G06F9/3012 , G06F9/30138 , G06F9/3824 , G06F9/3826 , G06F9/3832 , G06F9/3885 , G06F9/3891
摘要： The present invention relates to a data processing apparatus and method for accessing items of architectural state. The data processing apparatus comprises a plurality of registers operable to store items of architectural state, and a plurality of functional units, each functional unit being operable to perform a processing operation with reference to one or more of those items of architectural state. At least one of the functional units has a register cache associated therewith having one or more cache entries, each cache entry being operable to store a copy of one of the items of architectural state, and a register identifier identifying the register containing that item of architectural state. Control logic is operable to determine a subset of the items of architectural state to be copied in the register cache in dependence on the processing operation of the functional unit with which the register cache is associated. This assists in alleviating demands on access ports associated with the registers.
摘要翻译：本发明涉及一种用于访问建筑状态的数据处理装置和方法。数据处理装置包括可操作以存储建筑状态项目的多个寄存器和多个功能单元，每个功能单元可操作以参考建筑状态的一个或多个项目执行处理操作。功能单元中的至少一个具有与其相关联的寄存器高速缓冲存储器，其具有一个或多个高速缓存条目，每个高速缓存条目可操作以存储建筑状态项目之一的副本，以及标识包含该建筑物项目的寄存器的寄存器标识符州。控制逻辑可操作以根据与寄存器高速缓存相关联的功能单元的处理操作来确定要在寄存器高速缓存中复制的体系结构状态的子集。这有助于缓解与寄存器相关的访问端口的需求。

66. 发明授权

US07685404B2 Program subgraph identification 有权
标题翻译：程序子图识别
公开(公告)号：US07685404B2
公开(公告)日：2010-03-23
申请号：US11806907
申请日：2007-06-05
申请人： Stuart David Biles , Krisztian Flautner , Scott Mahlke , Nathan Clark
发明人： Stuart David Biles , Krisztian Flautner , Scott Mahlke , Nathan Clark
IPC分类号： G06F9/00
CPC分类号： G06F8/4441
摘要： An apparatus is provided for processing data under control of a program having program instructions and subgraph suggestion information identifying respective sequences of program instructions corresponding to computational subgraphs identified within the program. A memory stores a program formed of separate program instructions. Processing logic executes respective separate program instructions from said program. Accelerator logic, in response to reaching an execution point within the program associated with a subgraph suggestion, executes a sequence of program instructions corresponding to the subgraph suggestion as an accelerated operation instead of executing the sequence of program instructions as respective separate program instructions with the processing logic.
摘要翻译：提供了一种用于在具有程序指令和子图表建议信息的程序的控制下处理数据的装置，其识别与程序内识别的计算子图相对应的程序指令的各个序列。存储器存储由单独的程序指令形成的程序。处理逻辑从所述程序执行相应的单独的程序指令。加速器逻辑响应于到达与子图建议相关联的程序中的执行点，执行对应于子图建议的程序指令序列作为加速操作，而不是执行程序指令序列作为相应的单独的程序指令，其中处理逻辑。

67. 发明授权

US07650483B2 Execution of instructions within a data processing apparatus having a plurality of processing units 有权
标题翻译：执行具有多个处理单元的数据处理装置内的指令
公开(公告)号：US07650483B2
公开(公告)日：2010-01-19
申请号：US11592337
申请日：2006-11-03
申请人： Elodie Charra , Frederic Claude Marie Piry , Richard Roy Grisenthwaite , Mélanie Emanuelle Lucie Vincent , Norbert Bernard Eugéne Lataille , Jocelyn Francois Orion Jaubert , Stuart David Biles
发明人： Elodie Charra , Frederic Claude Marie Piry , Richard Roy Grisenthwaite , Mélanie Emanuelle Lucie Vincent , Norbert Bernard Eugéne Lataille , Jocelyn Francois Orion Jaubert , Stuart David Biles
IPC分类号： G06F15/80
CPC分类号： G06F15/8007 , G06F9/3004 , G06F9/3834 , G06F9/3836 , G06F9/3885 , G06F9/3891 , G06F9/3897 , G06F12/0837
摘要： A data processing apparatus and method are provided for handling execution of instructions within a data processing apparatus having a plurality of processing units. Each processing unit is operable to execute a sequence of instructions so as to perform associated operations, and at least a subset of the processing units form a cluster. Instruction forwarding logic is provided which for at least one instruction executed by at least one of the processing units in the cluster causes that instruction to be executed by each of the other processing units in the cluster, for example by causing that instruction to be inserted into the sequences of instructions executed by each of the other processing units in the cluster. Such a mechanism provides a particularly efficient technique to cause each of the processing units in the cluster to perform an identical operation which can be useful in a variety of situations, for example in an SMP system where coherency of data is required and accordingly maintenance operations need to be performed periodically within each processing unit to ensure such coherency.
摘要翻译：提供了一种用于处理具有多个处理单元的数据处理装置内的指令执行的数据处理装置和方法。每个处理单元可操作以执行指令序列，以便执行相关联的操作，并且处理单元的至少一个子集形成一个簇。提供了指令转发逻辑，对于由集群中的至少一个处理单元执行的至少一个指令，导致该指令由集群中的每个其他处理单元执行，例如通过使该指令被插入由群集中的每个其他处理单元执行的指令序列。这样的机制提供了一种特别有效的技术，以使群集中的每个处理单元执行相同的操作，其可以在各种情况下有用，例如在需要数据的一致性并因此需要维护操作的SMP系统中以在每个处理单元内周期性地执行以确保这样的一致性。

68. 发明申请

US20090313455A1 Instruction issue control wtihin a multithreaded processor 审中-公开
标题翻译：多线程处理器中的指令问题控制
公开(公告)号：US20090313455A1
公开(公告)日：2009-12-17
申请号：US11919210
申请日：2005-12-15
申请人： David Hennah Mansell , Stuart David Biles
发明人： David Hennah Mansell , Stuart David Biles
IPC分类号： G06F9/38
CPC分类号： G06F9/3836 , G06F9/3838 , G06F9/3851 , G06F9/3857
摘要： A multithreaded processor is provided with a saturating counter which serves to generate a thread preference signal to steer selection of which program thread operations are taken from for issue into the multiple processor pipelines. The counter is updated based upon the selections made for issue. The counter is a saturating counter and its sign bit may be used as a thread preference signal when discriminating between two threads. The update made to the count value can be weighted depending upon programmable priorities associated with the respective threads as well as a weighting based upon the time taken to execute the type of operation selected.
摘要翻译：多线程处理器设置有饱和计数器，其用于产生线程偏好信号以引导选择哪些程序线程操作被从多个处理器管线中发出。计数器根据对问题的选择进行更新。计数器是饱和计数器，并且当识别两个线程时，其符号位可以用作线程偏好信号。对计数值进行的更新可以根据与相应线程相关联的可编程优先级加权，以及基于执行所选择的操作类型所花费的时间的加权。

69. 发明申请

US20090265514A1 Efficiency of cache memory operations 有权
标题翻译：高速缓存存储器操作的效率
公开(公告)号：US20090265514A1
公开(公告)日：2009-10-22
申请号：US12081583
申请日：2008-04-17
申请人： Stuart David Biles , Nigel Charles Paver , Chander Sudanthi , Timothy Charles Mace
发明人： Stuart David Biles , Nigel Charles Paver , Chander Sudanthi , Timothy Charles Mace
IPC分类号： G06F12/00
CPC分类号： G06F12/0804 , G06F12/0215 , G06F12/121 , G06F12/127
摘要： A processing system 1 including a memory 10 and a cache memory 4 is provided with a page status unit 40 for providing a cache controller with a page open indication indicating one or more open pages of data values in memory. At least one of one or more cache management operations performed by the cache controller is responsive to the page open indication so that the efficiency and/or speed of the processing system can be improved.
摘要翻译：包括存储器10和高速缓存存储器4的处理系统1设置有页面状态单元40，用于向高速缓存控制器提供指示存储器中数据值的一个或多个打开页面的页面打开指示。高速缓存控制器执行的一个或多个高速缓存管理操作中的至少一个响应于页面打开指示，从而可以提高处理系统的效率和/或速度。

70. 发明申请

US20090094439A1 Data processing apparatus and method employing multiple register sets 有权
标题翻译：采用多个寄存器组的数据处理装置和方法
公开(公告)号：US20090094439A1
公开(公告)日：2009-04-09
申请号：US11919757
申请日：2005-05-11
申请人： David Hennah Mansell , Stuart David Biles , David Michael Gilday , Danel Kershaw
发明人： David Hennah Mansell , Stuart David Biles , David Michael Gilday , Danel Kershaw
IPC分类号： G06F9/38 , G06F9/30 , G06F9/318
CPC分类号： G06F9/30123 , G06F9/3012 , G06F9/3851
摘要： A data processing apparatus and method employing multiple register sets is disclosed. The data processing apparatus has processing logic for performing data processing operations and a register bank for storing data associated with the processing logic. The register bank has at least one register group, each register group having a plurality of register sets. The processing logic has an operating state associated with each register group defining how that register group is used, a first operating state being a state in which each register set in the register group is used to support an independent execution thread of the processing logic, and a second operating state being a state in which the register sets of the register group are collectively used to support a single execution thread of the processing logic. Control logic is provided to control how the register sets of each register group are used dependent on the operating state associated with that register group. This has been found to provide a particularly efficient use of the registers within the data processing apparatus.
摘要翻译：公开了一种采用多个寄存器组的数据处理装置和方法。数据处理装置具有用于执行数据处理操作的处理逻辑和用于存储与处理逻辑相关联的数据的寄存器组。寄存器组具有至少一个寄存器组，每个寄存器组具有多个寄存器组。处理逻辑具有与定义如何使用该寄存器组的每个寄存器组相关联的操作状态，第一操作状态是其中在寄存器组中设置的每个寄存器用于支持处理逻辑的独立执行线程的状态，以及第二操作状态是将寄存器组的寄存器组集中用于支持处理逻辑的单个执行线程的状态。提供控制逻辑以根据与该寄存器组相关联的操作状态来控制如何使用每个寄存器组的寄存器组。已经发现这提供了数据处理装置内寄存器的特别有效的用途。

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