专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20090094439A1 Data processing apparatus and method employing multiple register sets 有权
标题翻译：采用多个寄存器组的数据处理装置和方法
公开(公告)号：US20090094439A1
公开(公告)日：2009-04-09
申请号：US11919757
申请日：2005-05-11
申请人： David Hennah Mansell , Stuart David Biles , David Michael Gilday , Danel Kershaw
发明人： David Hennah Mansell , Stuart David Biles , David Michael Gilday , Danel Kershaw
IPC分类号： G06F9/38 , G06F9/30 , G06F9/318
CPC分类号： G06F9/30123 , G06F9/3012 , G06F9/3851
摘要： A data processing apparatus and method employing multiple register sets is disclosed. The data processing apparatus has processing logic for performing data processing operations and a register bank for storing data associated with the processing logic. The register bank has at least one register group, each register group having a plurality of register sets. The processing logic has an operating state associated with each register group defining how that register group is used, a first operating state being a state in which each register set in the register group is used to support an independent execution thread of the processing logic, and a second operating state being a state in which the register sets of the register group are collectively used to support a single execution thread of the processing logic. Control logic is provided to control how the register sets of each register group are used dependent on the operating state associated with that register group. This has been found to provide a particularly efficient use of the registers within the data processing apparatus.
摘要翻译：公开了一种采用多个寄存器组的数据处理装置和方法。数据处理装置具有用于执行数据处理操作的处理逻辑和用于存储与处理逻辑相关联的数据的寄存器组。寄存器组具有至少一个寄存器组，每个寄存器组具有多个寄存器组。处理逻辑具有与定义如何使用该寄存器组的每个寄存器组相关联的操作状态，第一操作状态是其中在寄存器组中设置的每个寄存器用于支持处理逻辑的独立执行线程的状态，以及第二操作状态是将寄存器组的寄存器组集中用于支持处理逻辑的单个执行线程的状态。提供控制逻辑以根据与该寄存器组相关联的操作状态来控制如何使用每个寄存器组的寄存器组。已经发现这提供了数据处理装置内寄存器的特别有效的用途。

2. 发明授权

US08041930B2 Data processing apparatus and method for controlling thread access of register sets when selectively operating in secure and non-secure domains 有权
标题翻译：当选择性地在安全和非安全域中操作时，用于控制寄存器组的线程访问的数据处理装置和方法
公开(公告)号：US08041930B2
公开(公告)日：2011-10-18
申请号：US11919757
申请日：2005-05-11
申请人： David Hennah Mansell , Stuart David Biles , David Michael Gilday , Daniel Kershaw
发明人： David Hennah Mansell , Stuart David Biles , David Michael Gilday , Daniel Kershaw
IPC分类号： G06F9/00
CPC分类号： G06F9/30123 , G06F9/3012 , G06F9/3851
摘要： The data processing apparatus has processing logic for performing data processing operations and a register bank for storing data associated with the processing logic. The register bank has at least one register group, each register group having a plurality of register sets. The processing logic has an operating state associated with each register group defining how that register group is used, a first operating state being a state in which each register set in the register group is used to support an independent execution thread of the processing logic, and a second operating state being a state in which the register sets of the register group are collectively used to support a single execution thread of the processing logic. Control logic is provided to control how the register sets of each register group are used dependent on the operating state associated with that register group.
摘要翻译：数据处理装置具有用于执行数据处理操作的处理逻辑和用于存储与处理逻辑相关联的数据的寄存器组。寄存器组具有至少一个寄存器组，每个寄存器组具有多个寄存器组。处理逻辑具有与定义如何使用该寄存器组的每个寄存器组相关联的操作状态，第一操作状态是其中在寄存器组中设置的每个寄存器用于支持处理逻辑的独立执行线程的状态，以及第二操作状态是将寄存器组的寄存器组集中用于支持处理逻辑的单个执行线程的状态。提供控制逻辑以根据与该寄存器组相关联的操作状态来控制如何使用每个寄存器组的寄存器组。

3. 发明授权

US08826079B2 Data processing apparatus and method for identifying debug events 有权
标题翻译：用于识别调试事件的数据处理装置和方法
公开(公告)号：US08826079B2
公开(公告)日：2014-09-02
申请号：US13327989
申请日：2011-12-16
申请人： David Michael Gilday , Simon John Craske
发明人： David Michael Gilday , Simon John Craske
IPC分类号： G06F11/00 , G06F11/36
CPC分类号： G06F11/3636 , G06F11/3656
摘要： A data processing apparatus has at least one circuit block accessible for debugging by a debugger, the block having a set of debug status registers and a debug event register which is set by the circuit block to indicate occurrence of a debug event. Debug interface circuitry interfaces with the set of debug status registers for each circuit block. The circuitry includes at least a first portion which is in a first power domain that remains in a fully powered state while the debugger is connected to the circuitry. Status registers are provided in a second power domain which transitions between the fully powered state and at least one low power state while the debugger is connected to the circuitry. Content of the debug status registers is only accessible to the debugger when the second power domain is in the fully powered state.
摘要翻译：数据处理装置具有至少一个可由调试器进行调试的电路块，该块具有一组调试状态寄存器和由电路块设置的调试事件寄存器，以指示调试事件的发生。调试接口电路与每个电路块的一组调试状态寄存器相连接。该电路包括至少第一部分，该第一部分处于处于完全供电状态的第一功率域中，同时调试器连接到电路。状态寄存器被提供在第二功率域中，其在调试器连接到电路时在完全供电状态和至少一个低功率状态之间转换。当第二个电源域处于完全供电状态时，调试状态寄存器的内容只能由调试器访问。

4. 发明授权

US07617409B2 System for checking clock-signal correspondence 有权
标题翻译：用于检查时钟信号对应的系统
公开(公告)号：US07617409B2
公开(公告)日：2009-11-10
申请号：US11414551
申请日：2006-05-01
申请人： David Michael Gilday , Daryl Wayne Bradley , Edmond John Simon Ashfield
发明人： David Michael Gilday , Daryl Wayne Bradley , Edmond John Simon Ashfield
IPC分类号： G06F1/04 , G06F1/12 , G06F1/00 , H03K19/00 , H03K10/096
CPC分类号： G06F1/10 , H03K23/52
摘要： A data processing system is provided having a clock signal comparator comprising a reference input port for receiving a reference clock signal and at least a further input port for receiving respective further clock signal. Checking logic is provided within the clock signal comparator to check for a correspondence between the clock edge of the reference clock signal and a corresponding clock edge of the further clock signal within a predetermined time window. The checking logic is operable to check for the correspondence during operation of the data processing system. The clock-signal comparator can be provided on an integrated circuit or as part of the data processing apparatus having at least two different timing domains such as timing domains associated with two different instances of the same clock. Furthermore the clock-signal comparator is implemented in a hardware description language and integrated in a simulation of the operation of a data processing apparatus to detect timing errors that arise from numerical artifacts of the simulation as well as timing errors that arise from configuration and layout of the circuit elements of the data processing apparatus being simulated.
摘要翻译：提供一种数据处理系统，其具有时钟信号比较器，该时钟信号比较器包括用于接收参考时钟信号的参考输入端口和用于接收相应另外的时钟信号的至少另一输入端口在时钟信号比较器内提供校验逻辑，以在预定时间窗内检查参考时钟信号的时钟沿与另一时钟信号的对应时钟沿之间的对应关系。检查逻辑可操作以在数据处理系统的操作期间检查对应关系。时钟信号比较器可以被提供在集成电路上或作为数据处理装置的一部分，该数据处理装置具有至少两个不同的定时域，例如与相同时钟的两个不同实例相关联的定时域。此外，时钟信号比较器以硬件描述语言实现，并且集成在数据处理装置的操作的仿真中，以检测由仿真的数字伪像产生的定时误差以及由配置和布局引起的定时误差模拟数据处理装置的电路元件。

5. 发明授权

US08417915B2 Alias management within a virtually indexed and physically tagged cache memory 有权
标题翻译：虚拟索引和物理标记的高速缓存内存中的别名管理
公开(公告)号：US08417915B2
公开(公告)日：2013-04-09
申请号：US11197523
申请日：2005-08-05
申请人： David Michael Gilday , Richard Roy Grisenthwaite
发明人： David Michael Gilday , Richard Roy Grisenthwaite
IPC分类号： G06F12/00
CPC分类号： G06F12/1045 , G06F12/0864 , G06F12/1063
摘要： A virtually indexed and physically tagged memory is described having a cache way size which can exceed the minimum page table size such that aliased virtual addresses VA within the cache way 12 can be mapped to the same physical address PA. Aliasing management logic 10 permits multiple copies of the data from the same physical address to be stored at different virtual indexes within the cache within given or different cache ways.
摘要翻译：描述了虚拟索引和物理标记的存储器，其具有可以超过最小页表大小的高速缓存路径大小，使得高速缓存路径12内的别名虚拟地址VA可以映射到相同的物理地址PA。混叠管理逻辑10允许来自相同物理地址的数据的多个副本被存储在给定或不同的高速缓存方式内的高速缓存内的不同虚拟索引处。

6. 发明申请

US20100138640A1 Reset synchronisation 有权
标题翻译：重置同步
公开(公告)号：US20100138640A1
公开(公告)日：2010-06-03
申请号：US12314020
申请日：2008-12-02
申请人： David Michael Gilday , Peter Logan Harrod
发明人： David Michael Gilday , Peter Logan Harrod
IPC分类号： G06F15/177
CPC分类号： G06F1/24
摘要： Reset control circuitry is disclosed, for controlling a first reset signal for resetting at least a first portion of a circuit and a further reset signal for resetting at least a second portion of said circuit, said reset control circuitry comprising: an input for receiving an input first reset signal; an input for receiving an input further reset signal; an output for outputting an output first reset signal; and an output for outputting an output further reset signal; said reset control circuitry being responsive to detecting deassertion of said input first reset signal when said input further reset signal is asserted to delay deassertion of said output first reset signal so that said output first reset signal is deasserted at a same time or later than said input further reset signal.
摘要翻译：公开了复位控制电路，用于控制用于复位电路的至少第一部分的第一复位信号和用于复位所述电路的至少第二部分的另外的复位信号，所述复位控制电路包括：用于接收输入第一复位信号; 用于接收输入进一步复位信号的输入; 用于输出输出第一复位信号的输出; 以及用于输出输出进一步复位信号的输出; 所述复位控制电路响应于当所述输入进一步复位信号被确定以延迟所述输出第一复位信号的失效时检测到所述输入第一复位信号的失效，以使所述输出第一复位信号在所述输入的同时或晚于所述输入进一步复位信号。

7. 发明授权

US08055888B2 Initialisation of a pipelined processor 有权
标题翻译：流水线处理器的初始化
公开(公告)号：US08055888B2
公开(公告)日：2011-11-08
申请号：US12073049
申请日：2008-02-28
申请人： Chiloda Ashan Senerath Pathirane , David Michael Gilday
发明人： Chiloda Ashan Senerath Pathirane , David Michael Gilday
IPC分类号： G06F9/00 , G06F7/38 , G06F15/00
CPC分类号： G06F9/3802 , G06F9/3867 , G06F9/3869
摘要： A data processing apparatus is disclosed that comprises a pipelined processor, said pipelined processor comprising a processing pipeline for processing instructions in a plurality of stages, at least some of said plurality of stages each comprising storage elements for storing an instruction or decoded instruction being processed in said stage, said storage elements in at least one of said stages comprising settable elements, each of said settable elements being adapted to store a predetermined value in response to a wake up event, said settable elements being arranged such that in response to said wake up event said values stored in said settable elements form an instruction or decoded instruction.
摘要翻译：公开了一种包括流水线处理器的数据处理装置，所述流水线处理器包括用于处理多个级中的指令的处理流水线，所述多个级中的至少一些级包括用于存储正在处理的指令或解码指令的存储元件所述级，所述级中的至少一个级中的所述存储元件包括可设置元件，每个所述可设置元件适于响应于唤醒事件而存储预定值，所述可设置元件布置成响应于所述唤醒存储在所述可设置元件中的所述值表示指令或解码指令。

8. 发明申请

US20100241777A1 Power efficient interrupt detection 有权
标题翻译：高效的中断检测
公开(公告)号：US20100241777A1
公开(公告)日：2010-09-23
申请号：US12382751
申请日：2009-03-23
申请人： Mittu Xavier Kocherry , Simon John Craske , Chiloda Ashan Senerath Pathirane , David Michael Gilday
发明人： Mittu Xavier Kocherry , Simon John Craske , Chiloda Ashan Senerath Pathirane , David Michael Gilday
IPC分类号： G06F13/24
CPC分类号： G06F13/24 , Y02D10/14
摘要： Interrupt request detection circuitry is disclosed for detecting and outputting interrupt requests to a processor. The interrupt request detection circuitry comprises: an interrupt signal input for receiving an interrupt signal; an input for receiving a signal from the processor indicating whether the processor is currently processing an interrupt; a detection circuit for detecting an interrupt request and outputting an interrupt request signal to a data processing apparatus; disabling logic for disabling at least a portion of the detection circuitry; wherein in response to detecting the processor is currently processing an interrupt; the detection circuit is configured to detect a change in value of the interrupt signal caused by assertion of the interrupt signal indicating an interrupt request and to output an interrupt request signal to output circuitry in response to detecting the interrupt signal assertion; and in response to detecting the processor is not currently processing an interrupt; the disabling logic is configured to disable at least a portion of the detection circuit; and the detection circuit with the at least a portion disabled, is configured to output the interrupt signal as the interrupt request signal to the output circuitry.
摘要翻译：公开了用于检测并向处理器输出中断请求的中断请求检测电路。所述中断请求检测电路包括：用于接收中断信号的中断信号输入; 用于从处理器接收指示处理器当前正在处理中断的信号的输入; 检测电路，用于检测中断请求并向数据处理装置输出中断请求信号; 用于禁用所述检测电路的至少一部分的禁用逻辑; 其中响应于检测到所述处理器正在处理中断; 检测电路被配置为检测由断言指示中断请求的中断信号引起的中断信号的变化，并且响应于检测到中断信号断言而将中断请求信号输出到输出电路; 并且响应于检测到处理器当前未处理中断; 所述禁用逻辑被配置为禁用所述检测电路的至少一部分; 并且具有至少部分禁用的检测电路被配置为将中断信号作为中断请求信号输出到输出电路。

9. 发明申请

US20130159776A1 DATA PROCESSING APPARATUS AND METHOD FOR IDENTIFYING DEBUG EVENTS 有权
标题翻译：数据处理设备和识别调试事件的方法
公开(公告)号：US20130159776A1
公开(公告)日：2013-06-20
申请号：US13327989
申请日：2011-12-16
申请人： David Michael Gilday , Simon John Craske
发明人： David Michael Gilday , Simon John Craske
IPC分类号： G06F11/07
CPC分类号： G06F11/3636 , G06F11/3656
摘要： A data processing apparatus has at least one circuit block accessible for debugging by a debugger, the block having a set of debug status registers and a debug event register which is set by the circuit block to indicate occurrence of a debug event. Debug interface circuitry interfaces with the set of debug status registers for each circuit block. The circuitry includes at least a first portion which is in a first power domain that remains in a fully powered state whilst the debugger is connected to the circuitry. Status registers are provided in a second power domain which transitions between the fully powered state and at least one low power state whilst the debugger is connected to the circuitry. Content of the debug status registers is only accessible to the debugger when the second power domain is in the fully powered state.
摘要翻译：数据处理装置具有至少一个可由调试器进行调试的电路块，该块具有一组调试状态寄存器和由电路块设置的调试事件寄存器，以指示调试事件的发生。调试接口电路与每个电路块的一组调试状态寄存器相连接。该电路包括至少第一部分，该第一部分处于处于完全供电状态的第一功率域中，同时调试器连接到电路。在第二功率域中提供状态寄存器，其在调试器连接到电路时在完全供电状态和至少一个低功率状态之间转换。当第二个电源域处于完全供电状态时，调试状态寄存器的内容只能由调试器访问。

10. 发明授权

US08250351B2 Synchronization of two independent reset signals 有权
标题翻译：两个独立复位信号的同步
公开(公告)号：US08250351B2
公开(公告)日：2012-08-21
申请号：US12314020
申请日：2008-12-02
申请人： David Michael Gilday , Peter Logan Harrod
发明人： David Michael Gilday , Peter Logan Harrod
IPC分类号： G06F15/177
CPC分类号： G06F1/24
摘要： Reset control circuitry is disclosed, for controlling a first reset signal for resetting at least a first portion of a circuit and a further reset signal for resetting at least a second portion of said circuit, said reset control circuitry comprising: an input for receiving an input first reset signal; an input for receiving an input further reset signal; an output for outputting an output first reset signal; and an output for outputting an output further reset signal; said reset control circuitry being responsive to detecting deassertion of said input first reset signal when said input further reset signal is asserted to delay deassertion of said output first reset signal so that said output first reset signal is deasserted at a same time or later than said input further reset signal.
摘要翻译：公开了复位控制电路，用于控制用于复位电路的至少第一部分的第一复位信号和用于复位所述电路的至少第二部分的另外的复位信号，所述复位控制电路包括：用于接收输入第一复位信号; 用于接收输入进一步复位信号的输入; 用于输出输出第一复位信号的输出; 以及用于输出输出进一步复位信号的输出; 所述复位控制电路响应于当所述输入进一步复位信号被断言以延迟所述输出第一复位信号的失效时检测到所述输入第一复位信号的失效，使得所述输出第一复位信号在所述输入的同时或晚于所述输入进一步复位信号。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式