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61. 发明授权

US6005272A Trench transistor with source contact in trench 失效
标题翻译：沟槽中具有源极接触的沟槽晶体管
公开(公告)号：US6005272A
公开(公告)日：1999-12-21
申请号：US28894
申请日：1998-02-24
申请人： Mark I. Gardner , Daniel Kadosh , Frederick N. Hause
发明人： Mark I. Gardner , Daniel Kadosh , Frederick N. Hause
IPC分类号： H01L21/28 , H01L21/336 , H01L29/78 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113
CPC分类号： H01L29/66613 , H01L21/28114 , H01L29/66621 , H01L29/66659 , H01L29/7834
摘要： An IGFET with a gate electrode and a source contact in a trench is disclosed. The IGFET includes a trench with opposing sidewalls and a bottom surface in a semiconductor substrate, a gate insulator on the bottom surface, a gate electrode on the gate insulator, a source contact on the bottom surface, insulative spacers between the gate electrode, the source contact and the sidewalls, and a source and drain adjacent to the bottom surface. Advantageously, the source contact overlaps the trench, thereby improving packing density.
摘要翻译：公开了具有沟槽中的栅电极和源极接触的IGFET。 IGFET包括具有相对侧壁和半导体衬底中的底表面的沟槽，底表面上的栅极绝缘体，栅极绝缘体上的栅电极，底表面上的源极接触，栅电极，源极之间的绝缘间隔接触和侧壁，以及与底表面相邻的源极和漏极。有利地，源极接触与沟槽重叠，从而改善了堆积密度。

62. 发明授权

US5994779A Semiconductor fabrication employing a spacer metallization technique 失效
标题翻译：采用间隔金属化技术的半导体制造
公开(公告)号：US5994779A
公开(公告)日：1999-11-30
申请号：US850253
申请日：1997-05-02
申请人： Mark I. Gardner , Daniel Kadosh , Fred N. Hause
发明人： Mark I. Gardner , Daniel Kadosh , Fred N. Hause
IPC分类号： H01L21/768 , H01L23/528
CPC分类号： H01L21/76885 , H01L21/76838 , H01L23/5283 , H01L2924/0002
摘要： An integrated circuit fabrication process is provided in which an interconnect having a least one vertical sidewall surface is formed. The interconnect thusly formed allows for higher packing density within the ensuring integrated circuit since the interconnect requires less space to accommodate the same current density as an interconnect having sloped (i.e., non-vertical) sidewall surfaces. A semiconductor topography is provided which includes transistors arranged upon and within a silicon-based substrate. A first interlevel dielectric is deposited across the semiconductor topography, and portions of the dielectric are removed to form vias to select portions of the transistors. Conductive plugs are formed exclusively within the vias. An insulating material patterned with vertical sidewall surfaces is then formed across the first interlevel dielectric and a portion of the plugs. The insulating material is then patterned. Conductive material is then deposited across the patterned insulating material, the plug upper surfaces, and the first interlevel dielectric. A portion of the conductive material is anisotropically removed to form interconnects which are laterally adjacent to the sidewall surfaces of the insulating material. Each interconnect includes two surfaces, one of which is vertical to the underlying topography and the other of which extends a distance from the fist surface and links with an upper region of the surface in an arcuate pattern. The first lateral surface of the interconnect is directly adjacent to a sidewall surface of the insulating material and is therefore intended to be vertical. The second lateral surface extends a distance from the first lateral surface, constrained the limitations of deposition and not lithography.
摘要翻译：提供一种集成电路制造工艺，其中形成具有至少一个垂直侧壁表面的互连。这样形成的互连允许在确保集成电路内的更高的封装密度，因为互连需要更少的空间以适应与具有倾斜（即，非垂直）侧壁表面的互连件相同的电流密度。提供半导体形貌，其包括布置在硅基衬底上和内部的晶体管。第一层间电介质淀积跨半导体形貌，去除电介质的部分以形成通孔以选择晶体管的部分。导电插头仅在通孔内形成。然后，跨越第一层间电介质和一部分插塞形成图案化有垂直侧壁表面的绝缘材料。然后将绝缘材料图案化。导电材料然后沉积在图案化的绝缘材料，插塞上表面和第一层间电介质上。导电材料的一部分被各向异性地去除以形成横向邻近绝缘材料的侧壁表面的互连。每个互连包括两个表面，其中一个垂直于下面的地形，另一个表面与第一表面延伸一段距离，并以弓形图案与表面的上部区域连接。互连的第一侧表面直接邻近绝缘材料的侧壁表面，因此意图是垂直的。第二侧表面从第一侧表面延伸一段距离，限制了沉积的限制，而不是光刻。

63. 发明授权

US5949092A Ultra-high-density pass gate using dual stacked transistors having a gate structure with planarized upper surface in relation to interlayer insulator 失效
标题翻译：使用具有相对于层间绝缘体的平坦化上表面的栅极结构的双重堆叠晶体管的超高密度栅极
公开(公告)号：US5949092A
公开(公告)日：1999-09-07
申请号：US905486
申请日：1997-08-01
申请人： Daniel Kadosh , Mark I. Gardner , Michael Duane
发明人： Daniel Kadosh , Mark I. Gardner , Michael Duane
IPC分类号： H01L21/822 , H01L27/06 , H01L29/78
CPC分类号： H01L21/8221 , H01L27/0688
摘要： A multi-dimensional transistor structure is fabricated which includes a base transistor substrate upon which transistors are formed. An elevated substrate is formed overlying the base transistor and having an oxide isolation formed in localized regions beneath the elevated substrate but overlying the base transistor substrate. A plurality of transistors are formed on a substrate wafer to form a base-level transistor formation. An intralevel dielectric (ILD) layer is deposited overlying the base-level transistor formation. Overlying the ILD layer, a "sandwich" structure is formed with the deposition of a first polysilicon layer, deposition of an oxide isolation layer, and deposition of a second polysilicon layer. The median oxide isolation layer is patterned and etched according to a localized oxide isolation mask in a configuration determined by the position of transistors in the base-level transistor formation and by the planned position of transistors, that are not yet formed, in an overlying elevated substrate level. The median oxide isolation layer is patterned and etched in a configuration so that isolation is achieved in a predetermined manner, for example, on an individual transistor basis, a transistor group basis, or the like. The resulting electronic integrated circuit structure is used for high speed circuit applications due to high packing densities and small distances between devices.
摘要翻译：制造了多维晶体管结构，其包括形成晶体管的基极晶体管基板。形成了一个升高的衬底，覆盖着基极晶体管，并且在升高的衬底下方的局部区域中形成氧化物隔离层，但覆盖在基极晶体管衬底上。在衬底晶片上形成多个晶体管，以形成基极晶体管结构。层叠电介质（ILD）层沉积在基极晶体管结构之上。覆盖ILD层，通过第一多晶硅层的沉积，氧化物隔离层的沉积和第二多晶硅层的沉积形成“三明治”结构。根据局部氧化物隔离掩模对中间氧化物隔离层进行构图和蚀刻，该隔离掩模的形状由基极晶体管形成中的晶体管的位置和尚未形成的晶体管的预定位置确定底物水平。对中间氧化物隔离层进行图案化和蚀刻，以使得以预定的方式实现隔离，例如基于单个晶体管，基于晶体管组等。所得的电子集成电路结构由于高封装密度和器件之间的距离小而用于高速电路应用。

64. 发明授权

US5933721A Method for fabricating differential threshold voltage transistor pair 失效
标题翻译：差分阈值电压晶体管对的制造方法
公开(公告)号：US5933721A
公开(公告)日：1999-08-03
申请号：US837580
申请日：1997-04-21
申请人： Frederick N. Hause , Mark I. Gardner , Daniel Kadosh
发明人： Frederick N. Hause , Mark I. Gardner , Daniel Kadosh
IPC分类号： H01L21/8238 , H01L21/60
CPC分类号： H01L21/823828 , H01L21/823807
摘要： A method of establishing a differential threshold voltage during the fabrication of first and second IGFETs having like conductivity type is disclosed. A dopant is introduced into the gate electrode of each transistor of the pair. The dopant is differentially diffused into respective channel regions to provide a differential dopant concentration therebetween, which results in a differential threshold voltage between the two transistors. One embodiment includes introducing a diffusion-retarding material, such as nitrogen, into the first gate electrode before the dopant is diffused into the respective channel regions, and without introducing a significant amount of the diffusion-retarding material into the second gate electrode. Advantageously, a single dopant implant can provide both threshold voltage values. The two threshold voltages may be chosen to provide various combinations of enhancement mode and depletion mode IGFETs.
摘要翻译：公开了在具有类似导电类型的第一和第二IGFET的制造期间建立差分阈值电压的方法。将掺杂剂引入该对的每个晶体管的栅电极。掺杂剂差异扩散到各个沟道区域中以在其间提供差分掺杂剂浓度，这导致两个晶体管之间的差分阈值电压。一个实施例包括在掺杂剂扩散到各个沟道区域之前将诸如氮的扩散阻滞材料引入第一栅电极中，并且不将大量的扩散阻滞材料引入第二栅电极。有利地，单个掺杂剂注入可以提供两个阈值电压值。可以选择两个阈值电压以提供增强模式和耗尽模式IGFET的各种组合。

65. 发明授权

US5923982A Method of making asymmetrical transistor with lightly and heavily doped drain regions and ultra-heavily doped source region using two source/drain implant steps 失效
标题翻译：使用两个源极/漏极注入步骤制造具有轻掺杂和重掺杂漏极区域和超重掺杂源极区域的不对称晶体管的方法
公开(公告)号：US5923982A
公开(公告)日：1999-07-13
申请号：US837526
申请日：1997-04-21
申请人： Daniel Kadosh , Mark I. Gardner , Robert Dawson
发明人： Daniel Kadosh , Mark I. Gardner , Robert Dawson
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/66659 , H01L29/7835
摘要： A method of making the IGFET includes providing a semiconductor substrate, providing a gate over the semiconductor substrate, implanting lightly doped source and drain regions into the substrate, forming a source-side spacer and a drain-side spacer in close proximity to opposing sidewalls of the gate, forming a masking layer that covers the drain-side spacer and includes an opening over the source-side spacer, removing the source-side spacer, and implanting a heavily doped drain region and an ultra-heavily doped source region into the substrate after removing the source-side spacer while the drain-side spacer is present, wherein the heavily doped drain region is implanted through the masking layer and the ultra-heavily doped source region is implanted through the opening in the masking layer. Accordingly, the ultra-heavily doped source region has a greater doping concentration than that of the heavily doped drain region due to the masking layer, and a portion of the lightly doped drain region is protected from the second source/drain implant step due to the drain-side spacer. Advantageously, the IGFET has low source-drain series resistance and reduces hot carrier effects.
摘要翻译：制造IGFET的方法包括提供半导体衬底，在半导体衬底上提供栅极，将轻掺杂的源极和漏极区域注入到衬底中，形成源极间隔物和漏极侧间隔物，所述栅极形成覆盖所述漏极侧间隔物的掩模层，并且包括在所述源极间隔物上的开口，去除所述源极间隔物，以及将重掺杂漏极区域和超重掺杂源极区域注入到所述衬底中在漏极侧间隔物存在时去除源极间隔物之后，其中通过掩模层注入重掺杂漏极区，并且通过掩模层中的开口注入超重掺杂源极区。因此，由于掩模层，超重掺杂源极区域具有比重掺杂漏极区域更大的掺杂浓度，并且轻掺杂漏极区域的一部分被保护免受第二源极/漏极注入步骤的影响，这是由于排水侧间隔件。有利地，IGFET具有低的源极 - 漏极串联电阻并且降低热载流子效应。

66. 发明授权

US5909622A Asymmetrical p-channel transistor formed by nitrided oxide and large tilt angle LDD implant 失效
标题翻译：由氮化氧化物和大倾角LDD植入物形成的非对称p沟道晶体管
公开(公告)号：US5909622A
公开(公告)日：1999-06-01
申请号：US720732
申请日：1996-10-01
申请人： Daniel Kadosh , Mark I. Gardner
发明人： Daniel Kadosh , Mark I. Gardner
IPC分类号： H01L21/28 , H01L21/336 , H01L29/49 , H01L29/78
CPC分类号： H01L21/28035 , H01L21/28176 , H01L29/4916 , H01L29/66659 , H01L29/7835 , H01L29/7836
摘要： Various processes are provided for producing a p-channel and/or n-channel transistor. The present processes are thereby applicable to NMOS, PMOS or CMOS integrated circuits, any of which derive a benefit from having an asymmetrical LDD structure. The asymmetrical structure can be produced on a p-channel or n-channel transistor in various ways. According, the present process employs various techniques to form an asymmetrical transistor. The various techniques employ processing steps which vary depending upon the LDD result desired. First, the LDD implant can be performed only in the drain-side of the channel, or in the drain-side as well as the source-side. Second, the gate conductor sidewall surface adjacent the drain can be made thicker than the sidewall surface adjacent the source. Thickening of the drain-side sidewall spacer can be achieved either by depositing oxide upon a nitride-bearing film, or by growing additional oxide upon an exposed silicon surface having the source-side sidewall protected from growth. Third, the drain-side can be enhanced relative to the source-side by using an LTA implant. There may be numerous other modifications and alternative processing steps, all of which are described herein. Regardless of the sequence chosen, a barrier implant may be employed to prevent deleterious ingress of p-type implant species into the channel region. The present fabrication sequence reduces source-side resistance to enhance drive current--a desirable outcome for high speed circuits.
摘要翻译：提供了用于产生p沟道和/或n沟道晶体管的各种工艺。因此，本发明的方法可应用于NMOS，PMOS或CMOS集成电路，其中任何一种从具有不对称的LDD结构中获益。可以以各种方式在p沟道或n沟道晶体管上产生非对称结构。据此，本方法采用各种技术形成不对称晶体管。各种技术采用根据所需LDD结果而变化的处理步骤。首先，LDD注入仅能够在沟道的漏极侧，或者在漏极侧以及源极侧进行。第二，与漏极相邻的栅极导体侧壁表面可以制成比邻近源极的侧壁表面更厚。漏极侧壁间隔物的增厚可以通过在氮化物承载膜上沉积氧化物，或通过在具有源极侧壁保护生长的暴露的硅表面上生长另外的氧化物来实现。第三，可以通过使用LTA植入物相对于源极侧的漏极侧增强。可以存在许多其它修改和替代的处理步骤，其全部在此描述。不管选择的顺序如何，可以使用阻挡植入物来防止p型植入物质进入通道区域的有害进入。本制造顺序降低了源极电阻以增强驱动电流 - 高速电路的期望结果。

67. 发明授权

US5888853A Integrated circuit including a graded grain structure for enhanced transistor formation and fabrication method thereof 失效
标题翻译：包括用于增强晶体管形成的渐变晶粒结构的集成电路及其制造方法
公开(公告)号：US5888853A
公开(公告)日：1999-03-30
申请号：US905482
申请日：1997-08-01
申请人： Mark I. Gardner , Daniel Kadosh , Michael Duane
发明人： Mark I. Gardner , Daniel Kadosh , Michael Duane
IPC分类号： H01L21/205 , H01L21/336 , H01L21/822 , H01L21/8238 , H01L21/00 , H01L21/84
CPC分类号： H01L29/66757 , H01L21/02381 , H01L21/02532 , H01L21/0262 , H01L21/02639 , H01L21/8221 , H01L21/8238 , H01L29/66772
摘要： An elevated transistor formation includes a plurality of planes upon which transistors are formed. The plurality of transistor planes are formed at multiple relative elevations overlying a substrate wafer using deposited polysilicon to form a substrate between the layers. The polysilicon is deposited in a multiple-grain form to achieve an advantageous balance between deposition rate and substrate quality. In particular, columnar polysilicon is deposited at a temperature of approximately 620.degree. C. and above to achieve a high deposition rate directly overlying a lower-elevation transistor plane. High quality polysilicon is then deposited overlying the columnar polysilicon layer at a temperature of approximately 580.degree. C. or below. The deposition rate for high quality polysilicon is substantially lower than the deposition rate for columnar polysilicon. The highest quality substrate, upon which transistors in an elevated transistor plane are formed, is amorphous polysilicon.
摘要翻译：升高的晶体管形成包括形成晶体管的多个平面。多个晶体管平面在沉积的多晶硅上形成在覆盖衬底晶片的多个相对高度处以在层之间形成衬底。多晶硅以多晶粒形式沉积以实现沉积速率和衬底质量之间的有利平衡。特别地，在约620℃及以上的温度下沉积柱状多晶硅，以实现直接覆盖较低仰角晶体管平面的高沉积速率。然后在大约580℃或更低的温度下将高品质多晶硅沉积在柱状多晶硅层上。高质量多晶硅的沉积速率明显低于柱状多晶硅的沉积速率。形成高架晶体管平面的晶体管的最高质量的衬底是无定形多晶硅。

68. 发明授权

US5874341A Method of forming trench transistor with source contact in trench 失效
标题翻译：在沟槽中形成具有源极接触的沟槽晶体管的方法
公开(公告)号：US5874341A
公开(公告)日：1999-02-23
申请号：US739567
申请日：1996-10-30
申请人： Mark I. Gardner , Daniel Kadosh , Frederick N. Hause
发明人： Mark I. Gardner , Daniel Kadosh , Frederick N. Hause
IPC分类号： H01L21/28 , H01L21/336 , H01L29/78
CPC分类号： H01L29/66613 , H01L21/28114 , H01L29/66621 , H01L29/66659 , H01L29/7834
摘要： An IGFET with a gate electrode and a source contact in a trench is disclosed. The IGFET includes a trench with opposing sidewalls and a bottom surface in a semiconductor substrate, a gate insulator on the bottom surface, a gate electrode on the gate insulator, a source contact on the bottom surface, insulative spacers between the gate electrode, the source contact and the sidewalls, and a source and drain adjacent to the bottom surface. A method of forming an IGFET includes forming a trench with first and second opposing sidewalls and a bottom surface in a substrate, forming disposable spacers on the bottom surface, forming a gate insulator material on the bottom surface between the disposable spacers, depositing a gate electrode material on the gate insulator material and disposable spacers, polishing the gate electrode material and then anisotropically etching a lateral portion of the gate electrode material and gate insulator material to form the gate electrode and gate insulator, removing the disposable spacers, forming a first insulative spacer adjacent to the first sidewall, a second insulative spacer adjacent to the gate electrode and second sidewall, and a third insulative spacer adjacent to the gate electrode such that a contact portion of the bottom surface between the first and third insulative spacers is exposed, forming a source and drain in the substrate and adjacent to the bottom surface, and forming source and drain contacts such that the source contact is electrically coupled to the source at the contact portion of the bottom surface and the drain contact is electrically coupled to the drain at the top surface of the substrate. Advantageously, the source contact overlaps the trench, thereby improving packing density.
摘要翻译：公开了具有沟槽中的栅电极和源极接触的IGFET。 IGFET包括具有相对侧壁和半导体衬底中的底表面的沟槽，底表面上的栅极绝缘体，栅极绝缘体上的栅电极，底表面上的源极接触，栅电极，源极之间的绝缘间隔接触和侧壁，以及与底表面相邻的源极和漏极。形成IGFET的方法包括在基板中形成具有第一和第二相对侧壁和底表面的沟槽，在底表面上形成一次性间隔物，在一次性间隔物之间的底表面上形成栅极绝缘体材料，沉积栅电极栅极绝缘体材料和一次性间隔物上的材料，抛光栅电极材料，然后各向异性地蚀刻栅极电极材料和栅极绝缘体材料的侧向部分以形成栅电极和栅极绝缘体，去除一次性间隔物，形成第一绝缘间隔物与第一侧壁相邻的第二绝缘间隔件，与栅电极和第二侧壁相邻的第二绝缘间隔件，以及与栅电极相邻的第三绝缘间隔件，使得第一和第三绝缘间隔件之间的底表面的接触部分露出，形成源极和漏极在衬底中并且邻近底面，并且形成尿液和漏极接触，使得源极接触件在底表面的接触部分处电耦合到源极，并且漏极接触件电耦合到衬底顶表面处的漏极。有利地，源极接触与沟槽重叠，从而改善了堆积密度。

69. 发明授权

US06358828B1 Ultra high density series-connected transistors formed on separate elevational levels 失效
标题翻译：超高密度串联晶体管形成在不同的高程
公开(公告)号：US06358828B1
公开(公告)日：2002-03-19
申请号：US09118514
申请日：1998-07-17
申请人： Daniel Kadosh , Mark I. Gardner
发明人： Daniel Kadosh , Mark I. Gardner
IPC分类号： H01L213205
CPC分类号： H01L27/0688
摘要： A three-dimensional integrated circuit and fabrication process is provided for producing active and passive devices on various levels of the integrated circuit. The present process is particularly suited to interconnecting a source of one transistor to a drain of another to form series-connected transistors often employed in core logic units. A junction of an underlying transistor can be connected to a junction of an overlying transistor, with both transistors separated by an interlevel dielectric. The lower transistor junction is connected to the upper level transistor junction using a plug conductor. The plug conductor and, more specifically, the mutually connected junction, is further coupled to a laterally extended interconnect. The interconnect extends from the mutual connection point of the plug conductor to a substrate of the overlying transistor. Accordingly, the source and substrate of the overlying transistor can be connected to a drain of the underlying transistor to not only achieve series-connection but also to connect the source and substrate of an internally configured transistor for the purpose of reducing body effects.
摘要翻译：提供三维集成电路和制造工艺，用于在集成电路的各种级别上产生有源和无源器件。本方法特别适用于将一个晶体管的源极互连到另一个晶体管的漏极，以形成通常用于核心逻辑单元的串联连接的晶体管。底层晶体管的结可以连接到上覆晶体管的结，两个晶体管由层间电介质分隔开。下部晶体管结使用插头导体连接到上层晶体管结。插头导体，更确切地说，相互连接的连接部分进一步耦合到横向延伸的互连。互连从插头导体的相互连接点延伸到上覆晶体管的衬底。因此，覆盖晶体管的源极和衬底可以连接到下面的晶体管的漏极，以便不仅实现串联连接，而且连接内部构造的晶体管的源极和衬底以减少体效应。

70. 发明授权

US6096591A Method of making an IGFET and a protected resistor with reduced processing steps 失效
标题翻译：制造IGFET和受保护电阻的方法，减少加工步骤
公开(公告)号：US6096591A
公开(公告)日：2000-08-01
申请号：US911746
申请日：1997-08-15
申请人： Mark I. Gardner , Daniel Kadosh , Derick J. Wristers
发明人： Mark I. Gardner , Daniel Kadosh , Derick J. Wristers
IPC分类号： H01L21/02 , H01L27/06 , H01L21/8234
CPC分类号： H01L28/20 , H01L27/0629
摘要： A method of making an IGFET and a protected resistor includes providing a semiconductor substrate with an active region and a resistor region, forming a gate over the active region, forming a diffused resistor in the resistor region, forming an insulating layer over the gate and the diffused resistor, forming a masking layer over the insulating layer that covers the resistor region and includes an opening above the active region, applying an etch using the masking layer as an etch mask so that unetched portions of the insulating layer over the active region form spacers in close proximity to opposing sidewalls of the gate and an unetched portion of the insulating layer over the resistor region forms a resistor-protect insulator, and forming a source and a drain in the active region. In this manner, a single insulating layer provides both sidewall spacers for the gate and a resistor-protect insulator for the diffused resistor.
摘要翻译：制造IGFET和受保护电阻器的方法包括向半导体衬底提供有源区和电阻区，在有源区上形成栅极，在电阻区中形成扩散电阻，在栅极上形成绝缘层，扩散电阻器，在覆盖电阻器区域的绝缘层上形成掩模层，并且在有源区域上方包括开口，使用掩模层施加蚀刻作为蚀刻掩模，使得在有源区域上的绝缘层的未蚀刻部分形成间隔物靠近栅极的相对侧壁并且在电阻器区域上的绝缘层的未蚀刻部分形成电阻器保护绝缘体，并且在有源区域中形成源极和漏极。以这种方式，单个绝缘层提供用于栅极的两个侧壁间隔件和用于扩散电阻器的电阻保护绝缘体。

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