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61. 发明授权

US07268570B1 Apparatus and method for customized burn-in of cores on a multicore microprocessor integrated circuit chip 失效
标题翻译：在多核微处理器集成电路芯片上定制化核心的装置和方法
公开(公告)号：US07268570B1
公开(公告)日：2007-09-11
申请号：US11426646
申请日：2006-06-27
申请人： Jean Audet , Louis B. Capps, Jr. , Glenn G. Daves , Joanne Ferris , Anand Haridass , Ronald E. Newhart , Michael J. Shapiro
发明人： Jean Audet , Louis B. Capps, Jr. , Glenn G. Daves , Joanne Ferris , Anand Haridass , Ronald E. Newhart , Michael J. Shapiro
IPC分类号： G01R31/02
CPC分类号： G01R31/2855
摘要： An apparatus and method for providing a multi-core integrated circuit chip that reduces the cost of the package and board while optimizing performance of the cores for use with a single voltage plane. The apparatus and method of the illustrative embodiments make use of a dynamic burn-in technique that optimizes all of the cores on the chip to run at peak performance at a single voltage. Each core is burned-in with a customized burn-in voltage that provides uniform power and performance across the whole chip. This results in a higher burn-in yield and lower overall power in the integrated circuit chip. The optimization of the cores to run at peak performance at a single voltage is achieved through use of the negative bias temperature instability affects on the cores imparted by the burn-in voltages applied.
摘要翻译：一种用于提供多核集成电路芯片的装置和方法，其降低了封装和板的成本，同时优化用于单个电压平面的芯的性能。说明性实施例的装置和方法使用动态老化技术，其优化芯片上的所有核心以在单个电压下以峰值性能运行。每个核心都具有定制的老化电压，可在整个芯片上提供均匀的功率和性能。这导致集成电路芯片中更高的老化成本和更低的总功率。通过使用负偏置温度不稳定性影响由所施加的老化电压施加的磁芯，可以实现在单电压下以峰值性能运行的磁芯的优化。

62. 发明授权

US08407644B2 Reducing crosstalk in the design of module nets 有权
标题翻译：减少模块网设计中的串扰
公开(公告)号：US08407644B2
公开(公告)日：2013-03-26
申请号：US12537767
申请日：2009-08-07
申请人： Dulce M. Altabella Cabrera , Sungjun Chun , Anand Haridass , Tingdong Zhou
发明人： Dulce M. Altabella Cabrera , Sungjun Chun , Anand Haridass , Tingdong Zhou
IPC分类号： G06F17/50
CPC分类号： H01L23/5386 , G06F17/5077 , G06F2217/82 , H01L23/5222 , H01L23/552 , H01L25/0655 , H01L2224/16227 , H01L2224/16235 , H01L2924/15192
摘要： A method, a system and a computer program product for reducing coupling noise in low loss on-module wires used for connecting module components in electrical circuits/devices. During the design stage, an Enhanced Crosstalk Reduction (ECR) utility identifies interconnect wires as driven/aggressor traces or receiver traces. The ECR utility substantially avoids forward crosstalk in a victim trace by specially arranging driver traces adjacent to the receiver victim trace in order to provide a lower level and saturated level of backward crosstalk. In particular, the ECR utility provided a configuration of wire/trace layers based on one or more of: (a) the crosstalk impact of a trace when positioned in a particular location; (b) the crosstalk impact of the trace upon remaining components based on placement in the particular location; and (c) system component specifications. In addition, the ECR utility reduces crosstalk by providing a configuration of receiver wires and transmitter wires without the use of isolation layers.
摘要翻译：一种用于减少用于连接电路/设备中的模块部件的低损耗模块电线中的耦合噪声的方法，系统和计算机程序产品。在设计阶段，增强型串扰降低（ECR）实用程序将互连导线识别为驱动/侵入轨迹或接收器迹线。 ECR实用程序通过专门布置与接收器受害者跟踪相邻的驱动器迹线，基本上避免了受害者跟踪中的前向串扰，以便提供较低级别和饱和的后向串扰水平。特别地，ECR实用程序基于以下中的一个或多个提供了线/迹线层的配置：（a）当定位在特定位置时迹线的串扰影响; （b）基于在特定位置的放置，迹线对剩余部件的串扰影响; 和（c）系统组件规格。此外，ECR实用程序通过提供接收器线和发射器线的配置来减少串扰，而不使用隔离层。

63. 发明申请

US20120331429A1 CIRCUIT MANUFACTURING AND DESIGN TECHNIQUES FOR REFERENCE PLANE VOIDS WITH STRIP SEGMENT 失效
标题翻译：具有条带划分的参考平面电路的电路制造和设计技术
公开(公告)号：US20120331429A1
公开(公告)日：2012-12-27
申请号：US13603732
申请日：2012-09-05
申请人： Sungjun Chun , Anand Haridass , Roger D. Weekly
发明人： Sungjun Chun , Anand Haridass , Roger D. Weekly
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , H05K1/0219 , H05K1/0237 , H05K1/0253 , H05K3/4602 , H05K3/4652 , H05K2201/09536 , H05K2201/09672 , H05K2201/0969 , H05K2201/09718 , Y10T29/49117 , Y10T29/49153 , Y10T29/49155 , Y10T29/49165 , Y10T428/24322
摘要： Manufacturing circuits with reference plane voids over vias with a strip segment interconnect permits routing critical signal paths over vias, while increasing via insertion capacitance only slightly. The transmission line reference plane defines voids above (or below) signal-bearing plated-through holes (PTHs) that pass through a rigid substrate core, so that the signals are not degraded by an impedance mismatch that would otherwise be caused by shunt capacitance from the top (or bottom) of the signal-bearing PTHs to the transmission line reference plane. In order to provide increased routing density, signal paths are routed over the voids, but disruption of the signal paths by the voids is prevented by including a conductive strip through the voids that reduces the coupling to the signal-bearing PTHs and maintains the impedance of the signal path conductor.
摘要翻译：具有带状段互连的通孔上的参考平面空隙的制造电路允许在通孔上路由关键信号路径，同时仅通过插入电容略微增加。传输线参考平面定义了通过刚性衬底芯的信号承载电镀通孔（PTH）上方（或下方）的空隙，使得信号不会被阻抗失配降级，否则会由分流电容引起信号承载PTH的顶部（或底部）到传输线参考平面。为了提供增加的布线密度，信号路径被布置在空隙上，但是通过将导电条包括通过空隙来防止由空隙引起的信号路径的破坏，从而减小与信号承载PTH的耦合并维持信号路径导体。

64. 发明授权

US08018837B2 Self-healing chip-to-chip interface 失效
标题翻译：自愈芯片到芯片的接口
公开(公告)号：US08018837B2
公开(公告)日：2011-09-13
申请号：US12635121
申请日：2009-12-10
申请人： Wiren D. Becker , Daniel M. Dreps , Frank D. Ferraiolo , Anand Haridass , Robert J. Reese
发明人： Wiren D. Becker , Daniel M. Dreps , Frank D. Ferraiolo , Anand Haridass , Robert J. Reese
IPC分类号： G01R31/08
CPC分类号： H01L22/22 , H01L2924/0002 , H01L2924/00
摘要： A method, apparatus, and computer instructions for managing a set of signal paths for a chip. A defective signal path within the set of signal paths for the chip is detected. Signals are re-routed through the set of signal paths such that the defective signal path is removed from the set of signal paths and sending signals using remaining data signal paths in the set of signal paths and using an extra signal path in response to detecting the defective signal path.
摘要翻译：一种用于管理用于芯片的一组信号路径的方法，装置和计算机指令。检测用于芯片的信号路径集合内的有缺陷的信号路径。信号通过一组信号路径重新路由，使得有缺陷的信号路径从信号路径集合中移除，并使用信号路径组中的剩余数据信号路径发送信号，并且响应于检测到的信号路径有缺陷的信号路径。

65. 发明授权

US07930129B2 Uniform power density across processor cores at burn-in 有权
标题翻译：老化时处理器内核的功率密度均匀
公开(公告)号：US07930129B2
公开(公告)日：2011-04-19
申请号：US12114032
申请日：2008-05-02
申请人： Louis Bennie Capps, Jr. , Anand Haridass , Ronald Edward Newhart , Michael J. Shapiro
发明人： Louis Bennie Capps, Jr. , Anand Haridass , Ronald Edward Newhart , Michael J. Shapiro
IPC分类号： G01R31/00 , G01R21/00
CPC分类号： G01R31/2868
摘要： A computer implemented method, data processing system, and computer usable code are provided for burn-in testing of a multiprocessor. A process identifies a power management data set for a plurality of processor cores associated with the multiprocessor. The process selects one or more of the plurality of processor cores to form a selected set of processor cores based upon the power management data set. The process initiates a burn-in test across the selected set of processor cores. In response to a determination that all processor cores in the plurality of processor cores have not been selected, the process repeats the above selecting and initiating steps until all the processor cores have been selected.
摘要翻译：提供计算机实现的方法，数据处理系统和计算机可用代码用于多处理器的老化测试。过程识别与多处理器相关联的多个处理器核心的功率管理数据集。该过程基于电源管理数据集选择多个处理器核中的一个或多个来形成选定的一组处理器核。该过程在所选的一组处理器核心上启动老化测试。响应于确定多个处理器核心中的所有处理器核心未被选择，该过程重复上述选择和启动步骤，直到所有处理器核心已被选择为止。

66. 发明授权

US07868608B2 Detecting open ground connections in surface mount connectors 失效
标题翻译：检测表面贴装连接器中的开放接地连接
公开(公告)号：US07868608B2
公开(公告)日：2011-01-11
申请号：US12420089
申请日：2009-04-08
申请人： Anand Haridass , Jesus Montanez , Xiaomin Shen , Sungjun Chun
发明人： Anand Haridass , Jesus Montanez , Xiaomin Shen , Sungjun Chun
IPC分类号： G01R31/28
CPC分类号： G01R31/026 , G01R31/043 , G01R31/2812 , H05K3/341
摘要： A device may include a current source for connecting to a printed circuit board. The device may also include a first FET switch pack and a second FET switch pack for connecting to the surface mount connector of the printed circuit board. Additionally, the device may include a FET controller connected to the first FET switch pack and the second FET switch pack. The FET controller may be utilized for connecting a first FET and a second FET to the first region of the surface mount connector. The FET controller may be configured for supplying the current to the first region of the surface mount connector to produce at least one continuous heat signature characteristic of an improperly connected ground pin. A thermal monitoring module may be used to identify the improper physical connection.
摘要翻译：设备可以包括用于连接到印刷电路板的电流源。该装置还可以包括用于连接到印刷电路板的表面安装连接器的第一FET开关组件和第二FET开关组件。另外，该装置可以包括连接到第一FET开关组和第二FET开关组的FET控制器。 FET控制器可以用于将第一FET和第二FET连接到表面安装连接器的第一区域。 FET控制器可以被配置为将电流提供给表面安装连接器的第一区域，以产生不正确连接的接地引脚的至少一个连续的热标记特性。热监测模块可用于识别不正确的物理连接。

67. 发明申请

US20100261346A1 CIRCUIT MANUFACTURING AND DESIGN TECHNIQUES FOR REFERENCE PLANE VOIDS WITH STRIP SEGMENT 失效
标题翻译：具有条带划分的参考平面电路的电路制造和设计技术
公开(公告)号：US20100261346A1
公开(公告)日：2010-10-14
申请号：US12823316
申请日：2010-06-25
申请人： Sungjun Chun , Anand Haridass , Roger D. Weekly
发明人： Sungjun Chun , Anand Haridass , Roger D. Weekly
IPC分类号： H01L21/768 , G06F17/50
CPC分类号： G06F17/5077 , H05K1/0219 , H05K1/0237 , H05K1/0253 , H05K3/4602 , H05K3/4652 , H05K2201/09536 , H05K2201/09672 , H05K2201/0969 , H05K2201/09718 , Y10T29/49117 , Y10T29/49153 , Y10T29/49155 , Y10T29/49165 , Y10T428/24322
摘要： Manufacturing circuits with reference plane voids over vias with a strip segment interconnect permits routing critical signal paths over vias, while increasing via insertion capacitance only slightly. The transmission line reference plane defines voids above (or below) signal-bearing plated-through holes (PTHs) that pass through a rigid substrate core, so that the signals are not degraded by an impedance mismatch that would otherwise be caused by shunt capacitance from the top (or bottom) of the signal-bearing PTHs to the transmission line reference plane. In order to provide increased routing density, signal paths are routed over the voids, but disruption of the signal paths by the voids is prevented by including a conductive strip through the voids that reduces the coupling to the signal-bearing PTHs and maintains the impedance of the signal path conductor.
摘要翻译：具有带状段互连的通孔上的参考平面空隙的制造电路允许在通孔上路由关键信号路径，同时仅通过插入电容略微增加。传输线参考平面定义了通过刚性衬底芯的信号承载电镀通孔（PTH）上方（或下方）的空隙，使得信号不会被阻抗失配降级，否则会由分流电容引起信号承载PTH的顶部（或底部）到传输线参考平面。为了提供增加的布线密度，信号路径被布置在空隙上，但是通过将导电条包括在通过空隙减少与信号承载PTH的耦合并且维持信号路径导体。

68. 发明申请

US20100259289A1 Detecting Open Ground Connections in Surface Mount Connectors 失效
标题翻译：检测表面贴装连接器中的开放接地连接
公开(公告)号：US20100259289A1
公开(公告)日：2010-10-14
申请号：US12420089
申请日：2009-04-08
申请人： Anand Haridass , Jesus Montanez , Xiaomin Shen , Sungjun Chun
发明人： Anand Haridass , Jesus Montanez , Xiaomin Shen , Sungjun Chun
IPC分类号： G01R31/02 , H01L25/00
CPC分类号： G01R31/026 , G01R31/043 , G01R31/2812 , H05K3/341
摘要： A device may include a current source for connecting to a printed circuit board. The device may also include a first FET switch pack and a second FET switch pack for connecting to the surface mount connector of the printed circuit board. Additionally, the device may include a FET controller connected to the first FET switch pack and the second FET switch pack. The FET controller may be utilized for connecting a first FET and a second FET to the first region of the surface mount connector. The FET controller may be configured for supplying the current to the first region of the surface mount connector to produce at least one continuous heat signature characteristic of an improperly connected ground pin. A thermal monitoring module may be used to identify the improper physical connection.
摘要翻译：设备可以包括用于连接到印刷电路板的电流源。该装置还可以包括用于连接到印刷电路板的表面安装连接器的第一FET开关组件和第二FET开关组件。另外，该装置可以包括连接到第一FET开关组和第二FET开关组的FET控制器。 FET控制器可以用于将第一FET和第二FET连接到表面安装连接器的第一区域。 FET控制器可以被配置为将电流提供给表面安装连接器的第一区域，以产生不正确连接的接地引脚的至少一个连续的热标记特性。热监测模块可用于识别不正确的物理连接。

69. 发明授权

US07721119B2 System and method to optimize multi-core microprocessor performance using voltage offsets 失效
标题翻译：使用电压补偿优化多核微处理器性能的系统和方法
公开(公告)号：US07721119B2
公开(公告)日：2010-05-18
申请号：US11466891
申请日：2006-08-24
申请人： Louis Bennie Capps, Jr. , Warren D. Dyckman , Joanne Ferris , Anand Haridass , James Douglas Jordan , Ronald Edward Newhart , Michael Richard Ouellette , Michael Jay Shapiro
发明人： Louis Bennie Capps, Jr. , Warren D. Dyckman , Joanne Ferris , Anand Haridass , James Douglas Jordan , Ronald Edward Newhart , Michael Richard Ouellette , Michael Jay Shapiro
IPC分类号： G06F1/00
CPC分类号： G06F1/26
摘要： A system and method to optimize multi-core microprocessor performance using voltage offsets is presented. A multi-core device tests each of its processor cores in order to identify each processor core's optimum supply voltage. In turn, the device configures voltage offset networks for each processor core based upon each processor core's identified optimum supply voltage. As a result, the offset voltages produced by the voltage offset networks are subtracted from the multi-core device's main voltage, which results in the voltage offset networks supplying optimum supply voltages to each processor core. The voltage offset networks may include fuses to generate a fixed voltage offset, or the voltage offset networks may include a control circuit to dynamically adjust voltage offsets during the multi-core device's operation.
摘要翻译：提出了使用电压偏移来优化多核微处理器性能的系统和方法。多核设备测试每个处理器内核，以便识别每个处理器内核的最佳电源电压。反过来，该设备基于每个处理器核心的所识别的最佳电源电压来配置每个处理器核心的电压偏移网络。结果，从多核设备的主电压中减去由电压偏移网络产生的偏移电压，这导致电压偏移网络向每个处理器核提供最佳电源电压。电压偏移网络可以包括熔丝以产生固定的电压偏移，或者电压偏移网络可以包括在多核装置的操作期间动态地调节电压偏移的控制电路。

70. 发明授权

US07614141B2 Fabricating substrates having low inductance via arrangements 失效
标题翻译：通过布置制造具有低电感的基板
公开(公告)号：US07614141B2
公开(公告)日：2009-11-10
申请号：US11355713
申请日：2006-02-16
申请人： Daniel Douriet , Anand Haridass , Andreas Huber , Colm B. O'Reilly , Roger D. Weekly
发明人： Daniel Douriet , Anand Haridass , Andreas Huber , Colm B. O'Reilly , Roger D. Weekly
IPC分类号： H01K3/10
CPC分类号： H05K1/162 , H01L23/49827 , H01L23/50 , H01L23/642 , H01L2924/0002 , H05K1/0306 , H05K3/4611 , H05K3/4629 , H05K2201/09609 , H05K2201/09627 , Y10T29/49117 , Y10T29/49155 , H01L2924/00
摘要： A low inductance via arrangement for multilayer ceramic (MLC) substrates is provided. With the MLC substrate and via arrangement of the illustrative embodiments, the via-field inductance for a given contact pad array is reduced. This reduction is achieved by the introduction of T-jogs and additional vias. These T-jogs and additional vias form additional current paths that cause additional parallel inductances that reduce the via-field inductance. In one illustrative embodiment, the additional T-jogs and vias are added to a center portion of a contact pad array. The T-jogs are comprised of two jogs in a wiring layer of the MLC, each jog being toward a via associated with an adjacent contact pad in the contact pad array. These additional T-jogs and vias form additional current loops parallel to the existing ones which thus, reduce the total inductance of the via-field.
摘要翻译：提供了一种用于多层陶瓷（MLC）衬底的低电感通孔布置。通过MLC衬底和示例性实施例的通孔布置，给定接触焊盘阵列的通孔电感减小。这种减少是通过引入T-jogs和附加通孔来实现的。这些T形点动和附加通孔形成额外的电流路径，从而产生额外的并联电感，从而减小通路电感。在一个说明性实施例中，附加的T形点动和通孔被添加到接触焊盘阵列的中心部分。 T-jogs由MLC的布线层中的两个点动组成，每个点动都朝向与接触垫阵列中的相邻接触焊盘相关联的通孔。这些额外的T形点动和通孔形成与现有循环平行的额外的电流回路，从而减小通孔的总电感。

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