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61. 发明授权

US07826252B2 Read-preferred SRAM cell design 有权
标题翻译：读取优先的SRAM单元设计
公开(公告)号：US07826252B2
公开(公告)日：2010-11-02
申请号：US12201725
申请日：2008-08-29
申请人： Ping-Wei Wang , Yuh-Jier Mii , Hung-Jen Liao
发明人： Ping-Wei Wang , Yuh-Jier Mii , Hung-Jen Liao
IPC分类号： G11C11/00
CPC分类号： G11C11/412 , H01L21/26586 , H01L29/66659
摘要： A method for operating a static random access memory (SRAM) cell includes providing the SRAM cell having a static read margin and a static write margin, wherein the static read margin is greater than the static write margin; applying a dynamic power to perform a write operation on the SRAM cell; and applying a static power to perform a read operation on the SRAM cell.
摘要翻译：一种用于操作静态随机存取存储器（SRAM）单元的方法包括提供具有静态读取余量和静态写入裕度的SRAM单元，其中静态读取余量大于静态写入余量; 施加动态功率以对SRAM单元执行写入操作; 并施加静态电力以对SRAM单元执行读取操作。

62. 发明申请

US20100157692A1 Distributed VDC for SRAM Memory 有权
标题翻译：分布式VDC用于SRAM存储器
公开(公告)号：US20100157692A1
公开(公告)日：2010-06-24
申请号：US12338732
申请日：2008-12-18
申请人： Li-Wen Wang , Yen-Huei Chen , Chen-Lin Yang , Hsien-Yu Pan , Shao-Yu Chou , Hung-Jen Liao
发明人： Li-Wen Wang , Yen-Huei Chen , Chen-Lin Yang , Hsien-Yu Pan , Shao-Yu Chou , Hung-Jen Liao
IPC分类号： G11C7/00 , G11C5/14
CPC分类号： G11C11/413 , G11C5/04 , G11C5/147
摘要： An integrated circuit structure includes a memory. The memory includes a first memory macro and a second memory macro identical to the first memory macro. A first power block is connected to the first memory macro and is configured to provide a regulated voltage to the first memory macro. The first power block has a first input and a first output. A second power block substantially identical to the first power block is connected to the second memory macro and is configured to provide the regulated voltage to the second memory macro. The second power block has a second input and a second output. The first input and the second input are interconnected. The first output and the second output are interconnected.
摘要翻译：集成电路结构包括存储器。存储器包括与第一存储器宏相同的第一存储器宏和第二存储器宏。第一功率块连接到第一存储器宏，并被配置为向第一存储器宏提供调节电压。第一功率块具有第一输入和第一输出。基本上与第一功率块相同的第二功率块连接到第二存储器宏，并且被配置为向第二存储器宏提供调节电压。第二功率块具有第二输入和第二输出。第一输入和第二输入互连。第一个输出和第二个输出相互连接。

63. 发明授权

US07639551B2 Sense amplifiers operated under hamming distance methodology 有权
标题翻译：感应放大器在汉明距离方法下运行
公开(公告)号：US07639551B2
公开(公告)日：2009-12-29
申请号：US11737093
申请日：2007-04-18
申请人： Chia-Wei Wang , Hong-Chen Cheng , Lee Cheng Hung , Hung-Jen Liao
发明人： Chia-Wei Wang , Hong-Chen Cheng , Lee Cheng Hung , Hung-Jen Liao
IPC分类号： G11C7/06
CPC分类号： G11C7/065
摘要： A semiconductor device includes a first sense amplifier coupled to an input for generating a first output; a second sense amplifier couple to the input for generating a second output; and a third sense amplifier coupled to the input for generating a third output, wherein a fourth output amplifying the input is generated based on combinations of logic states of the first, second and third outputs.
摘要翻译：半导体器件包括耦合到输入端的第一读出放大器，用于产生第一输出; 第二读出放大器耦合到输入以产生第二输出; 以及耦合到所述输入的第三读出放大器，用于产生第三输出，其中基于所述第一，第二和第三输出的逻辑状态的组合产生放大所述输入的第四输出。

64. 发明授权

US07577052B2 Power switching circuit 有权
标题翻译：电源开关电路
公开(公告)号：US07577052B2
公开(公告)日：2009-08-18
申请号：US11638187
申请日：2006-12-13
申请人： Jui-Jen Wu , Kun-Lung Chen , Hung-Jen Liao , Yung-Lung Lin , Chen Yen-Huei , Dao-Ping Wang
发明人： Jui-Jen Wu , Kun-Lung Chen , Hung-Jen Liao , Yung-Lung Lin , Chen Yen-Huei , Dao-Ping Wang
IPC分类号： G11C5/10
CPC分类号： G11C11/412 , G11C11/413
摘要： A power control circuit for an integrated circuit module includes at least one switch device coupled between a supply voltage and a power node of the integrated circuit module; and a switch control module having a first terminal coupled to the switch device, a second terminal coupled to a control signal, a third terminal coupled to a first storage node of at least one tracking cell, a fourth terminal coupled to a second storage node of the tracking cell, and a fifth terminal coupled to the power node of the integrated circuit module, for controlling the switch device to pass the supply voltage to the power node with or without a substantial voltage drop depending on an operation mode of the integrated circuit module.
摘要翻译：用于集成电路模块的功率控制电路包括耦合在电源电压和集成电路模块的功率节点之间的至少一个开关装置; 以及开关控制模块，其具有耦合到所述开关装置的第一端子，耦合到控制信号的第二端子，耦合到至少一个跟踪单元的第一存储节点的第三端子，耦合到所述至少一个跟踪单元的第二存储节点的第四端子跟踪单元和耦合到集成电路模块的功率节点的第五端子，用于根据集成电路模块的操作模式控制开关装置将电源电压传递到功率节点，具有或不具有实质的电压降。

65. 发明授权

US07551415B2 Repair circuitry with an enhanced ESD protection device 有权
标题翻译：具有增强型ESD保护装置的修复电路
公开(公告)号：US07551415B2
公开(公告)日：2009-06-23
申请号：US11512830
申请日：2006-08-30
申请人： Ming-Hsien Tsai , Hung-Jen Liao , Sung-Chieh Lin
发明人： Ming-Hsien Tsai , Hung-Jen Liao , Sung-Chieh Lin
IPC分类号： H02H3/22
CPC分类号： G11C29/02 , G11C17/18 , G11C29/027
摘要： A repair circuitry consisting of at least one electrical fuse forming part of a conduction path between a positive voltage supply (Vq) pad and a complimentary lower voltage supply source (Vss). The repair circuitry includes at least one switching device and at least one control circuitry. The at least one switching device has a control terminal and is coupled between the Vq pad and the at least one electrical fuse. The at least one control circuitry is coupled to the control terminal and the Vq pad respectively. Upon an application of a positive high voltage to the Vq pad, the control circuitry delays the turned-on state of the switching device for a predetermined period of time, thereby blocking stray currents occurred during ESD events. Consequently, the repair circuitry can prevent the at least one electrical fuse from being mistakenly programmed.
摘要翻译：修复电路由至少一个电熔丝构成，形成正电压源（Vq）焊盘和互补的低电压源（Vss）之间的传导路径的一部分。修复电路包括至少一个开关装置和至少一个控制电路。所述至少一个开关装置具有控制端子，并且耦合在所述Vq焊盘和所述至少一个电熔丝之间。至少一个控制电路分别耦合到控制端子和Vq焊盘。当向Vq焊盘施加正高电压时，控制电路将开关器件的接通状态延迟预定的时间段，从而阻止在ESD事件期间发生的杂散电流。因此，修理电路可以防止至少一个电熔丝被错误编程。

66. 发明申请

US20080158939A1 MEMORY HAVING IMPROVED POWER DESIGN 有权
标题翻译：具有改进功率设计的记忆
公开(公告)号：US20080158939A1
公开(公告)日：2008-07-03
申请号：US11619103
申请日：2007-01-02
申请人： Yen-Huei Chen , Hung-Jen Liao , Kun-Lung Chen , Jui-Jen Wu , Yung-Lung Lin , Dao-Ping Wang
发明人： Yen-Huei Chen , Hung-Jen Liao , Kun-Lung Chen , Jui-Jen Wu , Yung-Lung Lin , Dao-Ping Wang
IPC分类号： G11C11/00
CPC分类号： G11C11/412 , G11C11/413
摘要： A memory includes a plurality of cells arranged in a matrix having a plurality of rows and a plurality of columns, wherein each cell is capable of storing a bit. Each cell is coupled between a first power supply node that receives a power supply voltage and a second power supply node that receives a second voltage. A plurality of word lines are associated with the memory cells and supplied by a third voltage in read or write operation. The third voltage is a suppressed power supply voltage. The second voltage is negative in read operation and positive in write operation.
摘要翻译：存储器包括以具有多个行和多个列的矩阵的形式排列的多个单元，其中每个单元能够存储位。每个单元耦合在接收电源电压的第一电源节点和接收第二电压的第二电源节点之间。多个字线与存储器单元相关联并且在读或写操作中由第三电压提供。第三电压是抑制电源电压。读操作中的第二电压为负，写操作为正。

67. 发明授权

US08928113B2 Layout scheme and method for forming device cells in semiconductor devices 有权
标题翻译：用于在半导体器件中形成器件单元的布局方案和方法
公开(公告)号：US08928113B2
公开(公告)日：2015-01-06
申请号：US13082497
申请日：2011-04-08
申请人： Hsien-Yu Pan , Jung-Hsuan Chen , Shao-Yu Chou , Yen-Huei Chen , Hung-Jen Liao
发明人： Hsien-Yu Pan , Jung-Hsuan Chen , Shao-Yu Chou , Yen-Huei Chen , Hung-Jen Liao
IPC分类号： H01L23/52 , H01L27/108 , H01L29/94 , H01L21/70 , H01L27/02 , H01L27/11 , H01L27/118
CPC分类号： H01L27/1116 , H01L21/768 , H01L27/0207 , H01L27/11 , H01L2027/11887
摘要： A method and layout for forming word line decoder devices and other devices having word line decoder cells provides for forming metal interconnect layers using non-DPL photolithography operations and provides for stitching distally disposed transistors using a lower or intermediate metal layer or a subjacent conductive material. The transistors may be disposed in or adjacent longitudinally arranged word line decoder or other cells and the conductive coupling using the metal or conductive material lowers gate resistance between transistors and avoids RC signal delays.
摘要翻译：用于形成字线解码器装置和具有字线解码器单元的其它装置的方法和布局提供了使用非DPL光刻操作形成金属互连层，并且使用下部或中间金属层或下部导电材料提供了用于缝合的远端布置的晶体管。晶体管可以设置在纵向布置的字线解码器或其他单元中或其附近，并且使用金属或导电材料的导电耦合降低晶体管之间的栅极电阻并避免RC信号延迟。

68. 发明授权

US08773930B2 Built-in test circuit and method 有权
标题翻译：内置测试电路及方法
公开(公告)号：US08773930B2
公开(公告)日：2014-07-08
申请号：US13365631
申请日：2012-02-03
申请人： Tzu-Kuei Lin , Hung-Jen Liao , Yen-Huei Chen , Fang Jao
发明人： Tzu-Kuei Lin , Hung-Jen Liao , Yen-Huei Chen , Fang Jao
IPC分类号： G11C29/00
CPC分类号： G11C29/34 , G11C29/006 , G11C29/06 , G11C2029/2602
摘要： A method of testing a semiconductor memory includes performing a first test of a first type prior to packaging the semiconductor memory. The first test of the first type includes generating a first plurality of addresses, decoding the first plurality of addresses to generate a second plurality of decoded addresses at a first decoder, and activating one of a plurality of rows or a plurality of columns of the semiconductor memory based on the second plurality of decoded addresses. The semiconductor memory is packaged after performing the first test of the first type.
摘要翻译：测试半导体存储器的方法包括在封装半导体存储器之前执行第一类型的第一测试。第一类型的第一测试包括产生第一多个地址，解码第一多个地址以在第一解码器处产生第二多个解码地址，以及激活半导体的多个行或多个列中的一个基于第二多个解码地址的存储器。在执行第一类型的第一测试之后封装半导体存储器。

69. 发明授权

US08576655B2 Semiconductor memories 有权
标题翻译：半导体存储器
公开(公告)号：US08576655B2
公开(公告)日：2013-11-05
申请号：US13164807
申请日：2011-06-21
申请人： Wei Min Chan , Yen-Huei Chen , Jihi-Yu Lin , Hsien-Yu Pan , Hung-Jen Liao
发明人： Wei Min Chan , Yen-Huei Chen , Jihi-Yu Lin , Hsien-Yu Pan , Hung-Jen Liao
IPC分类号： G11C8/00
CPC分类号： G11C11/412
摘要： A semiconductor memory includes a bit cell having first and inverters forming a latch. First and second transistors are respectively coupled to first and second storage nodes of the latch and to first and second write bit lines. Each of the first and second transistors has a respective gate coupled to a first node. Third and fourth transistors are coupled together in series at the first node and are disposed between a write word line and a first voltage source. Each of the first and second transistors has a respective gate coupled to a first control line. A fifth transistor has a source coupled to a second voltage source, a drain coupled to at least one of the inverters of the latch, and a gate coupled to the first node. A read port is coupled to a first read bit line and to the second storage node of the latch.
摘要翻译：半导体存储器包括具有形成锁存器的第一和反相器的位单元。第一和第二晶体管分别耦合到锁存器的第一和第二存储节点以及第一和第二写入位线。第一和第二晶体管中的每一个具有耦合到第一节点的相应栅极。第三和第四晶体管在第一节点处串联耦合在一起，并且设置在写入字线和第一电压源之间。第一和第二晶体管中的每一个具有耦合到第一控制线的相应栅极。第五晶体管具有耦合到第二电压源的源极，耦合到锁存器的至少一个反相器的漏极和耦合到第一节点的栅极。读端口耦合到第一读位线和锁存器的第二存储节点。

70. 发明申请

US20130201776A1 BUILT-IN TEST CIRCUIT AND METHOD 有权
标题翻译：内置测试电路和方法
公开(公告)号：US20130201776A1
公开(公告)日：2013-08-08
申请号：US13365631
申请日：2012-02-03
申请人： Tzu-Kuei LIN , Hung-Jen Liao , Yen-Huei Chen , Fang Jao
发明人： Tzu-Kuei LIN , Hung-Jen Liao , Yen-Huei Chen , Fang Jao
IPC分类号： G11C29/00
CPC分类号： G11C29/34 , G11C29/006 , G11C29/06 , G11C2029/2602
摘要： A method of testing a semiconductor memory includes performing a first test of a first type prior to packaging the semiconductor memory. The first test of the first type includes generating a first plurality of addresses, decoding the first plurality of addresses to generate a second plurality of decoded addresses at a first decoder, and activating one of a plurality of rows or a plurality of columns of the semiconductor memory based on the second plurality of decoded addresses. The semiconductor memory is packaged after performing the first test of the first type.
摘要翻译：测试半导体存储器的方法包括在封装半导体存储器之前执行第一类型的第一测试。第一类型的第一测试包括产生第一多个地址，解码第一多个地址以在第一解码器处产生第二多个解码地址，以及激活半导体的多个行或多个列中的一个基于第二多个解码地址的存储器。在执行第一类型的第一测试之后封装半导体存储器。

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