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61. 发明授权

US4366613A Method of fabricating an MOS dynamic RAM with lightly doped drain 失效
标题翻译：制造具有轻掺杂漏极的MOS动态RAM的方法
公开(公告)号：US4366613A
公开(公告)日：1983-01-04
申请号：US217497
申请日：1980-12-17
申请人： Seiki Ogura , Paul J. Tsang
发明人： Seiki Ogura , Paul J. Tsang
IPC分类号： H01L21/336 , H01L21/8242 , H01L27/10 , H01L27/108 , H01L29/08 , H01L29/78 , H01L21/26
CPC分类号： H01L27/10873 , H01L29/0847 , H01L29/78
摘要： A method of manufacturing LDD MOS FET RAM capable of delineating short (less than 1 micrometer) lightly doped drain regions. An N.sup.- implant is effected between gate electrodes and field oxide insulators, before the N.sup.+ implant. An insulator layer is then deposited also prior to N.sup.+ ion implantation. Reactive ion etching of the layer leaves narrow dimensioned insulator regions adjacent the gate electrode which serves to protect portions of the N.sup.- impurity region during the subsequent N.sup.+ implant. These protected regions are the lightly doped source/drain regions.
摘要翻译：一种制造能够描绘短（小于1微米）轻掺杂漏极区的LDD MOS FET RAM的方法。在N +植入之前，在栅电极和场氧化物绝缘体之间进行N-注入。然后在N +离子注入之前也沉积绝缘体层。层的反应离子蚀刻离开邻近栅极的窄尺寸绝缘体区域，其用于在随后的N +植入期间保护N杂质区域的部分。这些受保护区域是轻掺杂的源极/漏极区域。

62. 发明申请

US20100046302A1 Complementary Reference method for high reliability trap-type non-volatile memory 有权
标题翻译：高可靠性陷阱型非易失性存储器的补充参考方法
公开(公告)号：US20100046302A1
公开(公告)日：2010-02-25
申请号：US12583743
申请日：2009-08-25
申请人： Nori Ogura , Tomoko Ogura , Seiki Ogura
发明人： Nori Ogura , Tomoko Ogura , Seiki Ogura
IPC分类号： G11C16/06 , G11C16/04 , G11C7/02
CPC分类号： G11C16/06 , G11C7/04 , G11C7/06 , G11C7/10 , G11C11/5628 , G11C11/5642 , G11C16/04 , G11C16/0466 , G11C16/10 , G11C2211/5647
摘要： Methods of complementary pairing of memory cells are described. These methods include two physical memory cells in a complementary pair, a complementary pair of reference cells for each erase block, and a physical complementary pair storing multiple data bits.
摘要翻译：描述了存储器单元的互补配对的方法。这些方法包括互补对中的两个物理存储器单元，每个擦除块的互补对参考单元，以及存储多个数据位的物理互补对。

63. 发明申请

US20070030745A1 Referencing scheme for trap memory 有权
标题翻译：陷阱内存引用方案
公开(公告)号：US20070030745A1
公开(公告)日：2007-02-08
申请号：US11500115
申请日：2006-08-07
申请人： Tomoko Ogura , Nori Ogura , Seiki Ogura , Yoshitaka Baba
发明人： Tomoko Ogura , Nori Ogura , Seiki Ogura , Yoshitaka Baba
IPC分类号： G11C7/02 , G11C16/06 , G11C11/34
CPC分类号： G11C7/14 , G11C16/0475 , G11C16/28 , G11C16/3445 , G11C16/3454 , G11C16/3459
摘要： A reference circuit is described for creating a reference signal using a twin MONOS memory cell. A first portion of the twin MONOS memory cell connects to a charged and floating bit line a current source formed in a second portion of the twin MONOS cell that discharges the charged bit line to form a reference signal for a sense amplifier. The sense amplifier compares the reference signal to a signal from a selected memory cell upon which memory operations are being performed comprising read, erase verify and program verify.
摘要翻译：描述了使用双MONOS存储单元创建参考信号的参考电路。双MONOS存储器单元的第一部分连接到充电和浮置位线，形成在双MONOS单元的第二部分中的电流源，其对充电的位线进行放电以形成用于读出放大器的参考信号。读出放大器将参考信号与来自执行存储器操作的所选存储器单元的信号进行比较，包括读取，擦除验证和程序验证。

64. 发明授权

US07170132B2 Twin insulator charge storage device operation and its fabrication method 有权
公开(公告)号：US07170132B2
公开(公告)日：2007-01-30
申请号：US11059081
申请日：2005-02-16
申请人： Seiki Ogura , Kimihiro Satoh , Tomoya Saito
发明人： Seiki Ogura , Kimihiro Satoh , Tomoya Saito
IPC分类号： H01L29/792
CPC分类号： H01L21/28282 , G11C16/0466 , G11C16/0475 , G11C16/0483 , H01L27/105 , H01L27/115 , H01L27/11568 , H01L29/4234 , H01L29/42364 , H01L29/66833 , H01L29/792 , H01L29/7923 , H01L2924/0002 , H01L2924/00
摘要： The invention proposes am improved twin MONOS memory device and its fabrication. The ONO layer is self-aligned to the control gate horizontally. The vertical insulator between the control gate and the word gate does not include a nitride layer. This prevents the problem of electron trapping. The device can be fabricated to pull the electrons out through either the top or the bottom oxide layer of the ONO insulator. The device also incorporates a raised memory bit diffusion between the control gates to reduce bit resistance. The twin MONOS memory array can be embedded into a standard CMOS circuit by the process of the present invention.

65. 发明申请

US20060198200A1 Twin insulator charge storage device operation and its fabrication method 有权
公开(公告)号：US20060198200A1
公开(公告)日：2006-09-07
申请号：US11409333
申请日：2006-04-21
申请人： Seiki Ogura , Kimihiro Satoh , Tomoya Saito
发明人： Seiki Ogura , Kimihiro Satoh , Tomoya Saito
IPC分类号： G11C16/04 , G11C11/34
CPC分类号： H01L21/28282 , G11C16/0466 , G11C16/0475 , G11C16/0483 , H01L27/105 , H01L27/115 , H01L27/11568 , H01L29/4234 , H01L29/42364 , H01L29/66833 , H01L29/792 , H01L29/7923 , H01L2924/0002 , H01L2924/00
摘要： The invention proposes am improved twin MONOS memory device and its fabrication. The ONO layer is self-aligned to the control gate horizontally. The vertical insulator between the control gate and the word gate does not include a nitride layer. This prevents the problem of electron trapping. The device can be fabricated to pull the electrons out through either the top or the bottom oxide layer of the ONO insulator. The device also incorporates a raised memory bit diffusion between the control gates to reduce bit resistance. The twin MONOS memory array can be embedded into a standard CMOS circuit by the process of the present invention.

66. 发明授权

US07006378B1 Array architecture and operation methods for a nonvolatile memory 有权
标题翻译：非易失性存储器的阵列架构和操作方法
公开(公告)号：US07006378B1
公开(公告)日：2006-02-28
申请号：US10742987
申请日：2003-12-22
申请人： Tomoya Saito , Tomoko Ogura , Kimihiro Satoh , Seiki Ogura
发明人： Tomoya Saito , Tomoko Ogura , Kimihiro Satoh , Seiki Ogura
IPC分类号： G11C16/04
CPC分类号： G11C16/0475
摘要： A nonvolatile memory device is achieved. The device comprises a string of MONOS cells connected drain to source. Each MONOS cell comprises a wordline gate overlying a channel region in a substrate. First and second control gates each overlying a channel region in the substrate. The wordline gate channel region is laterally between first and second control gate channel regions. An ONO layer is vertically between the control gates and the substrate. The nitride layer of the ONO layer forms a charge storage site for each control gate. First and second doped regions, forming a source and a drain, are in the substrate. The wordline gate channel region and the control gate channel regions are between the first doped region and the second doped region. First and second transistors connect the topmost MONOS cell to a first bit line and the bottom most MONOS cell to a second bit line.
摘要翻译：实现非易失性存储器件。该装置包括一串连接到源极的MONOS电池。每个MONOS单元包括覆盖衬底中的沟道区的字线门。第一和第二控制栅极，每个覆盖衬底中的沟道区域。字线栅极沟道区域横向在第一和第二控制栅极沟道区域之间。 ONO层在控制栅极和衬底之间垂直。 ONO层的氮化物层形成每个控制栅极的电荷存储位置。在衬底中形成源极和漏极的第一和第二掺杂区域。字线栅极沟道区和控制栅沟道区在第一掺杂区和第二掺杂区之间。第一和第二晶体管将最上面的MONOS单元连接到第一位线，将最底部的MONOS单元连接到第二位线。

67. 发明授权

US06838344B2 Simplified twin monos fabrication method with three extra masks to standard CMOS 有权
标题翻译：简单的双胞胎制造方法，具有三个额外的掩码到标准CMOS
公开(公告)号：US06838344B2
公开(公告)日：2005-01-04
申请号：US10853453
申请日：2004-05-25
申请人： Kimihiro Satoh , Tomoya Saito , Seiki Ogura
发明人： Kimihiro Satoh , Tomoya Saito , Seiki Ogura
IPC分类号： H01L21/8246 , H01L27/115 , H01L21/336
CPC分类号： H01L27/11568 , H01L27/115
摘要： The invention proposes to simplify fabrication of the twin MONOS memory array. The twin MONOS memory array can be embedded into a standard CMOS circuit by the process of the present invention by adding only three additional mask levels. Conventional floating gate devices need ten or more extra masks. In the present invention, the unique twin MONOS process steps can be inserted into the standard CMOS process flow without any parameter modifications. The present invention also achieves increased endurance by means of reducing the widths of the sidewall control gate and underlying nitride storage region.
摘要翻译：本发明提出简化双MONOS存储器阵列的制造。通过仅添加三个附加掩模级别，本发明的双MONOS存储器阵列可以嵌入到标准CMOS电路中。常规浮动栅极器件需要十个或更多个额外的掩模。在本发明中，独特的双MONOS工艺步骤可以插入到标准CMOS工艺流程中，无需任何参数修改。本发明还通过减小侧壁控制栅极和下面的氮化物存储区域的宽度来实现增加的耐久性。

68. 发明授权

US06784040B2 Nonvolatile semiconductor memory device and method for fabricating the same 失效
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US06784040B2
公开(公告)日：2004-08-31
申请号：US10382508
申请日：2003-03-07
申请人： Masataka Kusumi , Fumihiko Noro , Hiromasa Fujimoto , Akihiro Kamada , Shinji Odanaka , Seiki Ogura
发明人： Masataka Kusumi , Fumihiko Noro , Hiromasa Fujimoto , Akihiro Kamada , Shinji Odanaka , Seiki Ogura
IPC分类号： H01L29788
CPC分类号： H01L29/66825 , H01L21/28273 , H01L29/42324 , H01L29/7885
摘要： A nonvolatile semiconductor memory device has a protective insulating film deposited on each of the side surfaces of a control gate electrode to protect the control gate electrode during the formation of a floating gate electrode, the floating gate electrode opposed to one of the side surfaces of the control gate electrode with the protective insulating film interposed therebetween so as to be capacitively coupled to the control gate electrode, a tunnel insulating film formed between the floating gate electrode and the semiconductor substrate, a drain region formed in a region of the semiconductor substrate containing a portion underlying the floating gate electrode, and a source region formed in a region of the semiconductor substrate opposite to the drain region relative to the control gate electrode.
摘要翻译：非易失性半导体存储器件具有沉积在控制栅电极的每个侧表面上的保护绝缘膜，以在形成浮栅电极期间保护控制栅电极，浮置栅极与其中一个侧表面相对控制栅电极，其间插入有保护绝缘膜，以便电容耦合到控制栅电极，形成在浮置栅电极和半导体衬底之间的隧道绝缘膜，形成在半导体衬底的包含并且形成在半导体衬底的与漏极区相对的控制栅电极相对的区域中的源极区。

69. 发明授权

US06686622B2 Semiconductor memory device and manufacturing method thereof 失效
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US06686622B2
公开(公告)日：2004-02-03
申请号：US10077979
申请日：2002-02-20
申请人： Fumihiko Noro , Seiki Ogura
发明人： Fumihiko Noro , Seiki Ogura
IPC分类号： H01L2976
CPC分类号： H01L29/66825 , H01L21/28273 , H01L29/42324
摘要： A semiconductor memory device includes a control gate electrode formed on a first main surface of a semiconductor substrate through a first insulating film, and a floating gate electrode covering a stepped region which connects the first main surface of the semiconductor substrate and a second main surface positioned at a lower level than the first main surface through a second insulating film and having a side surface capacitively coupled with one side surface of the control gate electrode through a third insulating film. The stepped region has a first stepped portion connected with the first main surface and a second stepped portion connecting the first stepped portion and the second main surface.
摘要翻译：半导体存储器件包括通过第一绝缘膜形成在半导体衬底的第一主表面上的控制栅极电极和覆盖连接半导体衬底的第一主表面的阶梯区域的浮栅电极和位于通过第二绝缘膜在比第一主表面更低的水平处，并且具有通过第三绝缘膜与控制栅电极的一个侧表面电容耦合的侧表面。台阶区域具有与第一主表面连接的第一阶梯部分和连接第一阶梯部分和第二主表面的第二阶梯部分。

70. 发明授权

US06670240B2 Twin NAND device structure, array operations and fabrication method 有权
公开(公告)号：US06670240B2
公开(公告)日：2003-12-30
申请号：US10218210
申请日：2002-08-13
申请人： Seiki Ogura , Tomoko Ogura , Tomoya Saito , Kimihiro Satoh
发明人： Seiki Ogura , Tomoko Ogura , Tomoya Saito , Kimihiro Satoh
IPC分类号： H01L21336
CPC分类号： G11C11/5671 , G11C16/0475 , H01L27/115 , H01L27/11568
摘要： A method for making a twin MONOS memory array is described where two nitride storage sites lay under the memory cell word gate. The fabrication techniques incorporate self alignment techniques to produce a small cell in which N+ diffusion the nitride storage sites are defined by sidewalls. The memory cell is used in an NAND array where the memory operations are controlled by voltages on the word lines and column selectors. Each storage site within the memory cell is separately programmed and read by application of voltages to the selected cell through the selected word line whereas the unselected word lines are used to pass drain and source voltages to the selected cell from upper and lower column voltages.

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