专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

61. 发明授权

US06803790B2 Bidirectional port with clock channel used for synchronization 失效
公开(公告)号：US06803790B2
公开(公告)日：2004-10-12
申请号：US10690235
申请日：2003-10-21
申请人： Matthew B. Haycock , Stephen R. Mooney , Aaron K. Martin
发明人： Matthew B. Haycock , Stephen R. Mooney , Aaron K. Martin
IPC分类号： H03K190175
CPC分类号： G06F13/4077
摘要： A simultaneous bidirectional port coupled to a bus combines a synchronization circuit and a clock circuit. The synchronization and clock circuit synchronizes the port with another simultaneous data port coupled to the same bus. A clock driver circuit is provided that is capable of being turned on and off. Prior to synchronization, the clock driver is off, and after synchronization, the clock driver is on. A clock receiver circuit includes a clock detection circuit to detect the presence of an input clock signal. When an integrated circuit is ready to communicate, the output clock driver is turned on and the clock detection circuit is monitored to determine when an input clock signal is received. When both the output clock driver is turned on, and an input clock signal is being received, the simultaneous bidirectional port is synchronized, and communication between integrated circuits can take place.

62. 发明授权

US06847617B2 Systems for interchip communication 有权
标题翻译：芯片间通信系统
公开(公告)号：US06847617B2
公开(公告)日：2005-01-25
申请号：US09817659
申请日：2001-03-26
申请人： Shekhar Y Borkar , Matthew B. Haycock , Stephen R. Mooney , Aaron K. Martin , Joseph T. Kennedy
发明人： Shekhar Y Borkar , Matthew B. Haycock , Stephen R. Mooney , Aaron K. Martin , Joseph T. Kennedy
IPC分类号： G06F13/00 , G06F13/38 , G06F13/40 , H04L12/28
CPC分类号： G06F13/4086
摘要： In some embodiments, the invention involves a system having a first group of integrated circuits connected in a truncated ring fashion, wherein the truncated ring includes a truncated region to allow for additional integrated circuits to be added to the ring. In some embodiments, the invention involves a system having a group of integrated circuits connected in a pseudo ring fashion, wherein the pseudo ring is created by data flow of bi-directional signaling between the integrated circuits. In some embodiments, the invention involves a system having a group of integrated circuits connected in a pseudo differential arrangement in which multiple conductors carrying signals share a common reference signal conductor.
摘要翻译：在一些实施例中，本发明涉及具有以截头环方式连接的第一组集成电路的系统，其中所述截头环包括截取的区域，以允许将额外的集成电路添加到所述环中。在一些实施例中，本发明涉及具有以伪环方式连接的一组集成电路的系统，其中通过集成电路之间的双向信令的数据流创建伪环。在一些实施例中，本发明涉及一种具有以伪差分布置连接的一组集成电路的系统，其中携带多个导体的信号共用公共参考信号导体。

63. 发明授权

US06791356B2 Bidirectional port with clock channel used for synchronization 有权
标题翻译：具有时钟通道的双向端口用于同步
公开(公告)号：US06791356B2
公开(公告)日：2004-09-14
申请号：US09894865
申请日：2001-06-28
申请人： Matthew B. Haycock , Stephen R. Mooney , Aaron K. Martin
发明人： Matthew B. Haycock , Stephen R. Mooney , Aaron K. Martin
IPC分类号： H03K190175
CPC分类号： G06F13/4077
摘要： A simultaneous bidirectional port coupled to a bus combines a synchronization circuit and a clock circuit. The synchronization and clock circuit synchronizes the port with another simultaneous data port coupled to the same bus. A clock driver circuit is provided that is capable of being turned on and off. Prior to synchronization, the clock driver is off, and after synchronization, the clock driver is on. A clock receiver circuit includes a clock detection circuit to detect the presence of an input clock signal. When an integrated circuit is ready to communicate, the output clock driver is turned on and the clock detection circuit is monitored to determine when an input clock signal is received. When both the output clock driver is turned on, and an input clock signal is being received, the simultaneous bidirectional port is synchronized, and communication between integrated circuits can take place.
摘要翻译：耦合到总线的同时双向端口组合同步电路和时钟电路。同步和时钟电路将端口与耦合到同一总线的另一个同时的数据端口同步。提供能够打开和关闭的时钟驱动器电路。在同步之前，时钟驱动程序关闭，并且在同步之后，时钟驱动程序处于打开状态。时钟接收器电路包括用于检测输入时钟信号的存在的时钟检测电路。当集成电路准备好通信时，输出时钟驱动器导通，监视时钟检测电路，以确定何时接收输入时钟信号。当输出时钟驱动器都打开并且正在接收输入时钟信号时，同时双向端口被同步，并且可以发生集成电路之间的通信。

64. 发明授权

US06774678B2 Differential cascode current mode driver 有权
标题翻译：差分共源共栅电流模式驱动
公开(公告)号：US06774678B2
公开(公告)日：2004-08-10
申请号：US10368901
申请日：2003-02-14
申请人： Aaron K. Martin , Stephen R. Mooney
发明人： Aaron K. Martin , Stephen R. Mooney
IPC分类号： H03K19094
CPC分类号： H04L25/0282 , H03K19/01721 , H03K19/018528 , H04L25/0272 , H04L25/0294
摘要： A current mode driver includes a tail current device, a differential pair of input transistors, cascode output transistors, and pre-charge circuits to charge cascode nodes between the differential pair of input transistors and the cascode output transistors. The current mode driver is driven by CMOS drivers that alternately turn the input transistors on and off. A wide-swing bias circuit provides bias voltages for the current mode driver. This bias voltage for the tail current device is closely matched to provide current matching between the bias circuit and the current mode driver.
摘要翻译：电流模式驱动器包括尾电流器件，差分输入晶体管对，共源共栅输出晶体管和预充电电路，用于对差分输入晶体管对和共源共栅输出晶体管之间的共源共栅节点进行充电。电流模式驱动器由CMOS驱动器驱动，交替地将输入晶体管打开和关闭。宽摆幅偏置电路为电流模式驱动器提供偏置电压。尾电流器件的偏置电压紧密匹配，以提供偏置电路和电流模式驱动器之间的电流匹配。

65. 发明授权

US06747474B2 Integrated circuit stubs in a point-to-point system 有权
标题翻译：集成电路存根在点对点系统中
公开(公告)号：US06747474B2
公开(公告)日：2004-06-08
申请号：US09797480
申请日：2001-02-28
申请人： Shekhar Y. Borkar , Matthew B. Haycock , Stephen R. Mooney , Aaron K. Martin , Joseph T. Kennedy
发明人： Shekhar Y. Borkar , Matthew B. Haycock , Stephen R. Mooney , Aaron K. Martin , Joseph T. Kennedy
IPC分类号： H03K1716
CPC分类号： H04L5/14 , H03K19/01759 , H04L25/0278 , H04L25/24
摘要： In some embodiments, the invention involves multiple integrated circuit stubs coupled in series. At least one of the integrated circuit stubs including first conductors to receive signals from a first adjacent one of the integrated circuit stubs, second conductors to provide signals to a second adjacent one of the integrated circuit stubs, and third conductors to provide signals to an integrated circuit chip. The integrated circuit stubs include first drivers and second drivers coupled to the first, second, and third conductors, wherein the first drivers receive the external signals from the first conductors and drive them onto the second conductors and the second drivers receive signals from the first conductors and drive them onto the third conductors.
摘要翻译：在一些实施例中，本发明涉及串联耦合的多个集成电路短截线。所述集成电路短截线中的至少一个包括用于接收来自所述集成电路短截线中的第一相邻一个的信号的第一导体，用于向所述集成电路短截线中的第二相邻组件提供信号的第二导体以及向集成电路短截线提供信号的第三导体电路芯片。集成电路短截线包括耦合到第一，第二和第三导体的第一驱动器和第二驱动器，其中第一驱动器接收来自第一导体的外部信号并将它们驱动到第二导体上，并且第二驱动器从第一导体接收信号并将它们驱动到第三导体上。

66. 发明授权

US06741107B2 Synchronous clock generator for integrated circuits 有权
标题翻译：用于集成电路的同步时钟发生器
公开(公告)号：US06741107B2
公开(公告)日：2004-05-25
申请号：US09802584
申请日：2001-03-08
申请人： Shekhar Y. Borkar , Matthew B. Haycock , Stephen R. Mooney , Aaron K. Martin , Joseph T. Kennedy
发明人： Shekhar Y. Borkar , Matthew B. Haycock , Stephen R. Mooney , Aaron K. Martin , Joseph T. Kennedy
IPC分类号： H03L700
CPC分类号： H03L7/0805 , H03L7/0812
摘要： A synchronous clock generator for an integrated circuit is described in which a delay lock loop circuit may be used to delay a first input signal. A delay circuit is coupled to the delay lock loop circuit and receives a control voltage from the delay lock loop circuit, which is used to delay a second input signal. The first and second input signal may be complimentary.
摘要翻译：描述了用于集成电路的同步时钟发生器，其中可以使用延迟锁定环路来延迟第一输入信号。延迟电路耦合到延迟锁定环电路并且从延迟锁定环路电路接收用于延迟第二输入信号的控制电压。第一和第二输入信号可以是互补的。

67. 发明授权

US06536025B2 Receiver deskewing of multiple source synchronous bits from a parallel bus 失效
公开(公告)号：US06536025B2
公开(公告)日：2003-03-18
申请号：US09858346
申请日：2001-05-14
申请人： Joseph T. Kennedy , Shekhar Y. Borkar , Matthew B. Haycock , Stephen R. Mooney , Aaron K. Martin
发明人： Joseph T. Kennedy , Shekhar Y. Borkar , Matthew B. Haycock , Stephen R. Mooney , Aaron K. Martin
IPC分类号： G06F1750
CPC分类号： G06F13/4217
摘要： A receiver integrated circuit (IC) die or functional unit has deskew circuitry to reduce bit-to-bit timing variation that is no more than one bit time interval in a number of bits that are received, before validating the capture of the bits using a transition in a received strobe signal. The data bits and the strobe signal are driven in a parallel bus section that may be part of a shared multi-drop bus or a point-to-point bus. The system applications include interfacing to a processor or memory bus of a computer system.

68. 发明授权

US06445170B1 Current source with internal variable resistance and control loop for reduced process sensitivity 失效
标题翻译：具有内部可变电阻和控制回路的电流源，可降低工艺灵敏度
公开(公告)号：US06445170B1
公开(公告)日：2002-09-03
申请号：US09694901
申请日：2000-10-24
申请人： Amaresh Pangal , Siva G. Narendra , Aaron K. Martin , Stephen R. Mooney
发明人： Amaresh Pangal , Siva G. Narendra , Aaron K. Martin , Stephen R. Mooney
IPC分类号： G05F156
CPC分类号： G05F3/262
摘要： A current reference with reduced sensitivity to process variations includes two current sources. The first current source has an output current that is sensitive to process variations. The second current source has, as a component of its input current, the output current of the first current source. The input current to the second current source is substantially constant because the process dependent component has been removed by the output current of the first current source. Variable resistors internal to the current source are set using a control loop circuit and an external resistor.
摘要翻译：具有降低的对工艺变化灵敏度的电流参考包括两个电流源。第一个电流源具有对过程变化敏感的输出电流。作为其输入电流的一部分，第二电流源具有第一电流源的输出电流。到第二电流源的输入电流基本上是恒定的，因为由第一电流源的输出电流去除过程相关元件。电流源内部的可变电阻使用控制回路电路和外部电阻进行设置。

69. 发明授权

US06377108B1 Low jitter differential amplifier with negative hysteresis 失效
标题翻译：具有负滞后的低抖动差分放大器
公开(公告)号：US06377108B1
公开(公告)日：2002-04-23
申请号：US09649257
申请日：2000-08-28
申请人： Joseph T. Kennedy , Stephen R. Mooney , Aaron K. Martin , Rajendran Nair
发明人： Joseph T. Kennedy , Stephen R. Mooney , Aaron K. Martin , Rajendran Nair
IPC分类号： H03K1776
CPC分类号： H03K5/088
摘要： A differential amplifier is provided, incorporating negative hysteresis by automatic reference voltage adjustment. A delayed output signal is routed to a switch or multiplexer which functions to select one of two reference voltage levels, creating negative hysteresis. The delayed output signal is delayed by a series of inverters, which prevent certain embodiments of the invention from oscillating under some conditions. The two reference voltage levels are selected to be near the respective data signal input high and low signal voltage levels, but far enough from these levels so as not to be adversely affected by noise or other interference.
摘要翻译：提供了一个差分放大器，通过自动参考电压调整结合了负滞后。延迟的输出信号被路由到开关或多路复用器，其用于选择两个参考电压电平之一，产生负的滞后。延迟的输出信号由一系列逆变器延迟，这防止本发明的某些实施例在某些情况下振荡。两个参考电压电平被选择为接近相应的数据信号输入高和低信号电压电平，但远离这些电平，以免受噪声或其他干扰的不利影响。

70. 发明授权

US06304141B1 Complementary input self-biased differential amplifier with gain compensation 有权
标题翻译：具有增益补偿的互补输入自偏置差分放大器
公开(公告)号：US06304141B1
公开(公告)日：2001-10-16
申请号：US09609495
申请日：2000-06-30
申请人： Joseph T. Kennedy , Stephen R. Mooney , Aaron K. Martin , Rajendran Nair
发明人： Joseph T. Kennedy , Stephen R. Mooney , Aaron K. Martin , Rajendran Nair
IPC分类号： H03F345
CPC分类号： H03F3/45233 , H03F3/3028 , H03F3/45237 , H03F2203/45371 , H03F2203/45451 , H03F2203/45454 , H03F2203/45708
摘要： A complementary input self-biased differential amplifier includes gain compensation devices. The gain compensation devices are in parallel with input transistors and are biased by a self-bias node. The gain control devices serve to keep current flowing in load devices when operating at common-mode extremes, thereby limiting the reduction in amplifier output impedance and limiting the corresponding reduction in differential-mode gain at common-mode extremes. The gain control devices also serve to reduce input stage transconductance near the center of the common-mode input voltage swing, thereby reducing differential-mode gain near the center of the swing, and reducing gain variations across the input common-mode range. The differential amplifier can include multiple input legs on either side of an input stage. Multiple legs allow multiple reference voltages to be compared to a data signal. A bidirectional data link utilizes the multiple reference inputs to remove an ambiguity created by the bidirectional data link.
摘要翻译：互补输入自偏置差分放大器包括增益补偿装置。增益补偿装置与输入晶体管并联并由自偏压节点偏置。增益控制装置用于在共模极端工作时保持电流在负载装置中流动，从而限制了放大器输出阻抗的减小，并限制了共模极限下差分模式增益的相应降低。增益控制装置还用于减小共模输入电压摆幅中心附近的输入级跨导，从而减小摆幅中心附近的差模增益，并减少输入共模范围内的增益变化。差分放大器可以包括输入级两侧的多个输入支路。多个支路允许将多个参考电压与数据信号进行比较。双向数据链路利用多个参考输入来消除由双向数据链路创建的歧义。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式