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1. 发明授权

US07177288B2 Simultaneous transmission and reception of signals in different frequency bands over a bus line 有权
标题翻译：在总线上同时发送和接收不同频段的信号
公开(公告)号：US07177288B2
公开(公告)日：2007-02-13
申请号：US09998008
申请日：2001-11-28
申请人： Stephen R. Mooney , Aaron K. Martin , Matthew B. Haycock , Bryan K. Casper , Shekhar Y. Borkar , Joseph T. Kennedy , James E. Jaussi
发明人： Stephen R. Mooney , Aaron K. Martin , Matthew B. Haycock , Bryan K. Casper , Shekhar Y. Borkar , Joseph T. Kennedy , James E. Jaussi
IPC分类号： H04L5/14
CPC分类号： H04L5/1423
摘要： A device includes a bus, a first transmitter connected to the bus and configured to transmit a first signal over the bus in a first frequency band, a second transmitter connected to the bus and configured to transmit a second signal over the bus in a second frequency band at the same time that the first transmitter is transmitting the first signal, a first receiver connected to the bus and configured to receive the first signal transmitted over the bus in the first frequency band, and a second receiver connected to the bus and configured to receive the second signal transmitted over the bus in the second frequency band. The first frequency band and the second frequency band occupy different portions of the frequency spectrum.
摘要翻译：一种设备包括总线，连接到总线的第一发射机，并且被配置为在第一频带中通过总线传输第一信号，第二发射器连接到总线并且被配置为以第二频率通过总线发送第二信号与第一发射机正在发送第一信号的同时，连接到总线并被配置为接收通过总线在第一频带中发送的第一信号的第一接收机和连接到总线的第二接收机，并且被配置为接收在第二频带中通过总线发送的第二信号。第一频带和第二频带占据频谱的不同部分。

2. 发明授权

US06437601B1 Using a timing strobe for synchronization and validation in a digital logic device 有权
标题翻译：在数字逻辑器件中使用定时选通器进行同步和验证
公开(公告)号：US06437601B1
公开(公告)日：2002-08-20
申请号：US09752906
申请日：2000-12-26
申请人： Shekhar Y. Borkar , Matthew B. Haycock , Stephen R. Mooney , Aaron K. Martin , Joseph T. Kennedy
发明人： Shekhar Y. Borkar , Matthew B. Haycock , Stephen R. Mooney , Aaron K. Martin , Joseph T. Kennedy
IPC分类号： H03K19096
CPC分类号： G11C7/222 , G11C7/22 , H03L7/00 , H03L7/0812 , H04L7/0008
摘要： In an electronic system having first and second logic devices, a free running on-chip clock signal is generated by the first logic device, where the signal has a frequency that is controlled to match that of a global free-running clock signal received by both devices. The on-chip clock signal is synchronized to a strobe signal received by the first device and that was transmitted in association with a data signal by the second device. A logic function is repeatedly performed as synchronized by the first clock signal, to repeatedly generate one or more bits from the data signal.
摘要翻译：在具有第一和第二逻辑器件的电子系统中，由第一逻辑器件产生自由运行的片上时钟信号，其中信号的频率被控制以匹配由两者接收的全局自由运行时钟信号的频率设备。片上时钟信号与第一器件接收的选通信号同步，并与第二器件与数据信号相关联地发送。重复执行由第一时钟信号同步的逻辑功能，以从数据信号重复产生一个或多个位。

3. 发明授权

US06373289B1 Data and strobe repeater having a frequency control unit to re-time the data and reject delay variation in the strobe 有权
标题翻译：具有频率控制单元的数据和选通中继器，用于对数据进行重新计时并拒绝选通脉冲的延迟变化
公开(公告)号：US06373289B1
公开(公告)日：2002-04-16
申请号：US09752895
申请日：2000-12-26
申请人： Aaron K. Martin , Stephen R. Mooney , Joseph T. Kennedy , Matthew B. Haycock , Shekhar Y. Borkar
发明人： Aaron K. Martin , Stephen R. Mooney , Joseph T. Kennedy , Matthew B. Haycock , Shekhar Y. Borkar
IPC分类号： H03K1900
CPC分类号： H03L7/0812 , H03K5/135 , H04L25/242
摘要： A frequency control unit has an input to receive a digital downstream strobe signal and an output to provide a controlled delay to the input strobe signal. A downstream latch has a data input to receive a digital downstream data signal and a clock input coupled to the output of the frequency control unit. The controlled delay is essentially equal to a set up time of the latch. A delay element coupled to the output of the frequency control unit further delays the downstream strobe signal by essentially a propagation time of the latch. Output drivers are coupled to the outputs of the latch and the delay element.
摘要翻译：频率控制单元具有用于接收数字下行选通信号和输出的输入，以向输入选通信号提供受控的延迟。下游锁存器具有用于接收数字下行数据信号的数据输入和耦合到频率控制单元的输出的时钟输入。受控延迟基本上等于锁存器的设定时间。耦合到频率控制单元的输出的延迟元件进一步延迟下游选通信号基本上是锁存器的传播时间。输出驱动器耦合到锁存器和延迟元件的输出。

4. 发明申请

US20080181331A1 Pulse amplitude modulated system with reduced intersymbol interference 有权
公开(公告)号：US20080181331A1
公开(公告)日：2008-07-31
申请号：US12077987
申请日：2008-03-24
申请人： Bryan K. Casper , Shekhar Y. Borkar , Stephen R. Mooney , Aaron K. Martin , Joseph T. Kennedy , Matthew B. Haycock , James E. Jaussi
发明人： Bryan K. Casper , Shekhar Y. Borkar , Stephen R. Mooney , Aaron K. Martin , Joseph T. Kennedy , Matthew B. Haycock , James E. Jaussi
IPC分类号： H03K7/02 , H03D1/24 , H03K9/02 , H04L27/04
CPC分类号： H04L25/4917
摘要： A system and method for encoding and receiving data is provided. The data is encoded as a pulse amplitude modulated signal such that the amplitude signals do not transition from the highest signal level to the lowest signal level and do not transition from the lowest signal level to the highest signal level. The encoding and decoding is performed in some embodiments via a lookup table, and in further embodiments is designed to minimize the step between sequential pulse amplitude modulated symbols.

5. 发明授权

US07171510B2 On-chip observability buffer to observer bus traffic 失效
标题翻译：观察员总线流量的片上可观察性缓冲区
公开(公告)号：US07171510B2
公开(公告)日：2007-01-30
申请号：US09752880
申请日：2000-12-28
申请人： Matthew B. Haycock , Shekhar Y. Borkar , Stephen R. Mooney , Aaron K. Martin , Joseph T. Kennedy
发明人： Matthew B. Haycock , Shekhar Y. Borkar , Stephen R. Mooney , Aaron K. Martin , Joseph T. Kennedy
IPC分类号： G06F13/36 , G06F13/14 , G06F11/00 , G01R31/00 , G01R31/14
CPC分类号： G06F11/221
摘要： The invention provides, in an embodiment, an apparatus, method and means for unintrusively observing, echoing and reading signals transmitted by one of a bus and wireless communication, without disturbing electrical properties of the bus, without adding bus latency, and without adding signal discontinuities. In an aspect, a buffer having a trigger is coupled with a component that connects to a memory bus, the buffer echoes signals to an observability port, and a diagnostic device reads the echoed signals. In an aspect, the bus is one of a simultaneous bi-directional (SBD) bus having ternary logic levels, a single ended bus, a differential bus, an optically coupled bus, a chipset bus, a frontside bus, an input/output (I/O) bus, a peripheral component interface (PCI) bus, and an industry standard architecture (ISA) bus. In an aspect, the buffer echoes bus signals having frequencies between 500 MHz. and 5 GHz. In an aspect, the buffer echoes bus signals having frequencies of at least 5 GHz.
摘要翻译：本发明在一个实施例中提供了一种用于非干涉地观察，回送和读取由总线和无线通信之一发送的信号而不干扰总线的电气特性而不增加总线等待时间并且不增加信号不连续性的装置，方法和装置。在一方面，具有触发器的缓冲器与连接到存储器总线的部件耦合，缓冲器将信号回送到可观测端口，并且诊断装置读取回送信号。一方面，总线是具有三元逻辑电平的同时双向（SBD）总线之一，单端总线，差分总线，光耦合总线，芯片组总线，前端总线，输入/输出（ I / O）总线，外设组件接口（PCI）总线和工业标准架构（ISA）总线。在一个方面，缓冲器回波频率在500MHz之间的总线信号。和5 GHz。在一方面，缓冲器响应具有至少5GHz频率的总线信号。

6. 发明授权

US06538584B2 Transition reduction encoder using current and last bit sets 失效
标题翻译：使用当前位和最后位的转换减速编码器
公开(公告)号：US06538584B2
公开(公告)日：2003-03-25
申请号：US09752883
申请日：2000-12-28
申请人： Shekhar Y. Borkar , Matthew B. Haycock , Stephen R. Mooney , Aaron K. Martin , Joseph T. Kennedy
发明人： Shekhar Y. Borkar , Matthew B. Haycock , Stephen R. Mooney , Aaron K. Martin , Joseph T. Kennedy
IPC分类号： H03M700
CPC分类号： G11C7/10
摘要： In some embodiments, the invention involves a circuit including a first set of conductors to carry a current bit set and last bit set circuitry to hold and provide a last bit set. The circuit also includes drivers coupled to interconnect conductors to provide signals from the drivers to the interconnect conductors and an encoder to receive the last bit set and the current bit set and determine whether to provide the current bit set or an encoded version of the current bit set to the drivers.
摘要翻译：在一些实施例中，本发明涉及包括第一组导体的电路，以承载当前位组和最后位组电路以保持并提供最后位组。电路还包括耦合到互连导体的驱动器以提供从驱动器到互连导体的信号，以及用于接收最后位组和当前位组的编码器，并确定是提供当前位组还是当前位的编码版本设置为司机。

7. 发明授权

US06441649B1 Rail-to-rail input clocked amplifier 失效
标题翻译：轨至轨输入时钟放大器
公开(公告)号：US06441649B1
公开(公告)日：2002-08-27
申请号：US09752647
申请日：2000-12-29
申请人： Aaron K. Martin , Stephen R. Mooney , Joseph T. Kennedy , Matthew B. Haycock , Shekhar Y. Borkar
发明人： Aaron K. Martin , Stephen R. Mooney , Joseph T. Kennedy , Matthew B. Haycock , Shekhar Y. Borkar
IPC分类号： G01R1900
CPC分类号： H03K3/356191 , H03K3/35613
摘要： The invention provides an apparatus, method and means for capturing data. In an aspect, a differential and complementary input folded-cascode clocked amplifier is provided. In an aspect, the invention provides rail-to-rail input common-mode voltage range. In an aspect, the invention provides a setup/hold time window that is smaller than the setup/hold time window of a conventional clocked amplifier and a conventional input amplifier with a separate amplifier and latch. In an aspect, the invention provides high common-mode rejection as compared with conventional clocked sense amplifiers.
摘要翻译：本发明提供了一种用于捕获数据的装置，方法和装置。在一方面，提供差分和互补输入折叠共源共栅时钟放大器。在一方面，本发明提供轨至轨输入共模电压范围。在一方面，本发明提供了一种建立/保持时间窗口，其小于常规时钟放大器和具有单独放大器和锁存器的常规输入放大器的建立/保持时间窗口。在一方面，与传统的时钟感测放大器相比，本发明提供了高共模抑制。

8. 发明授权

US06847617B2 Systems for interchip communication 有权
标题翻译：芯片间通信系统
公开(公告)号：US06847617B2
公开(公告)日：2005-01-25
申请号：US09817659
申请日：2001-03-26
申请人： Shekhar Y Borkar , Matthew B. Haycock , Stephen R. Mooney , Aaron K. Martin , Joseph T. Kennedy
发明人： Shekhar Y Borkar , Matthew B. Haycock , Stephen R. Mooney , Aaron K. Martin , Joseph T. Kennedy
IPC分类号： G06F13/00 , G06F13/38 , G06F13/40 , H04L12/28
CPC分类号： G06F13/4086
摘要： In some embodiments, the invention involves a system having a first group of integrated circuits connected in a truncated ring fashion, wherein the truncated ring includes a truncated region to allow for additional integrated circuits to be added to the ring. In some embodiments, the invention involves a system having a group of integrated circuits connected in a pseudo ring fashion, wherein the pseudo ring is created by data flow of bi-directional signaling between the integrated circuits. In some embodiments, the invention involves a system having a group of integrated circuits connected in a pseudo differential arrangement in which multiple conductors carrying signals share a common reference signal conductor.
摘要翻译：在一些实施例中，本发明涉及具有以截头环方式连接的第一组集成电路的系统，其中所述截头环包括截取的区域，以允许将额外的集成电路添加到所述环中。在一些实施例中，本发明涉及具有以伪环方式连接的一组集成电路的系统，其中通过集成电路之间的双向信令的数据流创建伪环。在一些实施例中，本发明涉及一种具有以伪差分布置连接的一组集成电路的系统，其中携带多个导体的信号共用公共参考信号导体。

9. 发明授权

US06747474B2 Integrated circuit stubs in a point-to-point system 有权
标题翻译：集成电路存根在点对点系统中
公开(公告)号：US06747474B2
公开(公告)日：2004-06-08
申请号：US09797480
申请日：2001-02-28
申请人： Shekhar Y. Borkar , Matthew B. Haycock , Stephen R. Mooney , Aaron K. Martin , Joseph T. Kennedy
发明人： Shekhar Y. Borkar , Matthew B. Haycock , Stephen R. Mooney , Aaron K. Martin , Joseph T. Kennedy
IPC分类号： H03K1716
CPC分类号： H04L5/14 , H03K19/01759 , H04L25/0278 , H04L25/24
摘要： In some embodiments, the invention involves multiple integrated circuit stubs coupled in series. At least one of the integrated circuit stubs including first conductors to receive signals from a first adjacent one of the integrated circuit stubs, second conductors to provide signals to a second adjacent one of the integrated circuit stubs, and third conductors to provide signals to an integrated circuit chip. The integrated circuit stubs include first drivers and second drivers coupled to the first, second, and third conductors, wherein the first drivers receive the external signals from the first conductors and drive them onto the second conductors and the second drivers receive signals from the first conductors and drive them onto the third conductors.
摘要翻译：在一些实施例中，本发明涉及串联耦合的多个集成电路短截线。所述集成电路短截线中的至少一个包括用于接收来自所述集成电路短截线中的第一相邻一个的信号的第一导体，用于向所述集成电路短截线中的第二相邻组件提供信号的第二导体以及向集成电路短截线提供信号的第三导体电路芯片。集成电路短截线包括耦合到第一，第二和第三导体的第一驱动器和第二驱动器，其中第一驱动器接收来自第一导体的外部信号并将它们驱动到第二导体上，并且第二驱动器从第一导体接收信号并将它们驱动到第三导体上。

10. 发明授权

US06741107B2 Synchronous clock generator for integrated circuits 有权
标题翻译：用于集成电路的同步时钟发生器
公开(公告)号：US06741107B2
公开(公告)日：2004-05-25
申请号：US09802584
申请日：2001-03-08
申请人： Shekhar Y. Borkar , Matthew B. Haycock , Stephen R. Mooney , Aaron K. Martin , Joseph T. Kennedy
发明人： Shekhar Y. Borkar , Matthew B. Haycock , Stephen R. Mooney , Aaron K. Martin , Joseph T. Kennedy
IPC分类号： H03L700
CPC分类号： H03L7/0805 , H03L7/0812
摘要： A synchronous clock generator for an integrated circuit is described in which a delay lock loop circuit may be used to delay a first input signal. A delay circuit is coupled to the delay lock loop circuit and receives a control voltage from the delay lock loop circuit, which is used to delay a second input signal. The first and second input signal may be complimentary.
摘要翻译：描述了用于集成电路的同步时钟发生器，其中可以使用延迟锁定环路来延迟第一输入信号。延迟电路耦合到延迟锁定环电路并且从延迟锁定环路电路接收用于延迟第二输入信号的控制电压。第一和第二输入信号可以是互补的。

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