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1. 发明申请

US20140029143A1 RECEIVER HAVING A WIDE COMMON MODE INPUT RANGE 有权
标题翻译：具有广泛共通模式输入范围的接收器
公开(公告)号：US20140029143A1
公开(公告)日：2014-01-30
申请号：US13560944
申请日：2012-07-27
申请人： Siok Wei Lim , Cheng-Hsiang Hsieh , Jafar Savoj
发明人： Siok Wei Lim , Cheng-Hsiang Hsieh , Jafar Savoj
IPC分类号： H02H9/04 , H03F3/45
CPC分类号： H03F1/523 , H03F3/45224 , H03F3/45233 , H03F3/72 , H03F2200/444 , H03F2203/45091 , H03F2203/45092 , H03F2203/45466 , H03F2203/45494 , H03F2203/45568 , H03H11/1213 , H04L25/0276 , H04L27/0002
摘要： In one embodiment, a differential amplifier is provided. Gates of a first differential pair of transistors, of a first conductivity type, and a second pair or transistors, of a second conductivity type are coupled to first and second input terminals of the differential amplifier. A first pair of adjustable current sources are configured to adjust respective tail currents of the first differential pair of transistors in response to a first bias current control signal. A second pair of adjustable current sources are configured to adjust respective tail currents of the second differential pair of transistors in response to the first bias current control signal. A third pair of adjustable current sources are configured to adjust respective currents through the second differential pair of transistors in response to a second bias current control signal.
摘要翻译：在一个实施例中，提供了差分放大器。具有第二导电类型的第一导电类型和第二对晶体管的第一差分对晶体管的栅极耦合到差分放大器的第一和第二输入端。第一对可调电流源被配置为响应于第一偏置电流控制信号来调整第一差分对晶体管的相应尾电流。第二对可调电流源被配置为响应于第一偏置电流控制信号来调整第二差分对晶体管的相应尾电流。第三对可调电流源被配置为响应于第二偏置电流控制信号来调节通过第二差分对晶体管的相应电流。

2. 发明授权

US07737782B1 Operational amplifier circuit 有权
标题翻译：运算放大器电路
公开(公告)号：US07737782B1
公开(公告)日：2010-06-15
申请号：US12355264
申请日：2009-01-16
申请人： Minoru Sudou
发明人： Minoru Sudou
IPC分类号： H03F3/45
CPC分类号： H03F3/45233 , H03F2203/45292
摘要： Provided is a CMOS operational amplifier circuit that can operate with low noise, with low current consumption, and with stability. A cascode bias voltage of a folded cascode circuit in the CMOS operational amplifier circuit is modulated by a current at an input differential stage, thereby enabling operation with low noise, with low current consumption, and with stability.
摘要翻译：提供了可以以低噪声，低电流消耗和稳定运行的CMOS运算放大器电路。 CMOS运算放大器电路中的折叠共源共栅电路的共源共栅偏置电压由输入差分级的电流调制，从而能够以低噪声，低电流消耗和稳定运行。

3. 发明申请

US20190007014A1 SEMICONDUCTOR DEVICE 审中-公开
公开(公告)号：US20190007014A1
公开(公告)日：2019-01-03
申请号：US15988016
申请日：2018-05-24
申请人： Renesas Electronics Corporation
发明人： Yasufumi SUZUKI
IPC分类号： H03F3/45 , H03F1/30 , H03F1/52 , H03F3/72
CPC分类号： H03F3/45233 , H03F1/301 , H03F1/523 , H03F3/45183 , H03F3/72
摘要： An object of the present invention is to provide a semiconductor device amplifying input voltages of various standards across a wide range. According to an embodiment, a semiconductor device includes a first differential amplifier that performs an amplifying operation in a first voltage range, a second differential amplifier that performs an amplifying operation in a second voltage range, a first protection unit that conducts between the source and the drain of each pair of differential transistors included in the first and second differential amplifiers in a third voltage range, a third differential amplifier that performs an amplifying operation in a fourth voltage range, a fourth differential amplifier that performs an amplifying operation in a fifth voltage range, and a second protection unit that conducts between the source and the drain of each pair of differential transistors included in the third and fourth differential amplifiers in a sixth voltage range.

4. 发明申请

US20110242145A1 DISPLAY DEVICE, DIFFERENTIAL AMPLIFIER, AND DATA LINE DRIVE METHOD FOR DISPLAY DEVICE 审中-公开
标题翻译：显示装置，差分放大器和用于显示装置的数据线驱动方法
公开(公告)号：US20110242145A1
公开(公告)日：2011-10-06
申请号：US13074818
申请日：2011-03-29
申请人： Kouichi NISHIMURA , Masamitsu NAKAOKA
发明人： Kouichi NISHIMURA , Masamitsu NAKAOKA
IPC分类号： G09G5/10 , H03F3/45
CPC分类号： G09G3/3688 , G09G3/3614 , G09G2310/027 , G09G2310/0291 , H03F3/45233 , H03F2203/45726
摘要： A display device is provided with a plurality of differential amplifiers associated with a plurality of data lines within a display panel. Each of the plurality of differential amplifiers includes: an output stage circuit including a first transistor having a source connected to the positive power supply and a second transistor having a source connected to the negative power supply, an output terminal connected to drains of the first and second transistors; and a bias control circuit provided between the adder circuit and the output stage circuit to achieve bias control of gates of the first and second transistors. During the switching period, the output stage circuit provides short-circuiting between the gate and source of each of the first and second transistors, and the bias control circuit cuts off a current path between the gates of the first and second transistors during the switching period.
摘要翻译：显示装置设置有与显示面板内的多条数据线相关联的多个差分放大器。所述多个差分放大器中的每一个包括：输出级电路，包括具有连接到所述正电源的源极的第一晶体管和连接到所述负电源的源极的第二晶体管，连接到所述第一和第二漏极的漏极的输出端子，第二晶体管; 以及设置在加法器电路和输出级电路之间以实现第一和第二晶体管的栅极的偏置控制的偏置控制电路。在开关周期期间，输出级电路在第一和第二晶体管中的每一个的栅极和源极之间提供短路，偏置控制电路在开关周期期间切断第一和第二晶体管的栅极之间的电流路径。

5. 发明申请

US20170250663A1 DIFFERENTIAL AMPLIFIER, RECEIVER, AND CIRCUIT 审中-公开
公开(公告)号：US20170250663A1
公开(公告)日：2017-08-31
申请号：US15521736
申请日：2015-10-20
申请人： SONY CORPORATION
发明人： HIROSHI NAKAO , YUKIHIRO YASUI
IPC分类号： H03F3/45 , H04B1/16 , H03F1/34
CPC分类号： H03F3/45233 , H03F1/0277 , H03F1/3211 , H03F1/342 , H03F3/45 , H03F3/45219 , H03F3/45475 , H03F3/68 , H03F3/72 , H03F2203/45288 , H04B1/16
摘要： A differential amplifier which does not have an effect of noise resistance deterioration, waveform distortion, and a lower bandwidth while having a wide input range is realized. The differential amplifier does not cause deterioration in a signal quality due to an increase in an input load, and it is not necessary to additionally provide a configuration for generating a reference voltage. The differential amplifier includes a differential amplification circuit and an output circuit for amplifying and outputting a differential output from the differential amplification circuit. The differential amplification circuit includes a first conductive type first differential pair which supplies output currents according to a positive phase input signal and a reverse phase input signal to the output circuit, a second conductive type second differential pair which supplies output currents according to a positive phase input signal and a reverse phase input signal to the output circuit, a detector which detects an operation state of a differential pair, and an alternative current supplying circuit which supplies an alternative current for the output current of the differential pair which has been turned off to the output circuit.

6. 发明授权

US09473092B2 Reconfigurable amplifier 有权
标题翻译：可重构放大器
公开(公告)号：US09473092B2
公开(公告)日：2016-10-18
申请号：US14587863
申请日：2014-12-31
申请人： Texas Instruments Incorporated
发明人： Dina Reda El-Damak , Rajarshi Mukhopadhyay , Jeffrey Anthony Morroni
IPC分类号： H03F3/45
CPC分类号： H03F3/45645 , H03F3/3028 , H03F3/45206 , H03F3/45233 , H03F3/45273 , H03F3/45771 , H03F2203/45002 , H03F2203/45048 , H03F2203/45078 , H03F2203/45116
摘要： An amplifier receives a differential signal and, in response, generates a first negative input current and a first positive input current. In a first operating mode, the amplifier receives a second differential signal, and, in response, generates a second negative input current and a second positive input current. In a second operating mode, the amplifier receives the second differential signal, and, in response, generates a third negative input current and a third positive input current. When the device is operating in the first operating mode, the first negative input current is summed with the second negative input current and the first positive input current is summed with the second positive input current. When the device is operating in the second operating mode, the first negative input current is summed with the third negative input current and the first positive input current is summed with the third positive input current.
摘要翻译：放大器接收差分信号，作为响应，产生第一负输入电流和第一正输入电流。在第一操作模式中，放大器接收第二差分信号，并且作为响应，产生第二负输入电流和第二正输入电流。在第二操作模式中，放大器接收第二差分信号，并且作为响应，产生第三负输入电流和第三正输入电流。当器件在第一工作模式下工作时，第一个负输入电流与第二个负输入电流相加，第一个正输入电流与第二个正输入电流相加。当器件在第二工作模式下工作时，第一个负输入电流与第三个负输入电流相加，第一个正输入电流与第三个正输入电流相加。

7. 发明授权

US06304141B1 Complementary input self-biased differential amplifier with gain compensation 有权
标题翻译：具有增益补偿的互补输入自偏置差分放大器
公开(公告)号：US06304141B1
公开(公告)日：2001-10-16
申请号：US09609495
申请日：2000-06-30
申请人： Joseph T. Kennedy , Stephen R. Mooney , Aaron K. Martin , Rajendran Nair
发明人： Joseph T. Kennedy , Stephen R. Mooney , Aaron K. Martin , Rajendran Nair
IPC分类号： H03F345
CPC分类号： H03F3/45233 , H03F3/3028 , H03F3/45237 , H03F2203/45371 , H03F2203/45451 , H03F2203/45454 , H03F2203/45708
摘要： A complementary input self-biased differential amplifier includes gain compensation devices. The gain compensation devices are in parallel with input transistors and are biased by a self-bias node. The gain control devices serve to keep current flowing in load devices when operating at common-mode extremes, thereby limiting the reduction in amplifier output impedance and limiting the corresponding reduction in differential-mode gain at common-mode extremes. The gain control devices also serve to reduce input stage transconductance near the center of the common-mode input voltage swing, thereby reducing differential-mode gain near the center of the swing, and reducing gain variations across the input common-mode range. The differential amplifier can include multiple input legs on either side of an input stage. Multiple legs allow multiple reference voltages to be compared to a data signal. A bidirectional data link utilizes the multiple reference inputs to remove an ambiguity created by the bidirectional data link.
摘要翻译：互补输入自偏置差分放大器包括增益补偿装置。增益补偿装置与输入晶体管并联并由自偏压节点偏置。增益控制装置用于在共模极端工作时保持电流在负载装置中流动，从而限制了放大器输出阻抗的减小，并限制了共模极限下差分模式增益的相应降低。增益控制装置还用于减小共模输入电压摆幅中心附近的输入级跨导，从而减小摆幅中心附近的差模增益，并减少输入共模范围内的增益变化。差分放大器可以包括输入级两侧的多个输入支路。多个支路允许将多个参考电压与数据信号进行比较。双向数据链路利用多个参考输入来消除由双向数据链路创建的歧义。

8. 发明授权

US09306509B2 Receiver having a wide common mode input range 有权
标题翻译：接收机具有宽共模输入范围
公开(公告)号：US09306509B2
公开(公告)日：2016-04-05
申请号：US13560944
申请日：2012-07-27
申请人： Siok Wei Lim , Cheng-Hsiang Hsieh , Jafar Savoj
发明人： Siok Wei Lim , Cheng-Hsiang Hsieh , Jafar Savoj
IPC分类号： H02H9/00 , H03F1/52 , H03F3/45 , H03F3/72 , H04L27/00 , H03H11/12 , H04L25/02
CPC分类号： H03F1/523 , H03F3/45224 , H03F3/45233 , H03F3/72 , H03F2200/444 , H03F2203/45091 , H03F2203/45092 , H03F2203/45466 , H03F2203/45494 , H03F2203/45568 , H03H11/1213 , H04L25/0276 , H04L27/0002
摘要： In one embodiment, a differential amplifier is provided. Gates of a first differential pair of transistors, of a first conductivity type, and a second pair or transistors, of a second conductivity type are coupled to first and second input terminals of the differential amplifier. A first pair of adjustable current sources are configured to adjust respective tail currents of the first differential pair of transistors in response to a first bias current control signal. A second pair of adjustable current sources are configured to adjust respective tail currents of the second differential pair of transistors in response to the first bias current control signal. A third pair of adjustable current sources are configured to adjust respective currents through the second differential pair of transistors in response to a second bias current control signal.
摘要翻译：在一个实施例中，提供了差分放大器。具有第二导电类型的第一导电类型和第二对晶体管的第一差分对晶体管的栅极耦合到差分放大器的第一和第二输入端。第一对可调电流源被配置为响应于第一偏置电流控制信号来调整第一差分对晶体管的相应尾电流。第二对可调电流源被配置为响应于第一偏置电流控制信号来调整第二差分对晶体管的相应尾电流。第三对可调电流源被配置为响应于第二偏置电流控制信号来调节通过第二差分对晶体管的相应电流。

9. 发明申请

US20110285466A1 POWER AMPLIFIER CIRCUIT 审中-公开
标题翻译：功率放大器电路
公开(公告)号：US20110285466A1
公开(公告)日：2011-11-24
申请号：US13036344
申请日：2011-02-28
申请人： Takayuki Takida , Ryota Miwa
发明人： Takayuki Takida , Ryota Miwa
IPC分类号： H03F3/04
CPC分类号： H03F3/45233 , H03F3/3028 , H03F2200/456 , H03F2203/45028
摘要： A power amplifier circuit has a Gm amplifier, first and second transistors, third and fourth transistors consisting a mirror circuit, fifth and sixth transistors consisting a mirror circuit, seventh and eighth transistors consisting a mirror circuit, a ninth transistor of the first conductivity type which is connected at a first end thereof to the first power supply rail, connected at a second end thereof to a signal output terminal for outputting an amplified signal, and connected at a control terminal thereof to the inverting output terminal, and a tenth transistor of the second conductivity type connected at a first end thereof to the signal output terminal, connected at a second end thereof to the second power supply rail, and connected at a control terminal thereof to the noninverting output terminal.
摘要翻译：功率放大器电路具有Gm放大器，第一和第二晶体管，第三和第四晶体管构成镜电路，第五和第六晶体管由镜电路组成，第七和第八晶体管包括镜电路，第一导电类型的第九晶体管，在其第一端连接到第一电源轨，其第二端连接到用于输出放大信号的信号输出端，并且在其控制端连接到反相输出端;以及第十晶体管，第二导电类型在其第一端连接到信号输出端，其第二端连接到第二电源轨，并在其控制端连接到同相输出端。

10. 发明授权

US06249153B1 High slew rate input differential pair with common mode input to ground 有权
标题翻译：高压摆率输入差分对，共模输入接地
公开(公告)号：US06249153B1
公开(公告)日：2001-06-19
申请号：US09318399
申请日：1999-05-25
申请人： Farhood Moraveji
发明人： Farhood Moraveji
IPC分类号： H03F345
CPC分类号： H03F3/45125 , H03F3/45098 , H03F3/45134 , H03F3/4517 , H03F3/45197 , H03F3/45224 , H03F3/45233 , H03F3/45269 , H03F2203/45248 , H03F2203/45454 , H03F2203/45458 , H03F2203/45648 , H03F2203/45682
摘要： A differential pair includes a first and second transistors each having a control terminal coupled to a first input voltage, and a third and fourth transistors each having a control terminal coupled to a second input voltage. The first, second, third, and fourth transistors each has a first current handling terminal coupled to a reference voltage. The first and second transistors each has a second current handling terminal coupled to a first current mirror. The third and fourth transistors each has a second current handling terminal coupled to a second current mirror. A resistor is coupled between the second current handling terminals of the second and third transistors. The differential pair is capable of attaining a high slew rate and a possible common mode input voltage of ground while drawing only a small quiescent current.
摘要翻译：差分对包括每个具有耦合到第一输入电压的控制端的第一和第二晶体管，以及分别具有耦合到第二输入电压的控制端的第三和第四晶体管。第一，第二，第三和第四晶体管各自具有耦合到参考电压的第一电流处理端子。第一和第二晶体管各自具有耦合到第一电流镜的第二电流处理终端。第三和第四晶体管各自具有耦合到第二电流镜的第二电流处理终端。电阻器耦合在第二和第三晶体管的第二电流处理端子之间。差分对能够获得高转换速率和可能的共模输入电压，同时仅获得较小的静态电流。

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