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61. 发明申请

US20070189076A1 Memory elements and methods of using the same 失效
标题翻译：内存元素和使用方法
公开(公告)号：US20070189076A1
公开(公告)日：2007-08-16
申请号：US11353493
申请日：2006-02-14
申请人： Wagdi Abadeer , Anthony Bonaccio , Jack Mandelman , William Tonti , Sebastian Ventrone
发明人： Wagdi Abadeer , Anthony Bonaccio , Jack Mandelman , William Tonti , Sebastian Ventrone
IPC分类号： G11C16/04
CPC分类号： G11C16/0466
摘要： In a first aspect, a first apparatus is provided. The first apparatus is a memory element that includes (1) one or more MOSFETs each including a dielectric material having a dielectric constant of about 3.9 to about 25; and (2) control logic coupled to at least one of the one or more MOSFETs. The control logic is adapted to (a) cause the memory element to operate in a first mode to store data; and (b) cause the memory element to operate in a second mode to change a threshold voltage of at least one of the one or more MOSFETs from an original threshold voltage to a changed threshold voltage such that the changed threshold voltage affects data stored by the memory element when operated in the first mode. Numerous other aspects are provided.
摘要翻译：在第一方面中，提供了一种第一装置。第一装置是存储元件，其包括（1）一个或多个MOSFET，每个MOSFET包括具有约3.9至约25的介电常数的电介质材料; 和（2）耦合到所述一个或多个MOSFET中的至少一个的控制逻辑。控制逻辑适于（a）使存储元件以第一模式操作以存储数据; 和（b）使存储元件在第二模式下操作以将一个或多个MOSFET中的至少一个的阈值电压从原始阈值电压改变到改变的阈值电压，使得改变的阈值电压影响由存储元件在第一模式下操作。提供了许多其他方面。

62. 发明申请

US20070158779A1 Methods and semiconductor structures for latch-up suppression using a buried damage layer 审中-公开
标题翻译：使用掩埋损伤层进行闩锁抑制的方法和半导体结构
公开(公告)号：US20070158779A1
公开(公告)日：2007-07-12
申请号：US11330688
申请日：2006-01-12
申请人： Ethan Cannon , Toshiharu Furukawa , Robert Gauthier , David Horak , Jack Mandelman , William Tonti
发明人： Ethan Cannon , Toshiharu Furukawa , Robert Gauthier , David Horak , Jack Mandelman , William Tonti
IPC分类号： H01L29/00
CPC分类号： H01L21/26506 , H01L21/26513 , H01L21/2658 , H01L21/823892 , H01L27/0921
摘要： Semiconductor structures and methods for suppressing latch-up in bulk CMOS devices. The structure comprises a damage layer formed in a substrate, a first doped well formed in the substrate, and a second doped well formed in the substrate proximate to the first doped well. The damage layer extends within the substrate to intersect the first and second doped wells. The damage layer may be formed by ion implantation followed by growth of an epitaxial layer to segregate the active device regions from the damage layer.
摘要翻译：用于抑制大量CMOS器件中的闩锁的半导体结构和方法。该结构包括形成在衬底中的损伤层，在衬底中形成的第一掺杂阱，以及在靠近第一掺杂阱的衬底中形成的第二掺杂阱。损伤层在衬底内延伸以与第一和第二掺杂阱相交。可以通过离子注入形成损伤层，随后生长外延层以使有源器件区域与损伤层分离。

63. 发明申请

US20070148836A1 Reduced-resistance finFETs and methods of manufacturing the same 有权
标题翻译：降低电阻finFET及其制造方法
公开(公告)号：US20070148836A1
公开(公告)日：2007-06-28
申请号：US11316244
申请日：2005-12-22
申请人： Kangguo Cheng , Louis Hsu , Jack Mandelman , Haining Yang
发明人： Kangguo Cheng , Louis Hsu , Jack Mandelman , Haining Yang
IPC分类号： H01L21/84 , H01L21/336
CPC分类号： H01L29/785 , H01L21/823418 , H01L21/823437 , H01L29/41791 , H01L29/665 , H01L29/6653 , H01L29/66795 , H01L29/78618 , H01L2029/7858 , Y10S438/96
摘要： In a first aspect, a first method of manufacturing a finFET is provided. The first method includes the steps of (1) providing a substrate; and (2) forming at least one source/drain diffusion region of the finFET on the substrate. Each source/drain diffusion region includes (a) an interior region of unsilicided silicon; and (b) silicide formed on a top surface and sidewalls of the region of unsilicided silicon. Numerous other aspects are provided.
摘要翻译：在第一方面，提供了制造finFET的第一种方法。第一种方法包括以下步骤：（1）提供衬底; 和（2）在所述衬底上形成所述finFET的至少一个源极/漏极扩散区域。每个源极/漏极扩散区域包括（a）非硅化硅的内部区域; 和（b）硅化物形成在非硅化硅区域的顶表面和侧壁上。提供了许多其他方面。

64. 发明授权

US07227230B2 Low-K gate spacers by fluorine implantation 有权
标题翻译：通过氟注入的低K栅间隔
公开(公告)号：US07227230B2
公开(公告)日：2007-06-05
申请号：US10775440
申请日：2004-02-10
申请人： Jeffrey P. Gambino , Jack Mandelman , William R. Tonti
发明人： Jeffrey P. Gambino , Jack Mandelman , William R. Tonti
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/6659 , H01L21/26506 , H01L21/26586 , H01L21/31155 , H01L29/4983 , H01L29/6656 , Y10S257/90
摘要： A MOSFET device and a method of fabricating a MOSFET device having low-K dielectric oxide gate sidewall spacers produced by fluorine implantation. The present invention implants fluorine into the gate oxide sidewall spacers which is used to alter the properties of advanced composite gate dielectrics e.g. nitridized oxides, NO, and gate sidewall dielectrics, such that the low-K properties of fluorine are used to develop low parasitic capacitance MOSFETs.
摘要翻译： MOSFET器件和制造具有通过氟注入产生的低K电介质氧化物栅极侧壁间隔物的MOSFET器件的方法。本发明将氟注入到栅极氧化物侧壁间隔物中，其用于改变高级复合栅极电介质的性质，例如，氮化的氧化物，NO和栅极侧壁电介质，使得氟的低K特性用于开发低寄生电容MOSFET。

65. 发明申请

US20070099391A1 Methods for forming semiconductor structures with buried isolation collars and semiconductor structures formed by these methods 失效
标题翻译：用这些方法形成的具有掩埋隔离环和半导体结构的半导体结构的方法
公开(公告)号：US20070099391A1
公开(公告)日：2007-05-03
申请号：US11262128
申请日：2005-10-28
申请人： Kangguo Cheng , Jack Mandelman
发明人： Kangguo Cheng , Jack Mandelman
IPC分类号： H01L21/76
CPC分类号： H01L27/1087 , H01L29/66181 , H01L29/945
摘要： A semiconductor structure including a trench formed in a substrate and a buried isolation collar that extends about sidewalls of the trench. The buried isolation collar is constituted by an insulator formed from a buried porous region of substrate material. The porous region is formed from a buried doped region defined using masking and ion implantation or by masking the trench sidewalls and using dopant diffusion. Advantageously, the porous region is transformed to an oxide insulator by an oxidation process. The semiconductor structure may be a storage capacitor of a memory cell further having a buried plate about the trench and a capacitor node inside the trench that is separated from the buried plate by a node dielectric formed on the trench sidewalls.
摘要翻译：包括形成在衬底中的沟槽和在沟槽的侧壁周围延伸的掩埋隔离环的半导体结构。埋置的隔离环由由基底材料的埋入多孔区形成的绝缘体构成。多孔区域由掩蔽和离子注入限定的掩埋掺杂区域或通过掩蔽沟槽侧壁并使用掺杂剂扩散形成。有利地，多孔区域通过氧化工艺转变成氧化物绝缘体。半导体结构可以是存储单元的存储电容器，其还具有围绕沟槽的掩埋板和沟槽内的电容器节点，其通过形成在沟槽侧壁上的节点电介质与掩埋板分离。

66. 发明申请

US20070087525A1 Method and apparatus for making coplanar isolated regions of different semiconductor materials on a substrate 有权
标题翻译：在衬底上制造不同半导体材料的共面隔离区域的方法和装置
公开(公告)号：US20070087525A1
公开(公告)日：2007-04-19
申请号：US11254044
申请日：2005-10-19
申请人： Howard Chen , Louis Hsu , Jack Mandelman
发明人： Howard Chen , Louis Hsu , Jack Mandelman
IPC分类号： H01L21/76 , H01L21/30
CPC分类号： H01L21/76254 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L27/1203 , H01L27/1207
摘要： A semiconductor processing method includes providing a substrate, forming a plurality of semiconductor layers in the substrate, each of the semiconductor layers being distinct and selected from different groups of semiconductor element types. The semiconductor layers include a first, second, and third semiconductor layers. The method further includes forming a plurality of lateral void gap isolation regions for isolating portions of each of the semiconductor layers from portions of the other semiconductor layers.
摘要翻译：半导体处理方法包括提供衬底，在衬底中形成多个半导体层，每个半导体层是不同的，并且选自不同的半导体元件组。半导体层包括第一，第二和第三半导体层。该方法还包括形成多个侧向空隙间隔隔离区域，用于将每个半导体层的部分与其它半导体层的部分隔离。

67. 发明申请

US20060286779A1 Patterned Silicon-on-Insulator layers and methods for forming the same 失效
标题翻译：图案化的绝缘体上层及其形成方法
公开(公告)号：US20060286779A1
公开(公告)日：2006-12-21
申请号：US11155029
申请日：2005-06-16
申请人： Roger Booth , Louis Hsu , Jack Mandelman , William Tonti
发明人： Roger Booth , Louis Hsu , Jack Mandelman , William Tonti
IPC分类号： H01L21/76 , H01L21/00
CPC分类号： H01L21/76243
摘要： In an aspect, a method is provided for forming a silicon-on-insulator (SOI) layer. The method includes the steps of (1) providing a silicon substrate; (2) selectively implanting the silicon substrate with oxygen using a low implant energy to form an ultra-thin patterned seed layer; and (3) employing the ultra-thin patterned seed layer to form a patterned SOI layer on the silicon substrate. Numerous other aspects are provided.
摘要翻译：在一方面，提供了一种用于形成绝缘体上硅（SOI）层的方法。该方法包括以下步骤：（1）提供硅衬底; （2）使用低注入能量用氧选择性地注入硅衬底以形成超薄图案种子层; 和（3）使用超薄图案种子层在硅衬底上形成图案化SOI层。提供了许多其他方面。

68. 发明申请

US20060192612A1 Capacitor reliability for multiple-voltage power supply systems 失效
公开(公告)号：US20060192612A1
公开(公告)日：2006-08-31
申请号：US11065840
申请日：2005-02-25
申请人： Louis Hsu , Rajiv Joshi , Jack Mandelman
发明人： Louis Hsu , Rajiv Joshi , Jack Mandelman
IPC分类号： H03K5/00
CPC分类号： H02M3/07
摘要： A capacitor circuit having improved reliability includes at least first and second capacitors, a first terminal of the first capacitor connecting to a first source providing a first voltage, a first terminal of the second capacitor connecting to a second source providing a second voltage, the first voltage being greater than the second voltage. The capacitor further includes a voltage comparator having a first input for receiving a voltage representative of the first voltage, a second input for receiving a third voltage provided by a third source, and an output for generating a control signal. The control signal is a function of a difference between the voltage representative of the first voltage and the third voltage. A switch is connected to second terminals of the first and second capacitors. The switch is selectively operable in one of at least a first mode and a second mode in response to the control signal, wherein in the first mode the switch is operative to connect the first and second capacitors together in parallel, and in the second mode the switch is operative to connect the first and second capacitors together in series. The first mode is indicative of the voltage representative of the first voltage being less than or about equal to the third voltage, and the second mode is indicative of the voltage representative of the first voltage being greater than the third voltage.

69. 发明授权

US06974743B2 Method of making encapsulated spacers in vertical pass gate DRAM and damascene logic gates 失效
标题翻译：在垂直传输门DRAM和镶嵌逻辑门中制造封装间隔物的方法
公开(公告)号：US06974743B2
公开(公告)日：2005-12-13
申请号：US10770264
申请日：2004-02-02
申请人： Ramac Divakaruni , Stephan Kudelka , Jack Mandelman
发明人： Ramac Divakaruni , Stephan Kudelka , Jack Mandelman
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8242 , H01L29/06 , H01L29/423 , H01L29/737 , H01L29/78 , H01L27/108
CPC分类号： H01L29/66537 , H01L21/28114 , H01L27/10864 , H01L27/10876 , H01L27/10891 , H01L29/0692 , H01L29/42376 , H01L29/665 , H01L29/66553 , H01L29/6656 , H01L29/6659 , H01L29/66621 , H01L29/7371 , H01L29/7834
摘要： Semiconductor devices having improved isolation are provided along with methods of fabricating such semiconductor devices. The improved isolation includes an encapsulated spacer formed within a gate region of a device.
摘要翻译：提供具有改进的隔离的半导体器件与制造这种半导体器件的方法一起提供。改进的隔离包括形成在器件的栅极区域内的封装间隔物。

70. 发明申请

US20050196932A1 Method of creating deep trench capacitor using A P+ metal electrode 有权
标题翻译：使用P +金属电极制造深沟槽电容器的方法
公开(公告)号：US20050196932A1
公开(公告)日：2005-09-08
申请号：US11124324
申请日：2005-05-06
申请人： Ramachandra Divakaruni , Jack Mandelman , Dae-Gyu Park
发明人： Ramachandra Divakaruni , Jack Mandelman , Dae-Gyu Park
IPC分类号： H01L21/20 , H01L21/8242 , H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L27/10864
摘要： The present invention comprises a method including the steps of providing a substrate; forming a trench in the substrate; forming a buried plate in the substrate about the trench; depositing a dielectric layer within the trench; and then depositing a P-type metal atop the dielectric layer, where the dielectric layer is positioned between the P-type metal and the buried plate. Another aspect of the present invention provides a trench capacitor where said trench capacitor comprises a trench formed in a substrate, a buried plate formed in the substrate about the trench; a node dielectric; and a P-type metal liner deposited within the trench, where the P-type metal liner is separated from the buried plate by the node dielectric. A P-type metal is defined as a metal having a work function close to the Si valence band, approximately equal to 5.1 eV.
摘要翻译：本发明包括一种方法，包括提供基底的步骤; 在衬底中形成沟槽; 在沟槽周围形成衬底; 在沟槽内沉积介电层; 然后在电介质层的顶部沉积P型金属，其中电介质层位于P型金属和掩埋板之间。本发明的另一方面提供一种沟槽电容器，其中所述沟槽电容器包括形成在衬底中的沟槽，在衬底周围形成的掩埋板围绕沟槽; 节点电介质; 以及沉积在沟槽内的P型金属衬垫，其中P型金属衬垫通过节点电介质与掩埋板分离。 P型金属被定义为具有接近于Si价带的功函数的金属，大约等于5.1eV。

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