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1. 发明申请

US20070018239A1 Sea-of-fins structure on a semiconductor substrate and method of fabrication 审中-公开
标题翻译：半导体衬底上的海鳍结构和制造方法
公开(公告)号：US20070018239A1
公开(公告)日：2007-01-25
申请号：US11185646
申请日：2005-07-20
申请人： Howard Chen , Louis Hsu , Jack Mandelman , Chun-Yung Sung
发明人： Howard Chen , Louis Hsu , Jack Mandelman , Chun-Yung Sung
IPC分类号： H01L29/76
CPC分类号： H01L21/823437 , H01L21/823412 , H01L21/823431 , H01L27/1211 , H01L29/66795 , H01L29/66803 , H01L29/785 , Y10S977/734 , Y10S977/742 , Y10S977/749 , Y10S977/815 , Y10S977/955
摘要： A semiconductor device and a method of fabricating a semiconductor device, wherein the method comprises forming, on a substrate, a plurality of planarized fin bodies to be used for customized fin field effect transistor (FinFET) device formation; forming a nitride spacer around each of the plurality of fin bodies; forming an isolation region in between each of the fin bodies; and coating the plurality of fin bodies, the nitride spacers, and the isolation regions with a protective film. The fabricated semiconductor device is adapted to be used in customized applications as a customized semiconductor device.
摘要翻译：一种半导体器件和半导体器件的制造方法，其中所述方法包括在衬底上形成多个用于定制鳍状场效应晶体管（FinFET）器件形成的平坦化翅片体; 在所述多个翅片体中的每一个周围形成氮化物间隔物; 在每个翅片体之间形成隔离区域; 并用保护膜涂覆多个翅片体，氮化物间隔物和隔离区域。制造的半导体器件适用于定制应用中作为定制的半导体器件。

2. 发明申请

US20070048975A1 Method and apparatus for making coplanar dielectrically-isolated regions of different semiconductor materials on a substrate 有权
标题翻译：用于在衬底上制造不同半导体材料的共面介电隔离区域的方法和装置
公开(公告)号：US20070048975A1
公开(公告)日：2007-03-01
申请号：US11218198
申请日：2005-09-01
申请人： Howard Chen , Louis Hsu , Jack Mandelman
发明人： Howard Chen , Louis Hsu , Jack Mandelman
IPC分类号： H01L21/20 , H01L21/36
CPC分类号： H01L21/76254 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L27/1203 , H01L27/1207
摘要： A semiconductor processing method includes providing a substrate, forming a plurality of semiconductor layers in the substrate, each of the semiconductor layers being distinct and selected from different groups of semiconductor element types, the semiconductor layers comprising first, second, and third semiconductor layers. The method further includes forming a nitride cap layer on the second semiconductor layer prior to forming the third semiconductor layer. Semiconductor structure formed by the above method is also described.
摘要翻译：半导体处理方法包括提供衬底，在衬底中形成多个半导体层，每个半导体层是不同的并且选自不同的半导体元件组，半导体层包括第一，第二和第三半导体层。该方法还包括在形成第三半导体层之前在第二半导体层上形成氮化物覆盖层。还描述了通过上述方法形成的半导体结构。

3. 发明申请

US20070087525A1 Method and apparatus for making coplanar isolated regions of different semiconductor materials on a substrate 有权
标题翻译：在衬底上制造不同半导体材料的共面隔离区域的方法和装置
公开(公告)号：US20070087525A1
公开(公告)日：2007-04-19
申请号：US11254044
申请日：2005-10-19
申请人： Howard Chen , Louis Hsu , Jack Mandelman
发明人： Howard Chen , Louis Hsu , Jack Mandelman
IPC分类号： H01L21/76 , H01L21/30
CPC分类号： H01L21/76254 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L27/1203 , H01L27/1207
摘要： A semiconductor processing method includes providing a substrate, forming a plurality of semiconductor layers in the substrate, each of the semiconductor layers being distinct and selected from different groups of semiconductor element types. The semiconductor layers include a first, second, and third semiconductor layers. The method further includes forming a plurality of lateral void gap isolation regions for isolating portions of each of the semiconductor layers from portions of the other semiconductor layers.
摘要翻译：半导体处理方法包括提供衬底，在衬底中形成多个半导体层，每个半导体层是不同的，并且选自不同的半导体元件组。半导体层包括第一，第二和第三半导体层。该方法还包括形成多个侧向空隙间隔隔离区域，用于将每个半导体层的部分与其它半导体层的部分隔离。

4. 发明授权

US07676775B2 Method to determine the root causes of failure patterns by using spatial correlation of tester data 失效
标题翻译：通过使用测试仪数据的空间相关性确定故障模式的根本原因的方法
公开(公告)号：US07676775B2
公开(公告)日：2010-03-09
申请号：US11754947
申请日：2007-05-29
申请人： Howard Chen , Katherine V. Hawkins , Fook-Luen Heng , Louis Hsu , Xu Ouyang
发明人： Howard Chen , Katherine V. Hawkins , Fook-Luen Heng , Louis Hsu , Xu Ouyang
IPC分类号： G06F17/50
CPC分类号： G01R31/2894 , G01R31/31718 , G01R31/318314 , G11C29/10 , G11C29/56 , G11C29/56008
摘要： A method for determining the root causes of fail patterns in integrated circuit chips is provide wherein a known integrated circuit chip layout is used to identify a plurality of potential defects and a plurality of potential fail patterns in the integrated circuit chip. Correlations between the potential defects and the potential fail patterns that result from those defects are identified. Based on this identification, the potential fail patterns are grouped by common potential defect. An actual integrated circuit chip that is manufactured in accordance with the test layout is tested for failure patterns. These failure patterns are then compared to the groupings of potential fail patterns. When a match is found, that is when a given group of fail patterns is found in the actual integrated circuit chip, then the potential defect associated with the potential fail patterns to which the actual fail patterns are matched is identified. This defect is the root cause of the failure pattern in the actual chip.
摘要翻译：提供了一种用于确定集成电路芯片中的故障模式的根本原因的方法，其中使用已知的集成电路芯片布局来识别集成电路芯片中的多个潜在缺陷和多个潜在故障模式。鉴定出潜在缺陷与由这些缺陷产生的潜在失效模式之间的相关性。基于此识别，潜在的故障模式由共同的潜在缺陷分组。测试根据测试布局制造的实际集成电路芯片的故障模式。然后将这些故障模式与潜在故障模式的分组进行比较。当发现匹配时，即在实际的集成电路芯片中发现给定的一组故障模式时，识别与实际故障模式匹配的潜在故障模式相关联的潜在缺陷。这个缺陷是实际芯片中故障模式的根本原因。

5. 发明申请

US20060110852A1 Methods to achieve precision alignment for wafer scale packages 失效
标题翻译：实现晶圆级封装精密对准的方法
公开(公告)号：US20060110852A1
公开(公告)日：2006-05-25
申请号：US10994574
申请日：2004-11-22
申请人： Howard Chen , Louis Hsu
发明人： Howard Chen , Louis Hsu
IPC分类号： H01L21/48
CPC分类号： H01L23/5389 , H01L21/52 , H01L24/83 , H01L2223/5448 , H01L2223/54486 , H01L2924/1461 , H01L2924/00
摘要： Methods for manufacturing an integrated wafer scale package that reduces a potential misalignment between a chip and a pocket of a carrier substrate. According to one aspect of the present invention, a method for manufacturing a semiconductor device includes a photoresist layer disposed on a carrier substrate, a chip placed onto a surface of the photoresist layer. The photoresist layer is patterned using the chip as a mask. The chip is removed from the photoresist layer after the patterning step. A pocket is formed in the carrier substrate, and the chip that was removed is placed into the pocket formed in the carrier substrate.
摘要翻译：用于制造集成晶片级封装的方法，其减小载体衬底的芯片和凹坑之间的潜在的未对准。根据本发明的一个方面，一种制造半导体器件的方法包括：设置在载体衬底上的光致抗蚀剂层，放置在光致抗蚀剂层的表面上的芯片。使用芯片作为掩模对光致抗蚀剂层进行图案化。在图案化步骤之后，将芯片从光致抗蚀剂层上除去。在载体基板上形成有袋状物，将被除去的芯片放置在形成于载体基板上的槽内。

6. 发明申请

US20050059238A1 Cooling system for a semiconductor device and method of fabricating same 有权
标题翻译：一种用于半导体器件的冷却系统及其制造方法
公开(公告)号：US20050059238A1
公开(公告)日：2005-03-17
申请号：US10661299
申请日：2003-09-12
申请人： Howard Chen , Louis Hsu , Joseph Shepard
发明人： Howard Chen , Louis Hsu , Joseph Shepard
IPC分类号： H01L21/44 , H01L21/48 , H01L23/367
CPC分类号： H01L23/473 , H01L21/4871 , H01L23/3677 , H01L25/0655 , H01L2224/05001 , H01L2224/05008 , H01L2224/05548 , H01L2224/16225 , H01L2924/00014 , H01L2924/01019 , H01L2924/01079 , H01L2924/10158 , H01L2924/15311 , H01L2224/05599 , H01L2224/05099
摘要： A cooling system for a semiconductor substrate incudes a plurality of trenches formed from a backside of the semiconductor substrate, and thermally conductive material deposited in the plurality of trenches. A method of forming cooling elements in a semiconductor substrate, includes coating a backside of the semiconductor substrate with a first mask layer, forming a plurality of trench patterns in the first mask layer, etching the semiconductor substrate to form a plurality of trenches along the plurality of trench patterns, and depositing thermally conductive material in the plurality of trenches. Trenches constructed from the backside of a wafer improve efficiency of heat transfer from a front-side to the backside of an integrated-circuit chip. The fabrication of trenches from the backside of the wafer allows for increases in the depth and number of trenches, and provides a means to attach passive and active cooling devices directly to the backside of a wafer.
摘要翻译：用于半导体衬底的冷却系统包括由半导体衬底的背面形成的多个沟槽和沉积在多个沟槽中的导热材料。一种在半导体衬底中形成冷却元件的方法，包括用第一掩模层涂覆半导体衬底的背面，在第一掩模层中形成多个沟槽图案，蚀刻半导体衬底以形成沿着多个的多个沟槽的沟槽图案，并且在多个沟槽中沉积导热材料。从晶片背面构成的沟槽提高了从集成电路芯片的正面到背面的传热效率。从晶片的背面制造沟槽允许沟槽的深度和数量的增加，并且提供了将被动和主动的冷却装置直接附接到晶片的背面的手段。

7. 发明申请

US20080170368A1 Apparatuses for Dissipating Heat from Semiconductor Devices 审中-公开
标题翻译：从半导体器件散热的装置
公开(公告)号：US20080170368A1
公开(公告)日：2008-07-17
申请号：US12032063
申请日：2008-02-15
申请人： Howard Chen , Hsichang Liu , Louis Hsu , Lawrence Mok
发明人： Howard Chen , Hsichang Liu , Louis Hsu , Lawrence Mok
IPC分类号： H05K7/20
CPC分类号： H01L23/427 , F28D15/0233 , F28D15/0275 , F28D15/04 , F28F2215/06 , H01L2224/16225
摘要： An apparatus for providing two-phase heat transfer for semiconductor devices includes a vapor chamber configured to carry a cooling liquid, the vapor chamber having a base section, and a plurality of three-dimensional (3D) shaped members. The plurality of 3D-shaped members have interior and exterior sidewalls, the 3D-shaped members being connected to the base section so that vapor carrying latent heat can reach the respective interior sidewalls and get transferred to the respective exterior sidewalls configured to be in contact with an external coolant. The vapor chamber is configured to be in contact with a semiconductor device in order to remove heat therefrom.
摘要翻译：用于为半导体器件提供两相热传递的装置包括构造成承载冷却液体的蒸气室，蒸气室具有基部，以及多个三维（3D）形状的部件。多个3D形构件具有内部和外部侧壁，3D形构件连接到基部，使得携带潜热的蒸汽可以到达相应的内侧壁并被转移到被配置为与外部冷却液。蒸气室被配置为与半导体器件接触以从其中除去热量。

8. 发明授权

US07369410B2 Apparatuses for dissipating heat from semiconductor devices 有权
标题翻译：用于从半导体器件散热的装置
公开(公告)号：US07369410B2
公开(公告)日：2008-05-06
申请号：US11416762
申请日：2006-05-03
申请人： Howard Chen , Hsichang Liu , Louis Hsu , Lawrence Mok
发明人： Howard Chen , Hsichang Liu , Louis Hsu , Lawrence Mok
IPC分类号： H05K7/20
CPC分类号： H01L23/427 , F28D15/0233 , F28D15/0275 , F28D15/04 , F28F2215/06 , H01L2224/16225
摘要： An apparatus for providing two-phase heat transfer for semiconductor devices includes a vapor chamber configured to carry a cooling liquid, the vapor chamber having base section, and a plurality of three-dimensional (3D) shaped members. The plurality of 3D-shaped members have interior and exterior sidewalls, the 3D-shaped members being connected to the base section so that vapor carrying latent heat can reach the respective interior sidewalls and get transferred to the respective exterior sidewalls configured to be in contact with an external coolant. The vapor chamber is configured to be in contact with a semiconductor device in order to remove heat therefrom.
摘要翻译：一种用于半导体器件的两相热传递装置，包括一个蒸气室，被配置为承载冷却液体，该蒸气室具有基部，以及多个三维（3D）形状的部件。多个3D形构件具有内部和外部侧壁，3D形构件连接到基部，使得携带潜热的蒸汽可以到达相应的内侧壁并被转移到被配置为与外部冷却液。蒸气室被配置为与半导体器件接触以从其中除去热量。

9. 发明申请

US20070258213A1 Apparatuses for dissipating heat from semiconductor devices 有权
标题翻译：用于从半导体器件散热的装置
公开(公告)号：US20070258213A1
公开(公告)日：2007-11-08
申请号：US11416762
申请日：2006-05-03
申请人： Howard Chen , Hsichang Liu , Louis Hsu , Lawrence Mok
发明人： Howard Chen , Hsichang Liu , Louis Hsu , Lawrence Mok
IPC分类号： H05K7/20
CPC分类号： H01L23/427 , F28D15/0233 , F28D15/0275 , F28D15/04 , F28F2215/06 , H01L2224/16225
摘要： An apparatus for providing two-phase heat transfer for semiconductor devices includes a vapor chamber configured to carry a cooling liquid, the vapor chamber having base section, and a plurality of three-dimensional (3D) shaped members. The plurality of 3D-shaped members have interior and exterior sidewalls, the 3D-shaped members being connected to the base section so that vapor carrying latent heat can reach the respective interior sidewalls and get transferred to the respective exterior sidewalls configured to be in contact with an external coolant. The vapor chamber is configured to be in contact with a semiconductor device in order to remove heat therefrom.
摘要翻译：一种用于半导体器件的两相热传递装置，包括一个蒸气室，被配置为承载冷却液体，该蒸气室具有基部，以及多个三维（3D）形状的部件。多个3D形构件具有内部和外部侧壁，3D形构件连接到基部，使得携带潜热的蒸汽可以到达相应的内侧壁并被转移到被配置为与外部冷却液。蒸气室被配置为与半导体器件接触以从其中除去热量。

10. 发明申请

US20060110851A1 Methods for forming co-planar wafer-scale chip packages 有权
标题翻译：用于形成共面晶片级芯片封装的方法
公开(公告)号：US20060110851A1
公开(公告)日：2006-05-25
申请号：US10994494
申请日：2004-11-20
申请人： Lloyd Burrell , Howard Chen , Louis Hsu , Wolfgang Sauter
发明人： Lloyd Burrell , Howard Chen , Louis Hsu , Wolfgang Sauter
IPC分类号： H01L21/48 , H01L21/50
CPC分类号： H01L23/5389 , H01L21/52 , H01L23/147 , H01L23/5385 , H01L2221/68322 , H01L2221/68345 , H01L2924/0002 , H01L2924/1433 , H01L2924/00
摘要： Economical methods for forming a co-planar multi-chip wafer-level packages are proposed. Partial wafer bonding and partial wafer dicing techniques are used to create chips as well as pockets. The finished chips are then mounted in the corresponding pockets of a carrier substrate, and global interconnects among the chips are formed on the top planar surface of the finished chips. The proposed methods facilitate the integration of chips fabricated with different process steps and materials. There is no need to use a planarization process such as chemical-mechanical polish to planarize the top surfaces of the chips. Since the chips are precisely aligned to each other and all the chips are mounted facing up, the module is ready for global wiring, which eliminates the need to flip the chips from an upside-down position.
摘要翻译：提出了用于形成共面多芯片晶片级封装的经济方法。部分晶片接合和部分晶片切割技术用于制造芯片以及口袋。然后将完成的芯片安装在载体基板的相应凹穴中，并且芯片之间的全局互连形成在成品芯片的顶部平坦表面上。所提出的方法促进了用不同工艺步骤和材料制造的芯片的集成。不需要使用诸如化学机械抛光剂的平面化处理来平坦化芯片的顶表面。由于芯片精确地对准并且所有芯片都朝上安装，所以模块准备好进行全局布线，从而不需要将芯片从倒置的位置翻转。

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