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1. 发明授权

US06974743B2 Method of making encapsulated spacers in vertical pass gate DRAM and damascene logic gates 失效
标题翻译：在垂直传输门DRAM和镶嵌逻辑门中制造封装间隔物的方法
公开(公告)号：US06974743B2
公开(公告)日：2005-12-13
申请号：US10770264
申请日：2004-02-02
申请人： Ramac Divakaruni , Stephan Kudelka , Jack Mandelman
发明人： Ramac Divakaruni , Stephan Kudelka , Jack Mandelman
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8242 , H01L29/06 , H01L29/423 , H01L29/737 , H01L29/78 , H01L27/108
CPC分类号： H01L29/66537 , H01L21/28114 , H01L27/10864 , H01L27/10876 , H01L27/10891 , H01L29/0692 , H01L29/42376 , H01L29/665 , H01L29/66553 , H01L29/6656 , H01L29/6659 , H01L29/66621 , H01L29/7371 , H01L29/7834
摘要： Semiconductor devices having improved isolation are provided along with methods of fabricating such semiconductor devices. The improved isolation includes an encapsulated spacer formed within a gate region of a device.
摘要翻译：提供具有改进的隔离的半导体器件与制造这种半导体器件的方法一起提供。改进的隔离包括形成在器件的栅极区域内的封装间隔物。

2. 发明申请

US20050167741A1 ENCAPSULATED SPACERS IN VERTICAL PASS GATE DRAM AND DAMASCENE LOGIC GATES 失效
标题翻译：垂直通道门和大气门逻辑门的封装间隔
公开(公告)号：US20050167741A1
公开(公告)日：2005-08-04
申请号：US10770264
申请日：2004-02-02
申请人： Ramachandra Divakaruni , Stephan Kudelka , Jack Mandelman
发明人： Ramachandra Divakaruni , Stephan Kudelka , Jack Mandelman
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8242 , H01L29/06 , H01L29/423 , H01L29/737 , H01L29/78 , H01L29/76
CPC分类号： H01L29/66537 , H01L21/28114 , H01L27/10864 , H01L27/10876 , H01L27/10891 , H01L29/0692 , H01L29/42376 , H01L29/665 , H01L29/66553 , H01L29/6656 , H01L29/6659 , H01L29/66621 , H01L29/7371 , H01L29/7834
摘要： Semiconductor devices having improved isolation are provided along with methods of fabricating such semiconductor devices. The improved isolation includes an encapsulated spacer formed within a gate region of a device.
摘要翻译：提供具有改进的隔离的半导体器件与制造这种半导体器件的方法一起提供。改进的隔离包括形成在器件的栅极区域内的封装间隔物。

3. 发明授权

US07157328B2 Selective etching to increase trench surface area 有权
标题翻译：选择性蚀刻以增加沟槽表面积
公开(公告)号：US07157328B2
公开(公告)日：2007-01-02
申请号：US11047312
申请日：2005-01-31
申请人： Helmut Horst Tews , Stephan Kudelka , Kenneth T. Settlemyer
发明人： Helmut Horst Tews , Stephan Kudelka , Kenneth T. Settlemyer
IPC分类号： H01L21/8242
CPC分类号： H01L21/30604 , H01L29/66181
摘要： The surface area of the walls of a trench formed in a substrate is increased. A barrier layer is formed on the walls of the trench such that the barrier layer is thinner near the corners of the trench and is thicker between the corners of the trench. A dopant is introduced into the substrate through the barrier layer to form higher doped regions in the substrate near the corners of the trench and lesser doped regions between the corners of the trench. The barrier layer is removed, and the walls of the trench are etched in a manner that etches the lesser doped regions of the substrate at a higher rate than the higher doped regions of the substrate to widen and lengthen the trench and to form rounded corners at the intersections of the walls of the trench.
摘要翻译：在衬底中形成的沟槽的壁的表面积增加。阻挡层形成在沟槽的壁上，使得阻挡层在沟槽的角部附近更薄，并且在沟槽的角部之间更厚。通过势垒层将掺杂剂引入到衬底中，以在衬底附近的沟槽的角部附近形成更高的掺杂区域，并且在沟槽的角部之间形成较小的掺杂区域。去除阻挡层，并且以如下方式蚀刻沟槽的壁，该方式是以比衬底的较高掺杂区域更高的速率蚀刻衬底的较小掺杂区域，以加宽和延长沟槽并且形成圆角沟渠墙壁的交叉点。

4. 发明申请

US20060172486A1 Selective etching to increase trench surface area 有权
标题翻译：选择性蚀刻以增加沟槽表面积
公开(公告)号：US20060172486A1
公开(公告)日：2006-08-03
申请号：US11047312
申请日：2005-01-31
申请人： Helmut Tews , Stephan Kudelka , Kenneth Settlemyer
发明人： Helmut Tews , Stephan Kudelka , Kenneth Settlemyer
IPC分类号： H01L21/8242 , H01L29/94
CPC分类号： H01L21/30604 , H01L29/66181
摘要： The surface area of the walls of a trench formed in a substrate is increased. A barrier layer is formed on the walls of the trench such that the barrier layer is thinner near the corners of the trench and is thicker between the corners of the trench. A dopant is introduced into the substrate through the barrier layer to form higher doped regions in the substrate near the corners of the trench and lesser doped regions between the corners of the trench. The barrier layer is removed, and the walls of the trench are etched in a manner that etches the lesser doped regions of the substrate at a higher rate than the higher doped regions of the substrate to widen and lengthen the trench and to form rounded corners at the intersections of the walls of the trench.
摘要翻译：在衬底中形成的沟槽的壁的表面积增加。阻挡层形成在沟槽的壁上，使得阻挡层在沟槽的角部附近更薄，并且在沟槽的角部之间更厚。通过势垒层将掺杂剂引入到衬底中，以在衬底附近的沟槽的角部附近形成更高的掺杂区域，并且在沟槽的角部之间形成较小的掺杂区域。去除阻挡层，并且以如下方式蚀刻沟槽的壁，该方式是以比衬底的较高掺杂区域更高的速率蚀刻衬底的较小掺杂区域，以加宽和延长沟槽并且形成圆角沟渠墙壁的交叉点。

5. 发明授权

US06916721B2 Method for fabricating a trench capacitor with an insulation collar 失效
标题翻译：用于制造具有绝缘套圈的沟槽电容器的方法
公开(公告)号：US06916721B2
公开(公告)日：2005-07-12
申请号：US10722360
申请日：2003-11-26
申请人： Lars Heineck , Stephan Kudelka , Jörn Lützen , Hans-Peter Moll , Martin Popp , Till Schlösser , Johann Steinmetz
发明人： Lars Heineck , Stephan Kudelka , Jörn Lützen , Hans-Peter Moll , Martin Popp , Till Schlösser , Johann Steinmetz
IPC分类号： H01L21/20 , H01L21/334 , H01L21/425 , H01L21/8242 , H01L27/108 , H01L29/94
CPC分类号： H01L27/10867 , H01L27/10829 , H01L29/66181 , H01L29/945
摘要： A method for fabricating a trench capacitor with an insulation collar in a substrate, which is electrically connected to the substrate on one side via a buried contact, using a hard mask with a corresponding mask opening.
摘要翻译：一种在衬底中制造具有绝缘套环的沟槽电容器的方法，其使用具有相应掩模开口的硬掩模经由掩埋触点将其一侧的衬底电连接。

6. 发明申请

US20050079679A1 Trench capacitor and method for fabricating a trench capacitor 审中-公开
标题翻译：沟槽电容器和制造沟槽电容器的方法
公开(公告)号：US20050079679A1
公开(公告)日：2005-04-14
申请号：US10920808
申请日：2004-08-18
申请人： Harald Seidl , Annette Sanger , Stephan Kudelka , Martin Gutsche
发明人： Harald Seidl , Annette Sanger , Stephan Kudelka , Martin Gutsche
IPC分类号： H01L21/02 , H01L21/334 , H01L21/8242 , H01L27/108 , H01L29/94
CPC分类号： H01L29/66181 , H01L29/945
摘要： A method for fabricating a trench capacitor in a semiconductor substrate with a low-impedance inner electrode for use in memory cells of memory devices. A separating layer is provided on a dielectric layer in the active region of the trench capacitor. Afterward, a low-impedance inner electrode made of metal or a metal compound is introduced both in the active region and in the collar region lined with an insulation layer.
摘要翻译：一种用于在具有用于存储器件的存储器单元的低阻抗内部电极的半导体衬底中制造沟槽电容器的方法。隔离层设置在沟槽电容器的有源区中的电介质层上。之后，将由金属或金属化合物制成的低阻抗内部电极引入有源区域和衬有隔离层的环形区域中。

7. 发明申请

US20050026384A1 Method for fabricating trench capacitor with insulation collar electrically connected to substrate through buried contact, in particular, for a semiconductor memory cell 失效
标题翻译：用于制造具有绝缘环的沟槽电容器的方法，所述绝缘套环通过埋入触点电连接到衬底，特别是用于半导体存储器单元
公开(公告)号：US20050026384A1
公开(公告)日：2005-02-03
申请号：US10901406
申请日：2004-07-27
申请人： Stephan Kudelka , Martin Popp , Harald Seidl , Annette Sanger
发明人： Stephan Kudelka , Martin Popp , Harald Seidl , Annette Sanger
IPC分类号： H01L21/20 , H01L21/334 , H01L21/8242 , H01L27/108
CPC分类号： H01L27/1087 , H01L27/10829 , H01L29/66181
摘要： Fabricating a trench capacitor with an insulation collar in a substrate, which is electrically connected thereto on one side through a buried contact, in particular, for a semiconductor memory cell with a planar selection transistor in the substrate and connected through the buried contact, includes providing a trench using an opening in a hard mask, providing a capacitor dielectric in lower and central trench regions, the collar in central and upper trench regions, and a conductive filling at least as far as the insulation collar topside, completely filling the trench with a filling material, carrying out STI trench fabrication process, removing the filling material and sinking the filling to below the collar topside, forming an insulation region on one side above the collar; uncovering a connection region on a different side above the collar, and forming the buried contact by depositing and etching back a metallic filling.
摘要翻译：在衬底中制造具有绝缘套环的沟槽电容器，其在一侧通过埋入触点电连接，特别地，用于具有衬底中的平面选择晶体管并通过埋入触点连接的半导体存储器单元包括提供在硬掩模中使用开口的沟槽，在下部和中部沟槽区域中提供电容器电介质，在中央和上部沟槽区域中的套环，以及至少与绝缘套环顶部一样的导电填充物，完全用一个填充材料，执行STI沟槽制造工艺，去除填充材料并将填充物下沉到轴环顶部以下，在轴环上方的一侧上形成绝缘区域; 露出套环上方不同侧的连接区域，并通过沉积和蚀刻金属填充物来形成掩埋触点。

8. 发明授权

US06677197B2 High aspect ratio PBL SiN barrier formation 有权
标题翻译：高纵横比PBL SiN阻挡层形成
公开(公告)号：US06677197B2
公开(公告)日：2004-01-13
申请号：US10032040
申请日：2001-12-31
申请人： Stephan Kudelka , Helmut Horst Tews
发明人： Stephan Kudelka , Helmut Horst Tews
IPC分类号： H01L218242
CPC分类号： H01L27/1087 , H01L29/66181
摘要： In a process for preparing a DT DRAM for sub 100 nm groundrules that normally require the formation of a collar after the bottle formation, the improvement of providing a collar first scheme by forming a high aspect ration PBL SiN barrier, comprising: a) providing a semiconductor structure after SiN node deposition and DT polysilicon fill; b) depositing a poly buffered LOCOS (PBL) Si liner; c) subjecting the PBL liner to oxidation to form a pad oxide and depositing a SiN barrier layer; d) depositing a silicon mask liner; e) subjecting the DT to high directional ion implantation (I/I) using a p-dopant; f) employing a selective wet etch of unimplanted Si with an etch stop on SiN; g) subjecting the product of step f) to a SiN wet etch with an etch stop on the pad oxide; h) affecting a Si liner etch with a stop on the pad oxide; i) oxidizing the PBL Si liner and affecting a barrier SiN strip; j) providing a DT polysilicon fill and performing a poly chemical mechanical polishing.
摘要翻译：在制备通常需要在瓶形成后形成套环的亚100nm研磨剂制备DT DRAM的方法中，通过形成高面积比PBL SiN阻挡层来改进提供轴环第一方案，该方法包括：a）在SiN结点沉积和DT多晶硅填充之后的半导体结构; b）沉积多层缓冲LOCOS（PBL）Si衬垫; c）使PBL衬里氧化形成衬垫氧化物并沉积SiN阻挡层; d）沉积硅掩模衬垫; e）使用p-掺杂剂对DT进行高定向离子注入（I / I）; f）使用SiN上的蚀刻停止对未被注入的Si的选择性湿蚀刻; g）使步骤f）的产物在衬垫氧化物上具有蚀刻停止层的SiN湿蚀刻; h）影响衬垫氧化物上的停止的Si衬层蚀刻; i）氧化PBL Si衬垫并影响势垒SiN条; j）提供DT多晶硅填充物进行多化学机械抛光。

9. 发明授权

US06599798B2 Method of preparing buried LOCOS collar in trench DRAMS 失效
标题翻译：在沟槽DRAMS中制备掩埋LOCOS环的方法
公开(公告)号：US06599798B2
公开(公告)日：2003-07-29
申请号：US09910771
申请日：2001-07-24
申请人： Helmut Tews , Stephan Kudelka , Uwe Schroeder , Rolf Weis
发明人： Helmut Tews , Stephan Kudelka , Uwe Schroeder , Rolf Weis
IPC分类号： H01L218242
CPC分类号： H01L27/1087 , H01L21/76205 , H01L21/76235 , H01L27/10867 , H01L29/945
摘要： The vertical DRAM capacitor with a buried LOCOS collar characterized by: a self-aligned bottle and gas phase doping; no consumption of silicon at the depth of the buried strap; no reduction of trench diameter; and a nitride layer to protect trench sidewalls during gas phase doping.
摘要翻译：垂直DRAM电容器具有埋置的LOCOS环，其特征在于：自对准瓶和气相掺杂; 掩埋带深度不消耗硅; 没有减小沟槽直径; 以及在气相掺杂期间保护沟槽侧壁的氮化物层。

10. 发明授权

US06498061B2 Negative ion implant mask formation for self-aligned, sublithographic resolution patterning for single-sided vertical device formation 失效
标题翻译：用于单面垂直器件形成的自对准，亚光刻分辨率图案的负离子注入掩模形成
公开(公告)号：US06498061B2
公开(公告)日：2002-12-24
申请号：US09730674
申请日：2000-12-06
申请人： Rama Divakaruni , Stephan Kudelka , Helmut Tews , Irene McStay , Kil-Ho Lee , Uwe Schroeder
发明人： Rama Divakaruni , Stephan Kudelka , Helmut Tews , Irene McStay , Kil-Ho Lee , Uwe Schroeder
IPC分类号： H01L218242
CPC分类号： H01L27/10867
摘要： A process for fabricating a single-sided semiconductor deep trench structure filled with polysilicon trench fill material includes the following steps. Form a thin film, silicon nitride, barrier layer over the trench fill material. Deposit a thin film of an amorphous silicon masking layer over the barrier layer. Perform an angled implant into portions of the amorphous silicon masking layer which are not in the shadow of the deep trench. Strip the undoped portions of the amorphous silicon masking layer from the deep trench. Then strip the newly exposed portions of barrier layer exposing a part of the trench fill polysilicon surface and leaving the doped, remainder of the amorphous silicon masking layer exposed. Counterdope the exposed part of the trench fill material. Oxidize exposed portions of the polysilicon trench fill material, and then strip the remainder of the masking layer.
摘要翻译：用于制造填充有多晶硅沟槽填充材料的单面半导体深沟槽结构的工艺包括以下步骤。在沟槽填充材料上形成薄膜，氮化硅，阻挡层。在阻挡层上沉积非晶硅掩模层的薄膜。对非深度沟槽阴影的非晶硅掩模层的部分进行成角度的注入。从深沟槽剥离非晶硅掩模层的未掺杂部分。然后剥离暴露部分沟槽填充多晶硅表面的势垒层的新暴露部分，并且使非晶硅掩模层的掺杂剩余部分露出。反映出暴露部分的沟槽填充材料。氧化多晶硅沟槽填充材料的暴露部分，然后剥离掩模层的其余部分。

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