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1. 发明申请

US20070189076A1 Memory elements and methods of using the same 失效
标题翻译：内存元素和使用方法
公开(公告)号：US20070189076A1
公开(公告)日：2007-08-16
申请号：US11353493
申请日：2006-02-14
申请人： Wagdi Abadeer , Anthony Bonaccio , Jack Mandelman , William Tonti , Sebastian Ventrone
发明人： Wagdi Abadeer , Anthony Bonaccio , Jack Mandelman , William Tonti , Sebastian Ventrone
IPC分类号： G11C16/04
CPC分类号： G11C16/0466
摘要： In a first aspect, a first apparatus is provided. The first apparatus is a memory element that includes (1) one or more MOSFETs each including a dielectric material having a dielectric constant of about 3.9 to about 25; and (2) control logic coupled to at least one of the one or more MOSFETs. The control logic is adapted to (a) cause the memory element to operate in a first mode to store data; and (b) cause the memory element to operate in a second mode to change a threshold voltage of at least one of the one or more MOSFETs from an original threshold voltage to a changed threshold voltage such that the changed threshold voltage affects data stored by the memory element when operated in the first mode. Numerous other aspects are provided.
摘要翻译：在第一方面中，提供了一种第一装置。第一装置是存储元件，其包括（1）一个或多个MOSFET，每个MOSFET包括具有约3.9至约25的介电常数的电介质材料; 和（2）耦合到所述一个或多个MOSFET中的至少一个的控制逻辑。控制逻辑适于（a）使存储元件以第一模式操作以存储数据; 和（b）使存储元件在第二模式下操作以将一个或多个MOSFET中的至少一个的阈值电压从原始阈值电压改变到改变的阈值电压，使得改变的阈值电压影响由存储元件在第一模式下操作。提供了许多其他方面。

2. 发明申请

US20070188249A1 Programmable capacitors and methods of using the same 有权
标题翻译：可编程电容器及其使用方法
公开(公告)号：US20070188249A1
公开(公告)日：2007-08-16
申请号：US11353516
申请日：2006-02-14
申请人： Wagdi Abadeer , Anthony Bonaccio , Jack Mandelman , William Tonti , Sebastian Ventrone
发明人： Wagdi Abadeer , Anthony Bonaccio , Jack Mandelman , William Tonti , Sebastian Ventrone
IPC分类号： H03B5/12
CPC分类号： H03L7/099 , H03B5/1212 , H03B5/1228 , H03B5/124 , H03L7/095 , H03L7/10 , H03L7/18 , H03L2207/06
摘要： In a first aspect, a first method of adjusting capacitance of a semiconductor device is provided. The first method includes the steps of (1) providing a transistor including a dielectric material having a dielectric constant of about 3.9 to about 25, wherein the transistor is adapted to operate in a first mode to provide a capacitance and further adapted to operate in a second mode to change a threshold voltage of the transistor from an original threshold voltage to a changed threshold voltage such that the changed threshold voltage affects a capacitance provided by the transistor when operated in the first mode; and (2) employing the transistor in a circuit. Numerous other aspects are provided.
摘要翻译：在第一方面，提供了一种调整半导体器件的电容的方法。第一种方法包括以下步骤：（1）提供包括具有约3.9至约25的介电常数的介电材料的晶体管，其中该晶体管适于在第一模式下工作以提供电容，并进一步适于在将晶体管的阈值电压从初始阈值电压改变到改变的阈值电压，使得当在第一模式中操作时，改变的阈值电压影响由晶体管提供的电容; 和（2）在电路中采用晶体管。提供了许多其他方面。

3. 发明申请

US20070173029A1 Method for fabricating high performance metal-insulator-metal capacitor (MIMCAP) 审中-公开
标题翻译：制造高性能金属绝缘体金属电容器（MIMCAP）的方法
公开(公告)号：US20070173029A1
公开(公告)日：2007-07-26
申请号：US11340340
申请日：2006-01-26
申请人： Wagdi Abadeer , Jack Mandelman , Carl Radens , William Tonti
发明人： Wagdi Abadeer , Jack Mandelman , Carl Radens , William Tonti
IPC分类号： H01L21/20
CPC分类号： H01L28/60
摘要： A method of fabricating a high performance metal-insulator-metal capacitor (MIMCAP) includes providing a first inter-level dielectric (ILD) layer over an isolation region; forming a MIMCAP pattern in the first ILD layer over the isolation region; depositing a conformal conductive liner over the MIMCAP pattern and the first ILD layer; depositing an insulator over the conformal conductive liner; forming a contact pattern through the conformal conductive liner, the insulator and the first inter-level dielectric (ILD) layer; depositing a second conformal conductive liner over the MIMCAP pattern, the contact pattern and the first ILD layer; and depositing a conductive stud over the second conformal conductive liner in the MIMCAP pattern and the contact pattern. The method is applicable to both a conventional bulk semiconductor substrate and a silicon-on-insulator (SOI) substrate.
摘要翻译：一种制造高性能金属 - 绝缘体 - 金属电容器（MIMCAP）的方法包括在隔离区域上提供第一级间电介质层（ILD）层; 在隔离区域上的第一ILD层中形成MIMCAP图案; 在MIMCAP图案和第一ILD层上沉积共形导电衬垫; 在保形导电衬垫上沉积绝缘体; 通过所述共形导电衬垫，所述绝缘体和所述第一层间电介质层（ILD）层形成接触图案; 在MIMCAP图案，接触图案和第一ILD层上沉积第二共形导电衬垫; 以及在MIMCAP图案和接触图案中的第二共形导电衬垫上沉积导电柱。该方法适用于常规体半导体衬底和绝缘体上硅（SOI）衬底。

4. 发明申请

US20060259840A1 SELF-TEST CIRCUITRY TO DETERMINE MINIMUM OPERATING VOLTAGE 审中-公开
标题翻译：自检电路确定最小工作电压
公开(公告)号：US20060259840A1
公开(公告)日：2006-11-16
申请号：US10908452
申请日：2005-05-12
申请人： Wagdi Abadeer , George Braceras , Anthony Bonaccio , Kevin Gorman
发明人： Wagdi Abadeer , George Braceras , Anthony Bonaccio , Kevin Gorman
IPC分类号： G01R31/28
CPC分类号： G01R31/3004
摘要： A solution for determining minimum operating voltages due to performance/power requirements would be valid for a wide range of actual uses. The solution includes a test flow methodology for dynamically reducing power consumption under applied conditions while maintaining application performance via a BIST circuit. There is additionally provided a test flow method for dynamically reducing power consumption to the lowest possible stand-by/very low power level under applied conditions that will still be sufficient to maintain data/state information. One possible application would be for controlling the voltage supply to a group of particular circuits on an ASIC (Application Specific Integrated Circuit). These circuits are grouped together in a voltage island where they would receive a voltage supply that can be different from the voltage supply other circuits on the same chip are receiving. The same solution could be applied to a portion of a microprocessor (the cache logic control, for example).
摘要翻译：用于确定由于性能/功率要求而导致的最小工作电压的解决方案对于广泛的实际应用是有效的。该解决方案包括测试流程方法，用于在应用条件下动态降低功耗，同时通过BIST电路保持应用性能。另外提供了一种测试流程方法，用于在仍然足以维护数据/状态信息的应用条件下将功耗动态地降低到最低可能待机/极低功率水平。一种可能的应用是用于控制对ASIC（专用集成电路）上的一组特定电路的电压供应。这些电路分组在一个电压岛中，在那里它们将接收可以与同一芯片正在接收的其它电路的电压供给不同的电压源。相同的解决方案可以应用于微处理器的一部分（例如，高速缓存逻辑控制）。

5. 发明申请

US20060091951A1 INTEGRATED CIRCUIT AMPLIFIER DEVICE AND METHOD USING FET TUNNELING GATE CURRENT 失效
标题翻译：集成电路放大器装置及使用FET隧道栅极电流的方法
公开(公告)号：US20060091951A1
公开(公告)日：2006-05-04
申请号：US10904238
申请日：2004-10-29
申请人： Wagdi Abadeer , Anthony Bonaccio , Kiran Chatty , John Fifield
发明人： Wagdi Abadeer , Anthony Bonaccio , Kiran Chatty , John Fifield
IPC分类号： H03F3/45 , H03F3/16
CPC分类号： H03F3/16 , H03F3/45179 , H03F3/505 , H03F2203/45468
摘要： An integrated circuit amplifier includes, in an exemplary embodiment, a first field effect transistor (FET) device configured as a source follower and a second FET device configured as a tunneling gate FET, the tunneling gate FET coupled to the source follower. The tunneling gate FET is further configured so as to set a transconductance of the amplifier and the source follower is configured so as to set an output conductance of the amplifier.
摘要翻译：在示例性实施例中，集成电路放大器包括被配置为源极跟随器的第一场效应晶体管（FET）器件和被配置为隧道栅极FET的第二FET器件，所述隧道栅极FET耦合到源极跟随器。隧道栅极FET进一步配置为设置放大器的跨导，并且配置源极跟随器以便设置放大器的输出电导。

6. 发明申请

US20080059930A1 Mesa Optical Sensors and Methods of Manufacturing the Same 审中-公开
标题翻译： Mesa光学传感器及其制造方法
公开(公告)号：US20080059930A1
公开(公告)日：2008-03-06
申请号：US11926577
申请日：2007-10-29
申请人： Wagdi Abadeer , Jack Mandelman
发明人： Wagdi Abadeer , Jack Mandelman
IPC分类号： G06F9/45
CPC分类号： H01L31/103 , H01L27/14643 , H01L31/035281 , H01L31/03529 , Y02E10/50
摘要： In a first aspect, a first method of determining radiation intensity is provided. The first method includes the steps of (1) providing a semiconductor device having (a) a silicon mesa; and (b) photo-gate conductor material along at least three sidewalls of the silicon mesa; (2) forming a depletion region in the silicon mesa; and (3) in response to radiation impacting the semiconductor device, creating a signal in the semiconductor device, wherein the signal has a level related to an intensity of the radiation. In another aspect, a design structure embodied in a machine readable medium for designing manufacturing, or testing a design is provided. Numerous other aspects are provided.
摘要翻译：在第一方面，提供了确定辐射强度的第一种方法。第一种方法包括以下步骤：（1）提供具有（a）硅台面的半导体器件; 和（b）沿着硅台面的至少三个侧壁的光栅导体材料; （2）在硅台面形成耗尽区; 和（3）响应于影响半导体器件的辐射，在半导体器件中产生信号，其中信号具有与辐射强度相关的电平。在另一方面，提供了体现在用于设计制造的机器可读介质或测试设计中的设计结构。提供了许多其他方面。

7. 发明申请

US20070252088A1 MONITORING IONIZING RADIATION IN SILICON-ON INSULATOR INTEGRATED CIRCUITS 有权
标题翻译：监测硅绝缘子集成电路中的离子化辐射
公开(公告)号：US20070252088A1
公开(公告)日：2007-11-01
申请号：US11380736
申请日：2006-04-28
申请人： Wagdi Abadeer , Ethan Cannon , Dennis Cox , William Tonti
发明人： Wagdi Abadeer , Ethan Cannon , Dennis Cox , William Tonti
IPC分类号： G01T1/02
CPC分类号： G01T1/244
摘要： A method, device and system for monitoring ionizing radiation. The method including: collecting an ionizing radiation induced charge collected by the depletion region of a diode formed in a silicon layer below an oxide layer buried below a surface of a silicon substrate; and coupling a cathode of the diode to a precharged node of a clocked logic circuit such that the ionizing radiation induced charge collected by a depletion region of the diode will discharge the precharged node and change an output state of the clocked logic circuit.
摘要翻译：一种用于监测电离辐射的方法，装置和系统。该方法包括：收集由埋在硅衬底表面下方的氧化物层下面的硅层中形成的二极管的耗尽区收集的电离辐射感应电荷; 以及将二极管的阴极耦合到时钟逻辑电路的预充电节点，使得由二极管的耗尽区收集的电离辐射感应电荷将放电预充电节点并改变时钟逻辑电路的输出状态。

8. 发明申请

US20060249799A1 Concurrent fin-fet and thick body device fabrication 有权
公开(公告)号：US20060249799A1
公开(公告)日：2006-11-09
申请号：US11481120
申请日：2006-07-05
申请人： Wagdi Abadeer , Jeffrey Brown , David Fried , Robert Gauther , Edward Nowak , Jed Rankio , William Tonti
发明人： Wagdi Abadeer , Jeffrey Brown , David Fried , Robert Gauther , Edward Nowak , Jed Rankio , William Tonti
IPC分类号： H01L29/76
CPC分类号： H01L29/786 , H01L21/845 , H01L27/1211 , H01L29/4908 , H01L29/78615
摘要： An integrated circuit chip and a semiconductor structure. The integrated circuit chip includes: a thick-body device containing a semiconductor mesa and a doped body contact; and a field effect transistor on a first sidewall of a semiconductor mesa, wherein the doped body contact is on a second sidewall of the semiconductor mesa, and wherein the semiconductor mesa is disposed between the field effect transistor and the doped body contact. The semiconductor structure includes: a buried oxide layer on a semiconductor wafer; a thin fin structure on the buried oxide layer, wherein the thin fin structure includes a first hard mask on a semiconductor fin, wherein the semiconductor fin is disposed between the first hard mask and a surface of the buried oxide layer; and a thick mesa structure on the buried oxide layer, and wherein the thick mesa structure includes a semiconductor mesa.

9. 发明申请

US20050133884A1 Electronically programmable antifuse and circuits made therewith 有权
标题翻译：电子可编程反熔丝和由其制成的电路
公开(公告)号：US20050133884A1
公开(公告)日：2005-06-23
申请号：US11051703
申请日：2005-02-04
申请人： John Fifield , Wagdi Abadeer , William Tonti
发明人： John Fifield , Wagdi Abadeer , William Tonti
IPC分类号： H01L23/525 , H01L29/00
CPC分类号： H01L23/5252 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： An antifuse device (120) that includes a bias element (124) and an programmable antifuse element (128) arranged in series with one another so as to form a voltage divider having an output node (F) located between the bias and antifuse elements. When the antifuse device is in its unprogrammed state, each of the bias element and antifuse element is non-conductive. When the antifuse device is in its programmed state, the bias element remains non-conductive, but the antifuse element is conductive. The difference in the resistance of the antifuse element between its unprogrammed state and programmed state causes the difference in voltages seen at the output node to be on the order of hundreds of mili-volts when a voltage of 1 V is applied across the antifuse device. This voltage difference is so high that it can be readily sensed using a simple sensing circuit (228).
摘要翻译：一种反熔丝装置（120），其包括彼此串联布置的偏置元件（124）和可编程反熔丝元件（128），以形成具有位于偏置和反熔丝元件之间的输出节点（F）的分压器。当反熔丝装置处于其未编程状态时，偏置元件和反熔丝元件中的每一个都是不导电的。当反熔丝装置处于其编程状态时，偏置元件保持不导电，但是反熔丝元件是导电的。反熔丝元件在其未编程状态和编程状态之间的电阻差异导致当在反熔断器件上施加1V的电压时，在输出节点处看到的电压差为几百微升。该电压差非常高以至于可以使用简单的感测电路（228）容易地感测。

10. 发明申请

US20050122160A1 Method and circuit for compensating for tunneling current 失效
标题翻译：用于补偿隧道电流的方法和电路
公开(公告)号：US20050122160A1
公开(公告)日：2005-06-09
申请号：US10731298
申请日：2003-12-09
申请人： Wagdi Abadeer , Jennifer Appleyard , John Fifield , William Tonti
发明人： Wagdi Abadeer , Jennifer Appleyard , John Fifield , William Tonti
IPC分类号： G05F3/02 , G05F3/24
CPC分类号： G05F3/242
摘要： A method and circuit for tunneling leakage current compensation, the method including: forcing a current of known value through a tunneling current leakage monitor device to provide a voltage signal; and regulating an on-chip power supply of the integrated circuit chip based on the voltage signal.
摘要翻译：一种用于隧道泄漏电流补偿的方法和电路，所述方法包括：通过隧道电流泄漏监测装置强制已知值的电流以提供电压信号; 以及基于所述电压信号来调节所述集成电路芯片的片上电源。

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