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61. 发明授权

US08302043B2 Verification of logic circuit designs using dynamic clock gating 有权
标题翻译：使用动态时钟门控验证逻辑电路设计
公开(公告)号：US08302043B2
公开(公告)日：2012-10-30
申请号：US12876319
申请日：2010-09-07
申请人： Christian Habermann , Christian Jacobi , Matthias Pflanz , Hans-Werner Tast , Ralf Winkelmann
发明人： Christian Habermann , Christian Jacobi , Matthias Pflanz , Hans-Werner Tast , Ralf Winkelmann
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G06F2217/78
摘要： A method and system for verifying a logic circuit design using dynamic clock gating is disclosed. The method comprises choosing at least one master seed to determine initial values as initialization for said logic circuit and/or stimuli data for at least one interface of said logic circuit, choosing at least two different dynamic clock gating configurations for every chosen master seed, executing a functional simulation with said logic circuit for every chosen dynamic clock gating configuration by using said determined initialization and/or stimuli data based on a corresponding master seed, comparing simulation results of functional simulations against each other executed with said logic circuit for at least two different chosen dynamic clock gating configurations, and reporting an error if said at least two simulation results are not identical.
摘要翻译：公开了一种使用动态时钟门控验证逻辑电路设计的方法和系统。所述方法包括：选择至少一个主粒子以将初始值确定为所述逻辑电路的初始化和/或所述逻辑电路的至少一个接口的刺激数据，为每个所选择的主子选择至少两个不同的动态时钟选通配置，执行通过使用基于对应的主子种的所述确定的初始化和/或刺激数据，针对每个所选择的动态时钟门控配置，利用所述逻辑电路进行功能仿真，将与所述逻辑电路执行的功能模拟的仿真结果相互比较，用于至少两个不同的所选择的动态时钟门控配置，并且如果至少两个模拟结果不相同，则报告错误。

62. 发明授权

US08015362B2 Method and system for handling cache coherency for self-modifying code 有权
标题翻译：用于处理缓存一致性的自修改代码的方法和系统
公开(公告)号：US08015362B2
公开(公告)日：2011-09-06
申请号：US12031923
申请日：2008-02-15
申请人： Gregory W. Alexander , Christian Jacobi , Barry W. Krumm , Chung-Lung Kevin Shum , Aaron Tsai
发明人： Gregory W. Alexander , Christian Jacobi , Barry W. Krumm , Chung-Lung Kevin Shum , Aaron Tsai
IPC分类号： G06F12/00
CPC分类号： G06F12/0848 , G06F9/3812
摘要： A method for handling cache coherency includes allocating a tag when a cache line is not exclusive in a data cache for a store operation, and sending the tag and an exclusive fetch for the line to coherency logic. An invalidation request is sent within a minimum amount of time to an I-cache, preferably only if it has fetched to the line and has not been invalidated since, which request includes an address to be invalidated, the tag, and an indicator specifying the line is for a PSC operation. The method further includes comparing the request address against stored addresses of prefetched instructions, and in response to a match, sending a match indicator and the tag to an LSU, within a maximum amount of time. The match indicator is timed, relative to exclusive data return, such that the LSU can discard prefetched instructions following execution of the store operation that stores to a line subject to an exclusive data return, and for which the match is indicated.
摘要翻译：一种用于处理高速缓存一致性的方法包括当高速缓存行在存储操作的数据高速缓存中不排斥时分配标签，以及将该标签和该行的独占提取发送到一致性逻辑。无效请求在最小时间内被发送到I缓存，优选地只有当它已经被取出到该行并且没有被无效时，因为哪个请求包括要被无效的地址，该标签和一个指示线路用于PSC操作。该方法还包括将请求地址与预取指令的存储地址进行比较，并且响应于匹配，在最大时间量内向LSU发送匹配指示符和标签。匹配指示符相对于独占数据返回是定时的，使得LSU可以执行存储操作之后丢弃预取指令，存储到受独占数据返回的行，并且指示匹配。

63. 发明申请

US20110185158A1 HISTORY AND ALIGNMENT BASED CRACKING FOR STORE MULTIPLE INSTRUCTIONS FOR OPTIMIZING OPERAND STORE COMPARE PENALTIES 有权
标题翻译：用于存储多项指令的历史和对齐基础打破优化操作存储比较罚款
公开(公告)号：US20110185158A1
公开(公告)日：2011-07-28
申请号：US12695687
申请日：2010-01-28
申请人： KHARY J. ALEXANDER , Fadi Busaba , Brian Curran , Bruce Giamei , Christian Jacobi , James R. Mitchell
发明人： KHARY J. ALEXANDER , Fadi Busaba , Brian Curran , Bruce Giamei , Christian Jacobi , James R. Mitchell
IPC分类号： G06F9/40
CPC分类号： G06F9/30043 , G06F9/3017 , G06F9/3824 , G06F9/3838
摘要： Store multiple instructions are managed based on previous execution history and their alignment. At least one store multiple instruction is detected. A flag is determined to be associated with the at least one store multiple instruction. The flag indicates that the at least one store multiple instruction has previously encountered an operand store compare hazard. The at least one store multiple instruction is organized into a set of unit of operations. The set of unit of operations is executed. The executing avoids the operand store compare hazard previously encountered by the at least one store multiple instruction.
摘要翻译：存储多个指令是根据以前的执行历史及其对齐方式进行管理的。检测到至少一个存储多重指令。确定标志与至少一个存储多重指令相关联。该标志指示至少一个存储多指令先前已经遇到操作数存储比较危险。将至少一个存储多个指令组织成一组操作单元。执行一组操作单元。该执行避免了由至少一个存储多个指令先前遇到的操作数存储比较危险。

64. 发明申请

US20110066988A1 Method, System, Computer Program Product, and Data Processing Program for Verification of Logic Circuit Designs Using Dynamic Clock Gating 有权
标题翻译：方法，系统，计算机程序产品和用于使用动态时钟门控验证逻辑电路设计的数据处理程序
公开(公告)号：US20110066988A1
公开(公告)日：2011-03-17
申请号：US12876319
申请日：2010-09-07
申请人： Christian Habermann , Christian Jacobi , Matthias Pflanz , Hans-Werner Tast , Ralf Winkelmann
发明人： Christian Habermann , Christian Jacobi , Matthias Pflanz , Hans-Werner Tast , Ralf Winkelmann
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G06F2217/78
摘要： A method and system for verifying a logic circuit design using dynamic clock gating is disclosed. The method comprises choosing at least one master seed to determine initial values as initialization for said logic circuit and/or stimuli data for at least one interface of said logic circuit, choosing at least two different dynamic clock gating configurations for every chosen master seed, executing a functional simulation with said logic circuit for every chosen dynamic clock gating configuration by using said determined initialization and/or stimuli data based on a corresponding master seed, comparing simulation results of functional simulations against each other executed with said logic circuit for at least two different chosen dynamic clock gating configurations, and reporting an error if said at least two simulation results are not identical.
摘要翻译：公开了一种使用动态时钟门控验证逻辑电路设计的方法和系统。所述方法包括：选择至少一个主粒子以将初始值确定为所述逻辑电路的初始化和/或所述逻辑电路的至少一个接口的刺激数据，为每个所选择的主子选择至少两个不同的动态时钟选通配置，执行通过使用基于对应的主子种的所述确定的初始化和/或刺激数据，针对每个所选择的动态时钟门控配置，利用所述逻辑电路进行功能仿真，将与所述逻辑电路执行的功能模拟的仿真结果相互比较，用于至少两个不同的所选择的动态时钟门控配置，并且如果至少两个模拟结果不相同，则报告错误。

65. 发明申请

US20090083569A1 Generating a Local Clock Domain Using Dynamic Controls 失效
标题翻译：使用动态控件生成本地时钟域
公开(公告)号：US20090083569A1
公开(公告)日：2009-03-26
申请号：US11859819
申请日：2007-09-24
申请人： Sean Michael Carey , William Vincent Huott , Christian Jacobi , Guenter Mayer , Timothy Gerard McNamara , Chung-Lung Kevin Shum , Hans-Werner Tast , Michael Hemsley Wood
发明人： Sean Michael Carey , William Vincent Huott , Christian Jacobi , Guenter Mayer , Timothy Gerard McNamara , Chung-Lung Kevin Shum , Hans-Werner Tast , Michael Hemsley Wood
IPC分类号： G04F10/00 , H04L7/00 , G06F1/04
CPC分类号： G06F1/04 , G06F1/3275 , G11C7/22 , G11C7/222 , G11C11/413 , Y02D10/14
摘要： A method for generating a local clock domain within an operation includes steps of: receiving a clock frequency measurement for a slow portion of logic within the operation; generating a local signal to indicate commencement of the operation and to function as a clock gating signal; latching the clock gating signal to a selected cycle; generating clock domain controls based on the clock gating signal such that the operation times its commencement on the selected cycle; and propagating the clock gating signal in ungated latches for a number of cycles, such that a second operation is restricted from being launched until the operation completes.
摘要翻译：一种用于在操作中产生本地时钟域的方法包括以下步骤：在操作期间接收用于逻辑的较慢部分的时钟频率测量; 产生本地信号以指示操作的开始并用作时钟选通信号; 将时钟门控信号锁存到选定的周期; 基于时钟门控信号产生时钟域控制，使得操作在所选择的周期上开始生效; 并且在未锁定的锁存器中传播时钟门控信号多个周期，使得第二操作被限制为被启动直到操作完成。

66. 发明授权

US07506290B2 Method and system for case-splitting on nodes in a symbolic simulation framework 有权
标题翻译：符号仿真框架中节点分割的方法和系统
公开(公告)号：US07506290B2
公开(公告)日：2009-03-17
申请号：US11963264
申请日：2007-12-21
申请人： Christian Jacobi , Geert Janssen , Viresh Paruthi , Kai Oliver Weber
发明人： Christian Jacobi , Geert Janssen , Viresh Paruthi , Kai Oliver Weber
IPC分类号： G06F9/45 , G06F17/50
CPC分类号： G06F17/504
摘要： A method for performing verification includes receiving a design and building for the design an intermediate binary decision diagram set containing one or more nodes representing one or more variables. A first case-splitting is performed upon a first fattest variable from among the one or more variables represented by the one or more nodes by setting the first fattest variable to a primary value, and a first cofactoring is performed upon the intermediate binary decision diagram set with respect to the one or more nodes using an inverse of the primary value to generate a first cofactored binary decision diagram set. A second cofactoring is performed upon the intermediate binary decision diagram set with respect to the one or more nodes using the primary value to generate a second cofactored binary decision diagram set, and verification of the design is performed by evaluating a property of the second cofactored binary decision diagram set.
摘要翻译：用于执行验证的方法包括：为设计接收设计和构建包含表示一个或多个变量的一个或多个节点的中间二进制判定图集。通过将第一个胖子变量设置为一个初始值，对由一个或多个节点表示的一个或多个变量中的第一个胖子变量执行第一个分解，并且对该中间二进制判定图集执行第一个共同构想相对于使用主值的逆的一个或多个节点来生成第一辅因子二进制决策图集。对相对于一个或多个节点设置的中间二进制判定图，使用主值来生成第二共有二元决策图集，执行第二共同构想，并且通过评估第二构成二进制的属性来执行设计的验证决策图集。

67. 发明授权

US07475371B2 Method and system for case-splitting on nodes in a symbolic simulation framework 有权
公开(公告)号：US07475371B2
公开(公告)日：2009-01-06
申请号：US11963290
申请日：2007-12-21
申请人： Christian Jacobi , Geert Janssen , Viresh Paruthi , Kai Oliver Weber
发明人： Christian Jacobi , Geert Janssen , Viresh Paruthi , Kai Oliver Weber
IPC分类号： G06F9/45 , G06F17/50
CPC分类号： G06F17/504
摘要： A method for performing verification includes receiving a design and building for the design an intermediate binary decision diagram set containing one or more nodes representing one or more variables. A first case-splitting is performed upon a first fattest variable from among the one or more variables represented by the one or more nodes by setting the first fattest variable to a primary value, and a first cofactoring is performed upon the intermediate binary decision diagram set with respect to the one or more nodes using an inverse of the primary value to generate a first cofactored binary decision diagram set. A second cofactoring is performed upon the intermediate binary decision diagram set with respect to the one or more nodes using the primary value to generate a second cofactored binary decision diagram set, and verification of the design is performed by evaluating a property of the second cofactored binary decision diagram set.

68. 发明授权

US07447725B2 Apparatus for controlling rounding modes in single instruction multiple data (SIMD) floating-point units 失效
标题翻译：用于在单指令多数据（SIMD）浮点单元中控制舍入模式的装置
公开(公告)号：US07447725B2
公开(公告)日：2008-11-04
申请号：US10982110
申请日：2004-11-05
申请人： Sang Hoo Dhong , Harm Peter Hofstee , Christian Jacobi , Silvia Melitta Mueller , Hwa-Joon Oh
发明人： Sang Hoo Dhong , Harm Peter Hofstee , Christian Jacobi , Silvia Melitta Mueller , Hwa-Joon Oh
IPC分类号： G06F7/38
CPC分类号： G06F7/49947 , G06F7/483 , G06F7/49968 , G06F7/49973 , G06F7/49989 , G06F2207/3828
摘要： An apparatus for controlling rounding modes in a single instruction multiple data (SIMD) floating-point unit is disclosed. The SIMD floating-point unit includes a floating-point status-and-control register (FPSCR) having a first rounding mode bit field and a second rounding mode bit field. The SIMD floating-point unit also includes means for generating a first slice and a second slice. During a floating-point operation, the SIMD floating-point unit concurrently performs a first rounding operation on the first slice and a second rounding operation on the second slice according to a bit in the first rounding mode bit field and a bit in the second rounding mode bit field within the FPSCR, respectively.
摘要翻译：公开了一种用于在单指令多数据（SIMD）浮点单元中控制舍入模式的装置。 SIMD浮点单元包括具有第一舍入模式位字段和第二舍入模式位字段的浮点状态和控制寄存器（FPSCR）。 SIMD浮点单元还包括用于生成第一切片和第二切片的装置。在浮点运算期间，SIMD浮点单元根据第一舍入模式位字段中的位并且在第二舍入中的位同时对第一切片进行第一舍入运算，并对第二切片进行第二舍入运算 FPSCR中的模式位字段。

69. 发明授权

US07367001B2 Method, system and computer program product for verification of digital designs using case-splitting via constrained internal signals 有权
标题翻译：方法，系统和计算机程序产品，用于通过限制内部信号通过案例分割验证数字设计
公开(公告)号：US07367001B2
公开(公告)日：2008-04-29
申请号：US11002525
申请日：2004-12-02
申请人： Jason Raymond Baumgartner , Christian Jacobi , Viresh Paruthi , Kai Oliver Weber
发明人： Jason Raymond Baumgartner , Christian Jacobi , Viresh Paruthi , Kai Oliver Weber
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5022
摘要： A method of verifying a digital design is disclosed. The method comprises generating a reference model for a first digital design and creating an operational model for a second digital design, wherein the first digital design and the second digital design are intended to have a same logical function. A plurality of testcase types are then created by constraining one or more internal signals, and one or more test scripts representing the plurality of testcase types are produced. The method also includes verifying the second digital design with a testing simulation program by comparing results of the test scripts from the operational model and the reference model.
摘要翻译：公开了一种验证数字设计的方法。该方法包括生成用于第一数字设计的参考模型并创建用于第二数字设计的操作模型，其中第一数字设计和第二数字设计旨在具有相同的逻辑功能。然后通过约束一个或多个内部信号来创建多个测试用例类型，并且产生表示多个测试用例类型的一个或多个测试脚本。该方法还包括通过比较来自操作模型和参考模型的测试脚本的结果，通过测试模拟程序验证第二数字设计。

70. 发明申请

US20080077379A1 Computer Program Product for Verification of Digital Designs Using Case-Splitting via Constrained Internal Signals 有权
标题翻译：计算机程序产品用于通过约束内部信号使用案例分割来验证数字设计
公开(公告)号：US20080077379A1
公开(公告)日：2008-03-27
申请号：US11945069
申请日：2007-11-26
申请人： Jason Baumgartner , Christian Jacobi , Viresh Paruthi , Kai Weber
发明人： Jason Baumgartner , Christian Jacobi , Viresh Paruthi , Kai Weber
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： A method of verifying a digital design is disclosed. The method comprises generating a reference model for a first digital design and creating an operational model for a second digital design, wherein the first digital design and the second digital design are intended to have a same logical function. A plurality of testcase types are then created by constraining one or more internal signals, and one or more test scripts representing the plurality of testcase types are produced. The method also includes verifying the second digital design with a testing simulation program by comparing results of the test scripts from the operational model and the reference model.
摘要翻译：公开了一种验证数字设计的方法。该方法包括生成用于第一数字设计的参考模型并创建用于第二数字设计的操作模型，其中第一数字设计和第二数字设计旨在具有相同的逻辑功能。然后通过约束一个或多个内部信号来创建多个测试用例类型，并且产生表示多个测试用例类型的一个或多个测试脚本。该方法还包括通过比较来自操作模型和参考模型的测试脚本的结果，通过测试模拟程序验证第二数字设计。

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