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1. 发明授权

US07752583B2 System for verification of digital designs using case-splitting via constrained internal signals 失效
标题翻译：用于通过限制内部信号通过案例分解验证数字设计的系统
公开(公告)号：US07752583B2
公开(公告)日：2010-07-06
申请号：US11944956
申请日：2007-11-26
申请人： Jason Raymond Baumgartner , Christian Jacobi , Viresh Paruthi , Kai Oliver Weber
发明人： Jason Raymond Baumgartner , Christian Jacobi , Viresh Paruthi , Kai Oliver Weber
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5022
摘要： A method of verifying a digital design is disclosed. The method comprises generating a reference model for a first digital design and creating an operational model for a second digital design, wherein the first digital design and the second digital design are intended to have a same logical function. A plurality of testcase types are then created by constraining one or more internal signals, and one or more test scripts representing the plurality of testcase types are produced. The method also includes verifying the second digital design with a testing simulation program by comparing results of the test scripts from the operational model and the reference model.
摘要翻译：公开了一种验证数字设计的方法。该方法包括生成用于第一数字设计的参考模型并创建用于第二数字设计的操作模型，其中第一数字设计和第二数字设计旨在具有相同的逻辑功能。然后通过约束一个或多个内部信号来创建多个测试用例类型，并且产生表示多个测试用例类型的一个或多个测试脚本。该方法还包括通过比较来自操作模型和参考模型的测试脚本的结果，通过测试模拟程序来验证第二数字设计。

2. 发明授权

US07290229B2 Method and system for optimized handling of constraints during symbolic simulation 有权
标题翻译：在符号仿真期间优化处理约束的方法和系统
公开(公告)号：US07290229B2
公开(公告)日：2007-10-30
申请号：US11050592
申请日：2005-02-03
申请人： Jason Raymond Baumgartner , Christian Jacobi , Viresh Paruthi , Kai Oliver Weber
发明人： Jason Raymond Baumgartner , Christian Jacobi , Viresh Paruthi , Kai Oliver Weber
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： A method for verifying a design through symbolic simulation is disclosed. The method comprises creating one or more binary decision diagram variables for one or more inputs in a design containing one or more state variables and building a binary decision diagram for a first node of one or more nodes of the design. A binary decision diagram for the initial state function of one or more state variables of the design is generated and the design is subsequently initialized. Binary decisions diagrams for one or more constraints are synthesized. A set of constraint values is accumulated over time by combining the binary decision diagrams for the one or more constraints with a set of previously generated binary decision diagrams for a set of constraints previously used in one or more previous time-steps. A binary decision diagram for the next state function of the one or more state variables in the design is constructed in the presence of the constraints. The one or more state variables in the design are updated by propagating the binary decision diagram for the next state function to the one or more state variables and a set of binary decision diagrams for the one or more targets in the presence of the one or more constraints is calculated. The set of binary decision diagrams for one or more targets is constrained and the design is verified by determining whether the one or more targets were hit.
摘要翻译：公开了一种通过符号仿真验证设计的方法。该方法包括为包含一个或多个状态变量的设计中的一个或多个输入创建一个或多个二进制决策图变量，以及为设计的一个或多个节点的第一节点构建二进制决策图。生成设计的一个或多个状态变量的初始状态函数的二进制决策图，随后初始化设计。合成一个或多个约束的二进制决策图。通过将一个或多个约束的二进制判定图与先前在一个或多个先前时间步骤中使用的一组约束的先前生成的二进制决策图的组合来累积一组约束值。设计中一个或多个状态变量的下一个状态函数的二进制决策图是在有约束的情况下构建的。设计中的一个或多个状态变量通过将下一个状态函数的二进制决策图传播到一个或多个状态变量和一个或多个目标的存在下的一个或多个目标的一组二进制决策图来更新计算约束。用于一个或多个目标的二进制决策图集被约束，并且通过确定一个或多个目标是否被击中来验证设计。

3. 发明授权

US07458048B2 Computer program product for verification of digital designs using case-splitting via constrained internal signals 有权
标题翻译：用于通过限制内部信号通过案例分解验证数字设计的计算机程序产品
公开(公告)号：US07458048B2
公开(公告)日：2008-11-25
申请号：US11945069
申请日：2007-11-26
申请人： Jason Raymond Baumgartner , Christian Jacobi , Viresh Paruthi , Kai Oliver Weber
发明人： Jason Raymond Baumgartner , Christian Jacobi , Viresh Paruthi , Kai Oliver Weber
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5022
摘要： A method of verifying a digital design is disclosed. The method comprises generating a reference model for a first digital design and creating an operational model for a second digital design, wherein the first digital design and the second digital design are intended to have a same logical function. A plurality of testcase types are then created by constraining one or more internal signals, and one or more test scripts representing the plurality of testcase types are produced. The method also includes verifying the second digital design with a testing simulation program by comparing results of the test scripts from the operational model and the reference model.
摘要翻译：公开了一种验证数字设计的方法。该方法包括生成用于第一数字设计的参考模型并创建用于第二数字设计的操作模型，其中第一数字设计和第二数字设计旨在具有相同的逻辑功能。然后通过约束一个或多个内部信号来创建多个测试用例类型，并且产生表示多个测试用例类型的一个或多个测试脚本。该方法还包括通过比较来自操作模型和参考模型的测试脚本的结果，通过测试模拟程序验证第二数字设计。

4. 发明授权

US07367001B2 Method, system and computer program product for verification of digital designs using case-splitting via constrained internal signals 有权
标题翻译：方法，系统和计算机程序产品，用于通过限制内部信号通过案例分割验证数字设计
公开(公告)号：US07367001B2
公开(公告)日：2008-04-29
申请号：US11002525
申请日：2004-12-02
申请人： Jason Raymond Baumgartner , Christian Jacobi , Viresh Paruthi , Kai Oliver Weber
发明人： Jason Raymond Baumgartner , Christian Jacobi , Viresh Paruthi , Kai Oliver Weber
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5022
摘要： A method of verifying a digital design is disclosed. The method comprises generating a reference model for a first digital design and creating an operational model for a second digital design, wherein the first digital design and the second digital design are intended to have a same logical function. A plurality of testcase types are then created by constraining one or more internal signals, and one or more test scripts representing the plurality of testcase types are produced. The method also includes verifying the second digital design with a testing simulation program by comparing results of the test scripts from the operational model and the reference model.
摘要翻译：公开了一种验证数字设计的方法。该方法包括生成用于第一数字设计的参考模型并创建用于第二数字设计的操作模型，其中第一数字设计和第二数字设计旨在具有相同的逻辑功能。然后通过约束一个或多个内部信号来创建多个测试用例类型，并且产生表示多个测试用例类型的一个或多个测试脚本。该方法还包括通过比较来自操作模型和参考模型的测试脚本的结果，通过测试模拟程序验证第二数字设计。

5. 发明授权

US07853917B2 System for building binary decision diagrams efficiently in a structural network representation of a digital circuit 有权
标题翻译：用于在数字电路的结构网络表示中有效地构建二进制决策图的系统
公开(公告)号：US07853917B2
公开(公告)日：2010-12-14
申请号：US11963267
申请日：2007-12-21
申请人： Viresh Paruthi , Christian Jacobi , Geert Janssen , Jiazhao Xu , Kai Oliver Weber
发明人： Viresh Paruthi , Christian Jacobi , Geert Janssen , Jiazhao Xu , Kai Oliver Weber
IPC分类号： G06H17/50
CPC分类号： G06F17/30958 , G06F17/504 , Y10S707/99942
摘要： A method, system and computer program product for building decision diagrams efficiently in a structural network representation of a digital circuit using a dynamic resource constrained and interleaved depth-first-search and modified breadth-first-search schedule is disclosed. The method includes setting a first size limit for a first set of one or more m-ary decision representations describing a logic function and setting a second size limit for a second set of one or more m-ary decision representations describing a logic function. The first set of m-ary decision representations of the logic function is then built with one of the set of a depth-first technique or a breadth-first technique until the first size limit is reached, and a second set of m-ary decision representations of the logic function is built with the other technique until the second size limit is reached. In response to determining that a union of first set and the second set of m-ary decision representations do not describe the logic function, the first and second size limits are increased, and the steps of building the first and second set are repeated. In response to determining that the union of the first set of m-ary decision representations and the second set of m-ary decision representations describe the logic function, the union is reported.
摘要翻译：公开了一种用于在使用动态资源约束和交织的深度优先搜索和修改的宽度优先搜索时间表的数字电路的结构网络表示中有效地构建决策图的方法，系统和计算机程序产品。该方法包括：对描述逻辑功能的一个或多个多元决策表示的第一集合设置第一大小限制，并为描述逻辑功能的一个或多个虚拟决策表示的第二组设置第二大小限制。然后，利用深度优先技术或宽度优先技术的集合之一构建逻辑功能的第一组m元决定表示，直到达到第一大小限制，并且第二组m元决定使用其他技术构建逻辑功能的表示，直到达到第二个大小限制。响应于确定第一集合和第二组m元决定表示的并集不描述逻辑函数，增加第一和第二大小限制，并且重复构建第一集合和第二集合的步骤。响应于确定第一组m元决策表示和第二组m元决策表示的并集描述逻辑函数，报告联合。

6. 发明授权

US07836413B2 Building binary decision diagrams efficiently in a structural network representation of a digital circuit 有权
标题翻译：在数字电路的结构网络表示中有效地构建二进制决策图
公开(公告)号：US07836413B2
公开(公告)日：2010-11-16
申请号：US11963325
申请日：2007-12-21
申请人： Viresh Paruthi , Christian Jacobi , Geert Janssen , Jiazhao Xu , Kai Oliver Weber
发明人： Viresh Paruthi , Christian Jacobi , Geert Janssen , Jiazhao Xu , Kai Oliver Weber
IPC分类号： G06F17/50
CPC分类号： G06F17/30958 , G06F17/504 , Y10S707/99942
摘要： A method, system and computer program product for building decision diagrams efficiently in a structural network representation of a digital circuit using a dynamic resource constrained and interleaved depth-first-search and modified breadth-first-search schedule is disclosed. The method includes setting a first size limit for a first set of one or more m-ary decision representations describing a logic function and setting a second size limit for a second set of one or more m-ary decision representations describing a logic function. The first set of m-ary decision representations of the logic function is then built with one of the set of a depth-first technique or a breadth-first technique until the first size limit is reached, and a second set of m-ary decision representations of the logic function is built with the other technique until the second size limit is reached. In response to determining that a union of first set and the second set of m-ary decision representations do not describe the logic function, the first and second size limits are increased, and the steps of building the first and second set are repeated. In response to determining that the union of the first set of m-ary decision representations and the second set of m-ary decision representations describe the logic function, the union is reported.
摘要翻译：公开了一种用于在使用动态资源约束和交织的深度优先搜索和修改的宽度优先搜索时间表的数字电路的结构网络表示中有效地构建决策图的方法，系统和计算机程序产品。该方法包括：对描述逻辑功能的一个或多个多元决策表示的第一集合设置第一大小限制，并为描述逻辑功能的一个或多个虚拟决策表示的第二组设置第二大小限制。然后，利用深度优先技术或宽度优先技术的集合之一构建逻辑功能的第一组m元决定表示，直到达到第一大小限制，并且第二组m元决定使用其他技术构建逻辑功能的表示，直到达到第二个大小限制。响应于确定第一集合和第二组m元决定表示的并集不描述逻辑函数，增加第一和第二大小限制，并且重复构建第一集合和第二集合的步骤。响应于确定第一组m元决策表示和第二组m元决策表示的并集描述逻辑函数，报告联合。

7. 发明授权

US07340704B2 Method and system for optimized automated case-splitting via constraints in a symbolic simulation framework 失效
标题翻译：用于通过符号仿真框架中的约束优化自动案例分解的方法和系统
公开(公告)号：US07340704B2
公开(公告)日：2008-03-04
申请号：US11165455
申请日：2005-06-23
申请人： Jason Raymond Baumgartner , Christian Jacobi , Viresh Paruthi , Kai Weber
发明人： Jason Raymond Baumgartner , Christian Jacobi , Viresh Paruthi , Kai Weber
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： A method for performing verification is proposed. The method comprises receiving a design and building an intermediate binary decision diagram for the design containing one or more nodal binary decision diagrams. In response to a size of the intermediate binary decision diagram exceeding a size threshold, a node of the design is selected for case-splitting. A first case-splitting is performed upon the selected node of the design to generate a primary constraint for setting the selected node to a primary value. A first constraining is performed on one of the one or more nodal binary decision diagrams with the primary constraint to generate a primary final binary decision diagram, a first verification of the design is performed using the primary final binary decision diagram.
摘要翻译：提出了一种执行验证的方法。该方法包括接收设计并构建用于包含一个或多个节点二进制决策图的设计的中间二进制决策图。响应于超过尺寸阈值的中间二进制判定图的大小，设计的节点被选择用于案例分割。在设计的所选节点上执行第一个案例分解，以生成将所选节点设置为主值的主约束。在具有主要约束的一个或多个节点二进制决策图中的一个上执行第一约束以生成主要的最终二进制决策图，使用主要的最终二进制决策图来执行设计的第一次验证。

8. 发明授权

US07506290B2 Method and system for case-splitting on nodes in a symbolic simulation framework 有权
标题翻译：符号仿真框架中节点分割的方法和系统
公开(公告)号：US07506290B2
公开(公告)日：2009-03-17
申请号：US11963264
申请日：2007-12-21
申请人： Christian Jacobi , Geert Janssen , Viresh Paruthi , Kai Oliver Weber
发明人： Christian Jacobi , Geert Janssen , Viresh Paruthi , Kai Oliver Weber
IPC分类号： G06F9/45 , G06F17/50
CPC分类号： G06F17/504
摘要： A method for performing verification includes receiving a design and building for the design an intermediate binary decision diagram set containing one or more nodes representing one or more variables. A first case-splitting is performed upon a first fattest variable from among the one or more variables represented by the one or more nodes by setting the first fattest variable to a primary value, and a first cofactoring is performed upon the intermediate binary decision diagram set with respect to the one or more nodes using an inverse of the primary value to generate a first cofactored binary decision diagram set. A second cofactoring is performed upon the intermediate binary decision diagram set with respect to the one or more nodes using the primary value to generate a second cofactored binary decision diagram set, and verification of the design is performed by evaluating a property of the second cofactored binary decision diagram set.
摘要翻译：用于执行验证的方法包括：为设计接收设计和构建包含表示一个或多个变量的一个或多个节点的中间二进制判定图集。通过将第一个胖子变量设置为一个初始值，对由一个或多个节点表示的一个或多个变量中的第一个胖子变量执行第一个分解，并且对该中间二进制判定图集执行第一个共同构想相对于使用主值的逆的一个或多个节点来生成第一辅因子二进制决策图集。对相对于一个或多个节点设置的中间二进制判定图，使用主值来生成第二共有二元决策图集，执行第二共同构想，并且通过评估第二构成二进制的属性来执行设计的验证决策图集。

9. 发明授权

US07475371B2 Method and system for case-splitting on nodes in a symbolic simulation framework 有权
公开(公告)号：US07475371B2
公开(公告)日：2009-01-06
申请号：US11963290
申请日：2007-12-21
申请人： Christian Jacobi , Geert Janssen , Viresh Paruthi , Kai Oliver Weber
发明人： Christian Jacobi , Geert Janssen , Viresh Paruthi , Kai Oliver Weber
IPC分类号： G06F9/45 , G06F17/50
CPC分类号： G06F17/504
摘要： A method for performing verification includes receiving a design and building for the design an intermediate binary decision diagram set containing one or more nodes representing one or more variables. A first case-splitting is performed upon a first fattest variable from among the one or more variables represented by the one or more nodes by setting the first fattest variable to a primary value, and a first cofactoring is performed upon the intermediate binary decision diagram set with respect to the one or more nodes using an inverse of the primary value to generate a first cofactored binary decision diagram set. A second cofactoring is performed upon the intermediate binary decision diagram set with respect to the one or more nodes using the primary value to generate a second cofactored binary decision diagram set, and verification of the design is performed by evaluating a property of the second cofactored binary decision diagram set.

10. 发明申请

US20100146474A9 Method and System for Building Binary Decision Diagrams Efficiently in a Structural Network Representation of a Digital Circuit 有权
公开(公告)号：US20100146474A9
公开(公告)日：2010-06-10
申请号：US11963267
申请日：2007-12-21
申请人： Viresh Paruthi , Christian Jacobi , Geert Janssen , Jiazhao Xu , Kai Oliver Weber
发明人： Viresh Paruthi , Christian Jacobi , Geert Janssen , Jiazhao Xu , Kai Oliver Weber
IPC分类号： G06F17/50
CPC分类号： G06F17/30958 , G06F17/504 , Y10S707/99942
摘要： A method, system and computer program product for building decision diagrams efficiently in a structural network representation of a digital circuit using a dynamic resource constrained and interleaved depth-first-search and modified breadth-first-search schedule is disclosed. The method includes setting a first size limit for a first set of one or more m-ary decision representations describing a logic function and setting a second size limit for a second set of one or more m-ary decision representations describing a logic function. The first set of m-ary decision representations of the logic function is then built with one of the set of a depth-first technique or a breadth-first technique until the first size limit is reached, and a second set of m-ary decision representations of the logic function is built with the other technique until the second size limit is reached. In response to determining that a union of first set and the second set of m-ary decision representations do not describe the logic function, the first and second size limits are increased, and the steps of building the first and second set are repeated. In response to determining that the union of the first set of m-ary decision representations and the second set of m-ary decision representations describe the logic function, the union is reported.

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