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1. 发明授权

US07987384B2 Method, system, and computer program product for handling errors in a cache without processor core recovery 有权
标题翻译：用于在没有处理器核心恢复的情况下处理高速缓存中的错误的方法，系统和计算机程序产品
公开(公告)号：US07987384B2
公开(公告)日：2011-07-26
申请号：US12029516
申请日：2008-02-12
申请人： Christian Jacobi , Matthias Pflanz , Chung-Lung Kevin Shum , Hans-Werner Tast , Aaron Tsai
发明人： Christian Jacobi , Matthias Pflanz , Chung-Lung Kevin Shum , Hans-Werner Tast , Aaron Tsai
IPC分类号： G06F11/00
CPC分类号： G06F12/0804 , G06F11/1064 , G06F12/0855 , G06F12/0897
摘要： A method for handling errors in a cache memory without processor core recovery includes receiving a fetch request for data from a processor and simultaneously transmitting fetched data and a parity matching the parity of the fetched data to the processor. The fetched data is received from a higher-level cache into a low level cache of the processor. Upon determining that the fetched data failed an error check indicating that the fetched data is corrupted, the method includes requesting an execution pipeline to discontinue processing and flush its contents, and initiating a clean up sequence, which includes sending an invalidation request to the low level cache causing the low level cache to remove lines associated with the corrupted data, and requesting the execution pipeline to restart. The execution pipeline accesses a copy of the requested data from a higher-level storage location.
摘要翻译：用于处理高速缓冲存储器中没有处理器核心恢复的错误的方法包括从处理器接收对数据的取出请求，同时发送取出的数据以及将获取的数据的奇偶校验与校验符相匹配的处理器。将获取的数据从较高级别的高速缓存接收到处理器的低级缓存中。在确定所获取的数据失败的情况下，指示所取出的数据被破坏的错误检查失败，所述方法包括请求执行流水线中断处理和刷新其内容，以及启动清理序列，其包括将无效请求发送到低级别缓存导致低级缓存删除与损坏的数据相关联的行，并请求执行管道重新启动。执行流水线从较高级别的存储位置访问所请求的数据的副本。

2. 发明申请

US20090193308A1 Method and an Apparatus for Controlling an Unreliable Data Transfer in a Data Channel 失效
标题翻译：用于控制数据信道中的不可靠数据传输的方法和装置
公开(公告)号：US20090193308A1
公开(公告)日：2009-07-30
申请号：US12356191
申请日：2009-01-20
申请人： Christian Habermann , Christian Jacobi , Matthias Pflanz , Hans-Werner Tast , Ralf Winkelmann
发明人： Christian Habermann , Christian Jacobi , Matthias Pflanz , Hans-Werner Tast , Ralf Winkelmann
IPC分类号： G06F11/07
CPC分类号： H04L41/0654
摘要： Controlling an unreliable data transfer in a data channel from a transmitting unit to a receiving unit. A bypass mode or a buffer mode is activated depending on the error rate in the data channel. If bypass mode is selected, data packets are directly transferred in probation from the transmitting unit to the receiving unit by a bypass line. The data packets are error checked after the data transfer. If buffer mode is selected, data is transfer from the transmitting unit to the receiving unit by a buffer line via an error detecting and correcting unit and a buffer unit. The errors are detected and corrected during the data transfer.
摘要翻译：控制从发送单元到接收单元的数据信道中的不可靠数据传输。根据数据通道中的错误率，激活旁路模式或缓冲模式。如果选择了旁路模式，则通过旁路线将数据分组从发送单元直接传送到接收单元。数据包在数据传输后进行错误检查。如果选择了缓冲模式，则经由错误检测和校正单元和缓冲器单元通过缓冲线将数据从发送单元传送到接收单元。在数据传输期间检测和纠正错误。

3. 发明申请

US20080222590A1 Method and System for Building Binary Decision Diagrams Optimally for Nodes in a Netlist Graph Using Don't-Caring 失效
标题翻译：使用不关心网络列表图中的节点最佳构建二进制决策图的方法和系统
公开(公告)号：US20080222590A1
公开(公告)日：2008-09-11
申请号：US11683495
申请日：2007-03-08
申请人： Christian Jacobi , Udo Krautz , Viresh Paruthi , Matthias Pflanz , Kai O. Weber
发明人： Christian Jacobi , Udo Krautz , Viresh Paruthi , Matthias Pflanz , Kai O. Weber
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： An improved method, system and computer-readable medium for constructing binary decision diagrams for a netlist graph is disclosed. The method comprises traversing a netlist graph in a depth-first manner. At least one binary decision diagram is built for one input of a node of the netlist graph using a binary decision diagram for the other input of that node as a don't-care condition.
摘要翻译：公开了一种用于构建网表的二进制决策图的改进方法，系统和计算机可读介质。该方法包括以深度优先方式遍历网表。使用用于该节点的另一输入的二进制决策图作为不关心条件，为网表图形的节点的一个输入构建至少一个二进制决策图。

4. 发明申请

US20070168792A1 Method to Reduce Leakage Within a Sequential Network and Latch Circuit 审中-公开
标题翻译：降低连续网络和锁存电路泄漏的方法
公开(公告)号：US20070168792A1
公开(公告)日：2007-07-19
申请号：US11566462
申请日：2006-12-04
申请人： Harry Barowski , Tobias Gemmeke , Christian Jacobi , Matthias Pflanz
发明人： Harry Barowski , Tobias Gemmeke , Christian Jacobi , Matthias Pflanz
IPC分类号： G01R31/28
CPC分类号： H03K19/0016 , G01R31/318541 , H03K3/0372 , H03K3/0375
摘要： A method to reduce leakage within a sequential network comprising at least one latch and a combinatorial logic proximate to said latch, by applying an input vector on said sequential network during idle mode is described, the method comprising the steps of: overriding a static feedback of a latch comprising a static feedback loop with an input vector, and setting said sequential network into idle mode. Furthermore a latch circuit comprising a static feedback loop, to be used to perform said method is described, wherein said latch circuit comprises means to override a static feedback within said static feedback loop with an input vector before falling in idle mode.
摘要翻译：描述了一种通过在空闲模式期间通过在所述顺序网络上施加输入向量来减少包括至少一个锁存器和靠近所述锁存器的组合逻辑的顺序网络内的泄漏的方法，所述方法包括以下步骤：重写静态反馈锁存器，其包括具有输入向量的静态反馈回路，以及将所述顺序网络设置为空闲模式。此外，描述了包括用于执行所述方法的静态反馈回路的锁存电路，其中所述锁存电路包括在落入空闲模式之前用输入向量来覆盖所述静态反馈回路内的静态反馈的装置。

5. 发明申请

US20070050740A1 Method and System for Performing Functional Formal Verification of Logic Circuits 审中-公开
标题翻译：执行逻辑电路功能正式验证的方法和系统
公开(公告)号：US20070050740A1
公开(公告)日：2007-03-01
申请号：US11467651
申请日：2006-08-28
申请人： Christian Jacobi , Viresh Paruthi , Matthias Pflanz , Kai Weber
发明人： Christian Jacobi , Viresh Paruthi , Matthias Pflanz , Kai Weber
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： The present invention relates to a method, a computer program product and a system for performing functional formal verification. Error detection logic is verified by injecting errors in a hardware design description without any changes to the original design description. With the present invention both permanent and transient faults can be modelled, and the complete error space can be covered for all types of fault models that can be used at the RTL. The number of detected design errors is used to determine the overall coverage in relation to the number of injected errors. The error injection is prepared by adding additional circuits to an RTL netlist representation of the hardware logic design. Signal values for selected signals related to the error detection logic are compared for a modified netlist representation and for the original netlist using a formal verification tool.
摘要翻译：本发明涉及一种执行功能形式验证的方法，计算机程序产品和系统。通过在硬件设计描述中注入错误来验证错误检测逻辑，而不对原始设计描述进行任何更改。通过本发明，可以对永久和瞬态故障进行建模，并且可以对可在RTL中使用的所有类型的故障模型覆盖完整的误差空间。检测到的设计错误的数量用于确定与注入错误数量有关的总体覆盖。通过向硬件逻辑设计的RTL网表表示添加附加电路来准备错误注入。对于修改的网表表示和使用形式验证工具的原始网表来比较与错误检测逻辑相关的所选信号的信号值。

6. 发明授权

US08302043B2 Verification of logic circuit designs using dynamic clock gating 有权
标题翻译：使用动态时钟门控验证逻辑电路设计
公开(公告)号：US08302043B2
公开(公告)日：2012-10-30
申请号：US12876319
申请日：2010-09-07
申请人： Christian Habermann , Christian Jacobi , Matthias Pflanz , Hans-Werner Tast , Ralf Winkelmann
发明人： Christian Habermann , Christian Jacobi , Matthias Pflanz , Hans-Werner Tast , Ralf Winkelmann
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G06F2217/78
摘要： A method and system for verifying a logic circuit design using dynamic clock gating is disclosed. The method comprises choosing at least one master seed to determine initial values as initialization for said logic circuit and/or stimuli data for at least one interface of said logic circuit, choosing at least two different dynamic clock gating configurations for every chosen master seed, executing a functional simulation with said logic circuit for every chosen dynamic clock gating configuration by using said determined initialization and/or stimuli data based on a corresponding master seed, comparing simulation results of functional simulations against each other executed with said logic circuit for at least two different chosen dynamic clock gating configurations, and reporting an error if said at least two simulation results are not identical.
摘要翻译：公开了一种使用动态时钟门控验证逻辑电路设计的方法和系统。所述方法包括：选择至少一个主粒子以将初始值确定为所述逻辑电路的初始化和/或所述逻辑电路的至少一个接口的刺激数据，为每个所选择的主子选择至少两个不同的动态时钟选通配置，执行通过使用基于对应的主子种的所述确定的初始化和/或刺激数据，针对每个所选择的动态时钟门控配置，利用所述逻辑电路进行功能仿真，将与所述逻辑电路执行的功能模拟的仿真结果相互比较，用于至少两个不同的所选择的动态时钟门控配置，并且如果至少两个模拟结果不相同，则报告错误。

7. 发明申请

US20110066988A1 Method, System, Computer Program Product, and Data Processing Program for Verification of Logic Circuit Designs Using Dynamic Clock Gating 有权
标题翻译：方法，系统，计算机程序产品和用于使用动态时钟门控验证逻辑电路设计的数据处理程序
公开(公告)号：US20110066988A1
公开(公告)日：2011-03-17
申请号：US12876319
申请日：2010-09-07
申请人： Christian Habermann , Christian Jacobi , Matthias Pflanz , Hans-Werner Tast , Ralf Winkelmann
发明人： Christian Habermann , Christian Jacobi , Matthias Pflanz , Hans-Werner Tast , Ralf Winkelmann
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G06F2217/78
摘要： A method and system for verifying a logic circuit design using dynamic clock gating is disclosed. The method comprises choosing at least one master seed to determine initial values as initialization for said logic circuit and/or stimuli data for at least one interface of said logic circuit, choosing at least two different dynamic clock gating configurations for every chosen master seed, executing a functional simulation with said logic circuit for every chosen dynamic clock gating configuration by using said determined initialization and/or stimuli data based on a corresponding master seed, comparing simulation results of functional simulations against each other executed with said logic circuit for at least two different chosen dynamic clock gating configurations, and reporting an error if said at least two simulation results are not identical.
摘要翻译：公开了一种使用动态时钟门控验证逻辑电路设计的方法和系统。所述方法包括：选择至少一个主粒子以将初始值确定为所述逻辑电路的初始化和/或所述逻辑电路的至少一个接口的刺激数据，为每个所选择的主子选择至少两个不同的动态时钟选通配置，执行通过使用基于对应的主子种的所述确定的初始化和/或刺激数据，针对每个所选择的动态时钟门控配置，利用所述逻辑电路进行功能仿真，将与所述逻辑电路执行的功能模拟的仿真结果相互比较，用于至少两个不同的所选择的动态时钟门控配置，并且如果至少两个模拟结果不相同，则报告错误。

8. 发明授权

US08015451B2 Controlling an unreliable data transfer in a data channel 失效
标题翻译：控制数据通道中的不可靠数据传输
公开(公告)号：US08015451B2
公开(公告)日：2011-09-06
申请号：US12356191
申请日：2009-01-20
申请人： Christian Habermann , Christian Jacobi , Matthias Pflanz , Hans-Werner Tast , Ralf Winkelmann
发明人： Christian Habermann , Christian Jacobi , Matthias Pflanz , Hans-Werner Tast , Ralf Winkelmann
IPC分类号： G06F11/00
CPC分类号： H04L41/0654
摘要： Controlling an unreliable data transfer in a data channel from a transmitting unit to a receiving unit. A bypass mode or a buffer mode is activated depending on the error rate in the data channel. If bypass mode is selected, data packets are directly transferred in probation from the transmitting unit to the receiving unit by a bypass line. The data packets are error checked after the data transfer. If buffer mode is selected, data is transfer from the transmitting unit to the receiving unit by a buffer line via an error detecting and correcting unit and a buffer unit. The errors are detected and corrected during the data transfer.
摘要翻译：控制从发送单元到接收单元的数据信道中的不可靠数据传输。根据数据通道中的错误率，激活旁路模式或缓冲模式。如果选择了旁路模式，则通过旁路线将数据分组从发送单元直接传送到接收单元。数据包在数据传输后进行错误检查。如果选择了缓冲模式，则经由错误检测和校正单元和缓冲器单元通过缓冲线将数据从发送单元传送到接收单元。在数据传输期间检测和纠正错误。

9. 发明授权

US07890903B2 Method and system for formal verification of an electronic circuit design 有权
标题翻译：电子电路设计形式验证的方法和系统
公开(公告)号：US07890903B2
公开(公告)日：2011-02-15
申请号：US12129127
申请日：2008-05-29
申请人： Kai Weber , Matthias Pflanz , Christian Jacobi , Udo Krautz
发明人： Kai Weber , Matthias Pflanz , Christian Jacobi , Udo Krautz
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： A new and convenient methodology for proving the correctness of multiplier and multiply-accumulate circuit designs in a full custom design flow. Such an approach utilizes a basic description of the implemented algorithm, which is created in early phases of the design flow and requires only little extra work for the designer who spends most of the time in full-custom optimizations. Such an approach also defines arithmetic circuit at the arithmetic bit level and allows for the generation of a gate level netlist. Given a structural similarity between the specification and design under verification, a large amount of structural similarity between the generated netlists is obtained so that a standard equivalence checker can be utilized to verify the design against the specification.
摘要翻译：一种新的便捷的方法，用于在完整的定制设计流程中证明乘法器的正确性和乘法积累电路设计。这种方法利用了实现的算法的基本描述，该算法是在设计流程的早期阶段创建的，并且只需要花费大部分时间进行全自定义优化的设计人员的额外工作。这种方法还在算术位电平处定义运算电路，并允许生成门级网表。给定了在规范和验证设计之间的结构相似性，获得了生成的网表之间大量的结构相似性，从而可以利用标准的等价检验器来验证与规范相关的设计。

10. 发明申请

US20090300560A1 METHOD AND SYSTEM FOR FORMAL VERIFICATION OF AN ELECTRONIC CIRCUIT DESIGN 有权
标题翻译：用于电子电路设计的正式验证的方法和系统
公开(公告)号：US20090300560A1
公开(公告)日：2009-12-03
申请号：US12129127
申请日：2008-05-29
申请人： Kai Weber , Matthias Pflanz , Christian Jacobi , Udo Krautz
发明人： Kai Weber , Matthias Pflanz , Christian Jacobi , Udo Krautz
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： A new and convenient methodology for proving the correctness of multiplier and multiply-accumulate circuit designs in a full custom design flow. Such an approach utilizes a basic description of the implemented algorithm, which is created in early phases of the design flow and requires only little extra work for the designer who spends most of the time in full-custom optimizations. Such an approach also defines arithmetic circuit at the arithmetic bit level and allows for the generation of a gate level netlist. Given a structural similarity between the specification and design under verification, a large amount of structural similarity between the generated netlists is obtained so that a standard equivalence checker can be utilized to verify the design against the specification.
摘要翻译：一种新的便捷的方法，用于在完整的定制设计流程中证明乘法器的正确性和乘法积累电路设计。这种方法利用了实现的算法的基本描述，该算法是在设计流程的早期阶段创建的，并且只需要花费大部分时间进行全自定义优化的设计人员的额外工作。这种方法还在算术位电平处定义运算电路，并允许生成门级网表。给定了在规范和验证设计之间的结构相似性，获得了生成的网表之间大量的结构相似性，从而可以利用标准的等价检验器来验证与规范相关的设计。

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