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61. 发明授权

US06836166B2 Method and system for delay control in synchronization circuits 失效
标题翻译：同步电路延时控制方法与系统
公开(公告)号：US06836166B2
公开(公告)日：2004-12-28
申请号：US10339752
申请日：2003-01-08
申请人： Feng Lin , Brent Keeth , Brian Johnson
发明人： Feng Lin , Brent Keeth , Brian Johnson
IPC分类号： H03L706
CPC分类号： G11C7/222 , G11C7/1072 , H03L7/0814 , H03L7/0818 , H03L7/087
摘要： A synchronization circuit includes a first and second phase-shifting path circuit, with each generates a phase-shifted signal responsive to an input signal and the phase-shifted signal having respective fine and coarse phase shifts relative to the input signal. Each phase-shifting path circuit adjusts the coarse and fine phase shifts responsive to control signals. A selection circuit outputs one of the phase-shifted signals responsive to a selection signal. A control circuit monitors a phase shift between the input signal and the output phase-shifted signal and develops the selection and control signals to select one of the phase-shifting path circuits and to adjust the fine phase shift of the selected path circuit and the fine and coarse phase shifts of the other path circuit. When the fine delay of the selected phase-shifting path circuit has a threshold value, the control circuit develops the selection signal to select the other phase-shifting circuit.
摘要翻译：同步电路包括第一和第二移相路径电路，每个产生响应于输入信号的相移信号，并且相移信号相对于输入信号具有相应的精细和粗略的相移。每个移相路径电路响应于控制信号调整粗略和精细的相移。选择电路响应于选择信号输出一个相移信号。控制电路监视输入信号和输出相移信号之间的相移，并产生选择和控制信号以选择一个相移路径电路并调整所选路径电路的精细相移和精细和另一路径电路的粗相移。当所选择的移相路径电路的精细延迟具有阈值时，控制电路产生选择信号以选择另一个移相电路。

62. 发明授权

US06807500B2 Method and apparatus providing improved data path calibration for memory devices 失效
标题翻译：为存储器件提供改进的数据路径校准的方法和装置
公开(公告)号：US06807500B2
公开(公告)日：2004-10-19
申请号：US10292654
申请日：2002-11-13
申请人： Brian Johnson , Brent Keeth
发明人： Brian Johnson , Brent Keeth
IPC分类号： G06F112
CPC分类号： G11C29/028 , G11C7/1051 , G11C7/1066 , G11C7/1078 , G11C7/1093 , G11C7/22 , G11C7/222 , G11C29/02 , G11C29/50012 , G11C2207/2254
摘要： A method and apparatus for calibrating a data path of a digital circuit uses an even bit pseudo-random calibration pattern. A portion of the pattern is captured in a capture period and used to predict a next arriving portion of the calibration pattern. The next arriving portion of the calibration pattern is captured and then compared to the predicted pattern in a compare period, and the result of the comparison is used to relatively time data arriving in the data path to a clocking signal which clocks in the data. The time duration of the compare period may be varied to ensure that all possible bits of the calibration pattern are used in the calibration procedure.
摘要翻译：用于校准数字电路的数据路径的方法和装置使用偶数位伪随机校准模式。在捕获周期中捕获图案的一部分，并用于预测校准图案的下一个到达部分。捕获校准图案的下一个到达部分，然后在比较周期中与预测图案进行比较，并将比较结果用于到数据路径中的相对时间数据到数据中的时钟信号。可以改变比较周期的持续时间以确保在校准过程中使用校准图案的所有可能位。

63. 发明授权

US06697926B2 Method and apparatus for determining actual write latency and accurately aligning the start of data capture with the arrival of data at a memory device 有权
标题翻译：用于确定实际写入延迟并准确地将数据捕获的开始与数据到达存储器件的方法和装置
公开(公告)号：US06697926B2
公开(公告)日：2004-02-24
申请号：US09874289
申请日：2001-06-06
申请人： Brian Johnson , Brent Keeth , Troy A. Manning
发明人： Brian Johnson , Brent Keeth , Troy A. Manning
IPC分类号： G06F1200
CPC分类号： G11C29/028 , G06F13/1694 , G11C7/1072 , G11C7/1078 , G11C7/1093 , G11C11/401 , G11C29/50012 , G11C2207/2254
摘要： A method and apparatus for accurately determining the actual arrival of data at a memory device relative to the write clock to accurately align the start of data capture and the arrival of the data at the memory device is disclosed. The actual time of arrival of data at the inputs to a memory device is determined by sending back-to-back write commands along with a predetermined data pattern to the memory device. The data pattern is stored in a register and any difference between the predicted arrival time of the data and the actual arrival time of the data is determined by logic circuitry. Any determined difference can then be compensated for by delaying the start of the capture of the data at the memory device, thereby accurately aligning the start of the data capture and the arrival of the data at the memory device.
摘要翻译：公开了一种用于准确地确定数据在存储器件相对于写入时钟的实际到达以精确对准数据捕获的开始和数据到存储器件的方法和装置。将数据到输入到存储器件的实际时间通过与存储器件一起发送背靠背写入命令以及预定数据模式来确定。数据模式存储在寄存器中，数据的预计到达时间与数据的实际到达时间之间的任何差异由逻辑电路确定。然后可以通过延迟在存储器件处捕获数据的开始来补偿任何确定的差异，从而将数据捕获的开始和数据的到达准确地对准存储器件。

64. 发明授权

US06665223B2 Memory device and method having data path with multiple prefetch I/O configurations 有权
公开(公告)号：US06665223B2
公开(公告)日：2003-12-16
申请号：US10278509
申请日：2002-10-22
申请人： Brent Keeth , Brian Johnson , Troy A. Manning
发明人： Brent Keeth , Brian Johnson , Troy A. Manning
IPC分类号： G11C700
CPC分类号： G11C7/1072 , G11C7/1006 , G11C7/1018 , G11C7/1027 , G11C7/1045 , G11C7/1048 , G11C7/1051 , G11C7/106 , G11C7/1066 , G11C7/1069 , G11C7/1078 , G11C11/4093 , G11C11/4096 , G11C2207/107
摘要： A memory device is operable in either a high mode or a low speed mode. In either mode, 32 bits of data from each of two memory arrays are prefetched into respective sets of 32 flip-flops. In the high-speed mode, the prefetched data bits are transferred in parallel to 4 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 4 data bus terminals. In the low speed mode, two sets of prefetched data bits are transferred in parallel to 8 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 8 data bus terminals.

65. 发明授权

US06658523B2 System latency levelization for read data 有权
公开(公告)号：US06658523B2
公开(公告)日：2003-12-02
申请号：US09804221
申请日：2001-03-13
申请人： Jeffery W. Janzen , Brent Keeth , Kevin J. Ryan , Troy A. Manning , Brian Johnson
发明人： Jeffery W. Janzen , Brent Keeth , Kevin J. Ryan , Troy A. Manning , Brian Johnson
IPC分类号： G06F1200
CPC分类号： G11C7/22 , G11C7/1072
摘要： In a high speed memory subsystem differences in each memory device's minimum device read latency and differences in signal propagation time between the memory device and the memory controller can result in widely varying system read latencies. The present invention equalizes the system read latencies of every memory device in a high speed memory system by comparing the differences in system read latencies of each device and then operating each memory device with a device system read latency which causes every device to exhibit the same system read latency.

66. 发明授权

US06522172B2 High speed latch/register 有权
标题翻译：高速锁存/寄存器
公开(公告)号：US06522172B2
公开(公告)日：2003-02-18
申请号：US09812757
申请日：2001-03-20
申请人： Brent Keeth , Brian Johnson
发明人： Brent Keeth , Brian Johnson
IPC分类号： H03K1903
CPC分类号： H03K3/356121 , H03K3/012
摘要： A circuit having a data input pin for receiving a data signal, a clock input for receiving a clock signal and having a low setup time and a zero hold time is comprised of an input stage for periodically connecting a sampling device to the data input pin in response to the clock signal. An evaluation stage, responsive to the clock signal, evaluates the charge collected by the device at a time the device is disconnected from the data input pin. The evaluation stage produces a signal representative of the sampled charge. An output stage, responsive to the clock signal and the produced signal, outputs a data signal representative of the sampled data signal. The circuit may have a single data path and a single charge accumulating device such that an output signal representative of the sampled data signal is available on either the rising or the falling edge of the clock signal. Alternatively, multiple data paths may be provided as well as multiple charge accumulating devices so that data signals representative of the sampled data may be output on both the rising and the falling edge of the clock signal. The circuit can be operated as either a latch or a register. A method of operating a data acquisition and retention circuit having a zero hold time and of the type useful for receiving signals from a high speed bus is also disclosed.
摘要翻译：具有用于接收数据信号的数据输入引脚的电路，用于接收时钟信号并具有低建立时间和零保持时间的时钟输入包括用于将采样装置周期性地连接到数据输入引脚的输入级响应时钟信号。响应于时钟信号的评估阶段评估设备在与数据输入引脚断开连接时收集的电荷。评估阶段产生代表采样电荷的信号。响应于时钟信号和产生的信号的输出级输出表示采样数据信号的数据信号。电路可以具有单个数据路径和单个电荷累积装置，使得表示采样数据信号的输出信号在时钟信号的上升沿或下降沿都可用。或者，可以提供多个数据路径以及多个电荷累积装置，使得表示采样数据的数据信号可以在时钟信号的上升沿和下降沿两者上输出。该电路可以作为锁存器或寄存器来操作。还公开了一种操作具有零保持时间的数据采集和保持电路以及用于从高速总线接收信号的类型的方法。

67. 发明授权

US06480031B2 High speed latch/register 有权
标题翻译：高速锁存/寄存器
公开(公告)号：US06480031B2
公开(公告)日：2002-11-12
申请号：US10056384
申请日：2002-01-24
申请人： Brent Keeth , Brian Johnson
发明人： Brent Keeth , Brian Johnson
IPC分类号： H03K19096
CPC分类号： H03K3/356121 , H03K3/012
摘要： A circuit having a data pin, an input pin for receiving a clock signal and having a zero hold time, is comprised of a sampling transistor for collecting charge at the data pin during a setup time defined by the clock signal; a device for isolating the sampling transistor from the data pin in response to the clock signal; and an output stage for outputting a logic signal in response to the charge sampled by the sampling transistor and the clock signal. The circuit may have an inverter for producing the complement of the clock signal, and the device for isolating may include a multiplexer responsive to the clock signal and the complement of the clock signal. The circuit can be operated as either a latch or a register. A method of operating a data acquisition and retention circuit having a zero hold time is also disclosed.
摘要翻译：具有数据引脚的电路，用于接收时钟信号并具有零保持时间的输入引脚包括用于在由时钟信号定义的建立时间期间在数据引脚处收集电荷的采样晶体管; 用于响应于时钟信号将采样晶体管与数据引脚隔离的装置; 以及输出级，用于响应于由采样晶体管采样的电荷和时钟信号而输出逻辑信号。电路可以具有用于产生时钟信号的补码的反相器，并且用于隔离的装置可以包括响应于时钟信号和时钟信号的补码的多路复用器。该电路可以作为锁存器或寄存器来操作。还公开了具有零保持时间的操作数据采集和保持电路的方法。

68. 发明授权

US07881149B2 Write latency tracking using a delay lock loop in a synchronous DRAM 有权
标题翻译：使用同步DRAM中的延迟锁定环来写入延迟跟踪
公开(公告)号：US07881149B2
公开(公告)日：2011-02-01
申请号：US12551876
申请日：2009-09-01
申请人： James Brian Johnson , Feng Lin , Brent Keeth
发明人： James Brian Johnson , Feng Lin , Brent Keeth
IPC分类号： G11C8/00
CPC分类号： G11C29/50 , G11C7/1078 , G11C7/1087 , G11C7/1093 , G11C7/22 , G11C7/222 , G11C11/401 , G11C11/4076 , G11C11/4096 , G11C29/02 , G11C29/023 , G11C29/028 , G11C29/50012
摘要： A method and circuitry for improved write latency tracking in a SDRAM is disclosed. In one embodiment, a delay locked loop is used in the command portion of the write path, and receives the system clock as its reference input. The DLL includes a modeled delay which models the delay in transmission of the internal Write Valid signal and system clock distribution to the deserializers in the data path portion of the write path, which is otherwise controlled by the intermittently asserted write strobe signal. With the input distribution delay of the system clock (Clk) and the write strobe (WS) matched by design, the distributed system clock and Write Valid signal are synchronized to the WS distribution path by means of the DLL delay with reference to the system clock input to the DLL. By backing the distribution delay out of system clock as sent to the deserializers, the write valid signal is effectively synchronized with the write strobe, with the effect that data will be passed out of the deserializer circuitry to the memory array on time and consistent with the programmed write latency.
摘要翻译：公开了一种用于在SDRAM中改进写延迟跟踪的方法和电路。在一个实施例中，在写入路径的命令部分中使用延迟锁定环，并且接收系统时钟作为其参考输入。 DLL包括建模延迟，其将内部写入有效信号的传输延迟和系统时钟分布建模到写入路径的数据路径部分中的解串行器，否则由间歇性断言的写入选通信号控制。随着系统时钟（Clk）的输入分配延迟和设计匹配的写选通（WS），分布式系统时钟和写有效信号通过参考系统时钟的DLL延迟与WS分配路径同步输入到DLL。通过将分发延迟从发送到解串器的系统时钟中提取出来，写入有效信号与写入选通有效地同步，其影响是数据将及时从解串器电路传送到存储器阵列，并与编程写延迟。

69. 发明授权

US07660187B2 Method and apparatus for initialization of read latency tracking circuit in high-speed DRAM 有权
标题翻译：用于在高速DRAM中初始化读延迟跟踪电路的方法和装置
公开(公告)号：US07660187B2
公开(公告)日：2010-02-09
申请号：US12329779
申请日：2008-12-08
申请人： James Brian Johnson , Brent Keeth , Feng Dan Lin
发明人： James Brian Johnson , Brent Keeth , Feng Dan Lin
IPC分类号： G11C8/00 , H03L7/06
CPC分类号： G11C7/22 , G11C7/222 , G11C8/18 , G11C11/4072 , G11C11/4076 , G11C2207/2254 , H03L7/0812 , H03L7/095
摘要： A method of controlling the output of data from a memory device includes deriving from an external clock signal a read clock and a control clock for operating an array of storage cells, both the read clock and the control clock each being comprised of clock pulses. A value is preloaded into one or both of a first counter located in the read clock domain and a second counter located in the control clock domain such that the difference in starting counts between the two counters is equal to a column address strobe latency (L) minus a synchronization (SP) overhead. A start signal is generated for initiating production of a running count of the read clock pulses in the first counter. The input of the start signal to the second counter is delayed so as to delay the initiation of a running count of the control clock pulses. A value of the second counter is held in response to a read command. The held value of the second counter is compared to a running count of the first counter; and data is output from the memory device with the read clock signal in response to the comparing.
摘要翻译：控制来自存储器件的数据输出的方法包括从外部时钟信号导出读时钟和用于操作存储单元阵列的控制时钟，读时钟和控制时钟均由时钟脉冲组成。值被预加载到位于读时钟域中的第一计数器中的一个或两者，位于控制时钟域中的第二计数器，使得两个计数器之间的启动计数的差值等于列地址选通延迟（L）减去同步（SP）开销。产生起始信号，用于开始产生第一计数器中的读取时钟脉冲的运行计数。启动信号到第二计数器的输入被延迟，以延迟启动控制时钟脉冲的运行计数。响应于读取命令来保持第二计数器的值。将第二计数器的保持值与第一计数器的运行计数进行比较; 并且响应于比较，从存储器件输出具有读时钟信号的数据。

70. 发明申请

US20090323441A1 Write Latency Tracking Using a Delay Lock Loop in a Synchronous DRAM 有权
标题翻译：使用同步DRAM中的延迟锁定环来写入延迟跟踪
公开(公告)号：US20090323441A1
公开(公告)日：2009-12-31
申请号：US12551876
申请日：2009-09-01
申请人： James Brian Johnson , Feng Lin , Brent Keeth
发明人： James Brian Johnson , Feng Lin , Brent Keeth
IPC分类号： G11C7/00 , G11C8/18
CPC分类号： G11C29/50 , G11C7/1078 , G11C7/1087 , G11C7/1093 , G11C7/22 , G11C7/222 , G11C11/401 , G11C11/4076 , G11C11/4096 , G11C29/02 , G11C29/023 , G11C29/028 , G11C29/50012
摘要： A method and circuitry for improved write latency tracking in a SDRAM is disclosed. In one embodiment, a delay locked loop is used in the command portion of the write path, and receives the system clock as its reference input. The DLL includes a modeled delay which models the delay in transmission of the internal Write Valid signal and system clock distribution to the deserializers in the data path portion of the write path, which is otherwise controlled by the intermittently asserted write strobe signal. With the input distribution delay of the system clock (Clk) and the write strobe (WS) matched by design, the distributed system clock and Write Valid signal are synchronized to the WS distribution path by means of the DLL delay with reference to the system clock input to the DLL. By backing the distribution delay out of system clock as sent to the deserializers, the write valid signal is effectively synchronized with the write strobe, with the effect that data will be passed out of the deserializer circuitry to the memory array on time and consistent with the programmed write latency.
摘要翻译：公开了一种用于在SDRAM中改进写延迟跟踪的方法和电路。在一个实施例中，在写入路径的命令部分中使用延迟锁定环，并且接收系统时钟作为其参考输入。 DLL包括建模延迟，其将内部写入有效信号的传输延迟和系统时钟分布建模到写入路径的数据路径部分中的解串行器，否则由间歇性断言的写入选通信号控制。随着系统时钟（Clk）的输入分配延迟和设计匹配的写选通（WS），分布式系统时钟和写有效信号通过参考系统时钟的DLL延迟与WS分配路径同步输入到DLL。通过将分发延迟从发送到解串器的系统时钟中提取出来，写入有效信号与写入选通有效地同步，其影响是数据将及时从解串器电路传送到存储器阵列，并与编程写延迟。

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