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61. 发明申请

US20110109956A1 Plasmonic Device Tuned Using Physical Modulation 有权
标题翻译：使用物理调制调谐的等离子体装置
公开(公告)号：US20110109956A1
公开(公告)日：2011-05-12
申请号：US12646585
申请日：2009-12-23
申请人： Akinori Hashimura , Liang Tang , Apostolos T. Voutsas
发明人： Akinori Hashimura , Liang Tang , Apostolos T. Voutsas
IPC分类号： G02B26/00
CPC分类号： G02F1/23 , G02F1/19 , G02F2203/10
摘要： A plasmonic display device is provided that uses physical modulation mechanisms. The device is made from an electrically conductive bottom electrode and a first dielectric layer overlying the bottom electrode. The first dielectric layer is a piezoelectric material having an index of expansion responsive to an electric field. An electrically conductive top electrode overlies the first dielectric layer. A first plasmonic layer, including a plurality of discrete plasmonic particles, is interposed between the top and bottom electrodes and in contact with the first dielectric layer. In one aspect, the plasmonic particles are an expandable polymer material covered with a metal coating having a size responsive to an electric field.
摘要翻译：提供了使用物理调制机制的等离子体显示装置。该器件由导电底部电极和覆盖底部电极的第一电介质层制成。第一电介质层是具有响应于电场的扩展指数的压电材料。导电顶电极覆盖在第一电介质层上。包括多个离散等离子体激元的第一等离子体激元层介于顶电极和底电极之间并与第一电介质层接触。在一个方面，等离子体激元粒子是覆盖有对电场有响应尺寸的金属涂层的可膨胀聚合物材料。

62. 发明申请

US20110109870A1 Optical Spectrum Splitting for Black Color Display 有权
标题翻译：黑色显示屏的光谱分离
公开(公告)号：US20110109870A1
公开(公告)日：2011-05-12
申请号：US12873138
申请日：2010-08-31
申请人： Liang Tang , Akinori Hashimura , Apostolos T. Voutsas
发明人： Liang Tang , Akinori Hashimura , Apostolos T. Voutsas
IPC分类号： G02F1/13
CPC分类号： G02F1/139 , B82Y20/00 , G02B6/005 , G02B6/1225 , G02B6/1226 , G02F1/134309 , G02F1/19 , G02F2201/02 , G02F2201/122 , G02F2202/32 , G02F2202/36 , G02F2203/10 , G02F2203/34 , G02F2203/62
摘要： A display device is provided for reflecting a black color, as enabled by an optical splitting photonic liquid crystal waveguide. Sets of top and bottom electrodes are formed in a periodic pattern. A first dielectric layer overlies the set of bottom electrodes, made from a liquid crystal (LC) material with molecules having dipoles responsive to an electric field. A plasmonic layer, including a plurality of discrete plasmonic particles, is interposed between the sets of top and bottom electrodes, and is in contact with the first dielectric layer. A voltage potential is applied between the top and bottom electrodes, generating an electric field. Dipole local orientation and non-orientation regions are created in the liquid crystal molecules in response to the electric field, and a wavelength of light outside the visible spectrum is reflected in response to optical spectrum splitting of the incident light.
摘要翻译：提供用于反射黑色的显示装置，如通过光分裂光子液晶波导所实现的。顶部和底部电极组以周期性图案形成。第一电介质层覆盖由具有对电场响应的偶极子的分子的液晶（LC）材料制成的一组底部电极。包括多个离散等离子体激元的等离子体激元层插入在顶部和底部电极组之间，并与第一介电层接触。在顶部和底部电极之间施加电压电位，产生电场。响应于电场在液晶分子中产生偶极局部取向和非取向区域，并且响应于入射光的光谱分解反射可见光谱外的光的波长。

63. 发明授权

US07916986B2 Erbium-doped silicon nanocrystalline embedded silicon oxide waveguide 失效
标题翻译：掺铒硅纳米晶体嵌入式硅氧化物波导
公开(公告)号：US07916986B2
公开(公告)日：2011-03-29
申请号：US12112767
申请日：2008-04-30
申请人： Hao Zhang , Pooran Chandra Joshi , Apostolos T. Voutsas
发明人： Hao Zhang , Pooran Chandra Joshi , Apostolos T. Voutsas
IPC分类号： G02B6/26 , B05D5/06 , C23C14/48 , C23C14/16 , C23F1/00 , H01L21/00
CPC分类号： C23C16/30 , C23C16/56 , H01L21/02156 , H01L21/02164 , H01L21/02274 , H01L21/02321 , H01L21/02362 , H01L21/31608
摘要： An erbium (Er)-doped silicon (Si) nanocrystalline embedded silicon oxide (SiOx) waveguide and associated fabrication method are presented. The method provides a bottom layer, and forms an Er-doped Si nanocrystalline embedded SiOx film waveguide overlying the bottom layer, having a minimum optical attenuation at about 1540 nanometers (nm). Then, a top layer is formed overlying the Er-doped SiOx film. The Er-doped SiOx film is formed by depositing a silicon rich silicon oxide (SRSO) film using a high density plasma chemical vapor deposition (HDPCVD) process and annealing the SRSO film. After implanting Er+ ions, the Er-doped SiOx film is annealed again. The Er-doped Si nanocrystalline SiOx film includes has a first refractive index (n) in the range of 1.46 to 2.30. The top and bottom layers have a second refractive index, less than the first refractive index.
摘要翻译：提出了一种铒（Er）掺杂的硅（Si）纳米晶体嵌入式氧化硅（SiOx）波导及其制造方法。该方法提供底层，并且形成覆盖底层的掺铒Si纳米晶体的包含SiOx的薄膜波导，在约1540纳米（nm）处具有最小的光衰减。然后，形成覆盖Er掺杂的SiOx膜的顶层。通过使用高密度等离子体化学气相沉积（HDPCVD）方法沉积富硅氧化物（SRSO）膜并退火SRSO膜来形成Er掺杂的SiOx膜。在注入Er +离子后，再次对Er掺杂的SiOx膜进行退火。掺铒Si纳米晶SiOx膜的第一折射率（n）在1.46〜2.30的范围内。顶层和底层具有小于第一折射率的第二折射率。

64. 发明授权

US07786021B2 High-density plasma multilayer gate oxide 有权
标题翻译：高密度等离子体多层栅极氧化物
公开(公告)号：US07786021B2
公开(公告)日：2010-08-31
申请号：US11264979
申请日：2005-11-02
申请人： Pooran Chandra Joshi , Apostolos T. Voutsas
发明人： Pooran Chandra Joshi , Apostolos T. Voutsas
IPC分类号： H01L21/31 , H01L21/469
CPC分类号： H01L29/4908 , H01L21/02164 , H01L21/02274 , H01L21/02304 , H01L21/0234 , H01L21/28008 , H01L21/31612 , H01L29/6675 , H01L29/78642
摘要： A thin-film transistor (TFT) with a multilayer gate insulator is provided, along with a method for forming the same. The method comprises: forming a channel, first source/drain (S/D) region, and a second S/D region in a Silicon (Si) active layer; using a high-density plasma (HDP) source, growing a first layer of Silicon oxide (SiOx) from the Si active layer, to a first thickness, where x is less than, or equal to 2; depositing a second layer of SiOx having a second thickness, greater than the first thickness, overlying the first layer of SiOx; using the HDP source, additionally oxidizing the second layer of SiOx, wherein the first and second SiOx layers form a gate insulator; and, forming a gate electrode adjacent the gate insulator. In one aspect, the second Si oxide layer is deposited using a plasma-enhanced chemical vapor deposition (PECVD) process with tetraethylorthosilicate (TEOS) precursors.
摘要翻译：提供具有多层栅极绝缘体的薄膜晶体管（TFT）及其形成方法。该方法包括：在硅（Si）有源层中形成沟道，第一源/漏（S / D）区和第二S / D区; 使用高密度等离子体（HDP）源，从Si活性层生长第一层氧化硅（SiO x）至第一厚度，其中x小于或等于2; 在SiOx的第一层上沉积具有大于第一厚度的第二厚度的第二SiO x层; 使用HDP源，另外氧化SiO x的第二层，其中第一和第二SiO x层形成栅极绝缘体; 并且形成与栅极绝缘体相邻的栅电极。在一个方面，使用等离子体增强化学气相沉积（PECVD）法与原硅酸四乙酯（TEOS）前体沉积第二Si氧化物层。

65. 发明申请

US20100102323A1 Directionally Annealed Silicon Film Having a (100)-Normal Crystallographical Orientation 审中-公开
标题翻译：具有（100） - 正常晶体取向的定向退火硅膜
公开(公告)号：US20100102323A1
公开(公告)日：2010-04-29
申请号：US12258363
申请日：2008-10-24
申请人： Robert S. Sposili , Apostolos T. Voutsas
发明人： Robert S. Sposili , Apostolos T. Voutsas
IPC分类号： H01L29/04 , H01L21/36
CPC分类号： H01L21/02609 , H01L21/02422 , H01L21/02532 , H01L21/02675 , H01L27/1285
摘要： A method is provided for forming a directionally crystallized (100)-normal crystallographic orientation silicon (Si) film. The method provides a substrate including Si. An amorphous Si (a-Si) layer is formed overlying the substrate, and a silicon oxide cap layer is formed overlying the a-Si layer. In response to scanning a laser in a first direction along a top surface of the silicon oxide cap layer, the a-Si layer is transformed into a crystalline Si film having a (100)-normal crystallographic orientation, with crystal grains elongated in the first direction. That is, the crystalline Si film has grain boundaries between crystal grains, aligned in parallel with the first direction.
摘要翻译：提供了一种用于形成定向结晶（100） - 正常晶体取向硅（Si）膜的方法。该方法提供包括Si的衬底。在衬底上形成非晶Si（a-Si）层，并且形成覆盖a-Si层的氧化硅覆盖层。响应于沿着氧化硅盖层的顶表面沿第一方向扫描激光器，将a-Si层转变为具有（100） - 正常结晶取向的晶体Si膜，其中晶粒在第一方向。也就是说，晶体Si膜在晶粒之间具有与第一方向平行排列的晶界。

66. 发明授权

US07532187B2 Dual-gate transistor display 有权
标题翻译：双栅晶体管显示
公开(公告)号：US07532187B2
公开(公告)日：2009-05-12
申请号：US11184699
申请日：2005-07-18
申请人： Themistokles Afentakis , Apostolos T. Voutsas , Paul J. Schuele
发明人： Themistokles Afentakis , Apostolos T. Voutsas , Paul J. Schuele
IPC分类号： G09G3/36 , G09G3/32
CPC分类号： G09G3/20 , G09G3/3208 , G09G3/3659 , G09G2300/08 , G09G2310/0262 , H01L29/78648
摘要： A dual-gate thin-film transistor (DG-TFT) voltage storage circuit is provided. The circuit includes a voltage storage element, a DG-TFT having a first source/drain (S/D) connected to a data line, a top gate connected to a first gate line, a second S/D region connected to the voltage storage element, and a bottom gate connected to a bias line. In one aspect, the circuit further includes a voltage shifter having an input connected to the first gate line and an output to supply a bias voltage on the bias line. Examples of a voltage storage element include a capacitor, a liquid crystal (LC) pixel, and a light emitting diode (LED) pixel.
摘要翻译：提供了双栅极薄膜晶体管（DG-TFT）电压存储电路。电路包括电压存储元件，具有连接到数据线的第一源极/漏极（S / D）的DG-TFT，连接到第一栅极线的顶栅极，连接到电压存储器的第二S / D区域元件和连接到偏置线的底栅。在一个方面，电路还包括具有连接到第一栅极线的输入的电压移位器和用于在偏置线上提供偏置电压的输出。电压存储元件的实例包括电容器，液晶（LC）像素和发光二极管（LED）像素。

67. 发明申请

US20090115311A1 Fabrication of a Semiconductor Nanoparticle Embedded Insulating Film Electroluminescence Device 有权
标题翻译：半导体纳米颗粒嵌入式绝缘膜电致发光器件的制造
公开(公告)号：US20090115311A1
公开(公告)日：2009-05-07
申请号：US12187605
申请日：2008-08-07
申请人： Pooran Chandra Joshi , Jiandong Huang , Apostolos T. Voutsas
发明人： Pooran Chandra Joshi , Jiandong Huang , Apostolos T. Voutsas
IPC分类号： H05B33/00 , H01L21/38
CPC分类号： C23C16/30 , C23C16/24 , C23C16/401 , C23C16/402 , C23C16/505 , C23C16/56 , H01L21/0214 , H01L21/02274 , H01L21/02321 , H01L21/0234 , H01L21/02532 , H01L21/02601 , H01L21/0262 , H01L21/31608 , H01L33/18
摘要： A method is provided for fabricating a semiconductor nanoparticle embedded Si insulating film for electroluminescence (EL) applications. The method provides a bottom electrode, and deposits a semiconductor nanoparticle embedded Si insulating film, including an element selected from a group consisting of N and C, overlying the bottom electrode. After annealing, a semiconductor nanoparticle embedded Si insulating film is formed having an extinction coefficient (k) in a range of 0.01-1.0, as measured at about 632 nanometers (nm), and a current density (J) of greater than 1 Ampere per square centimeter (A/cm2) at an applied electric field lower than 3 MV/cm. In another aspect, the annealed semiconductor nanoparticle embedded Si insulating film has an index of refraction (n) in a range of 1.8-3.0, as measured at 632 nm, with a current density of greater than 1 A/cm2 at an applied electric field lower than 3 MV/cm.
摘要翻译：提供了一种用于制造用于电致发光（EL）应用的半导体纳米颗粒嵌入的Si绝缘膜的方法。该方法提供底部电极，并且沉积半导体纳米颗粒嵌入的Si绝缘膜，其包括选自N和C组成的组的元素，覆盖在底部电极上。在退火之后，形成半导体纳米颗粒嵌入的Si绝缘膜，其消光系数（k）在0.01〜1.0的范围内，在大约632纳米（nm）测量，电流密度（J）大于1安培在施加的电场低于3MV / cm下的平方厘米（A / cm 2）。在另一方面，被退火的半导体纳米颗粒嵌入的Si绝缘膜的折射率（n）在632nm处测量的范围为1.8-3.0，在施加的电场下的电流密度大于1A / cm 2 低于3 MV / cm。

68. 发明授权

US07446023B2 High-density plasma hydrogenation 失效
标题翻译：高密度等离子体氢化
公开(公告)号：US07446023B2
公开(公告)日：2008-11-04
申请号：US11013605
申请日：2004-12-15
申请人： Pooran Chandra Joshi , Apostolos T. Voutsas , John W. Hartzell
发明人： Pooran Chandra Joshi , Apostolos T. Voutsas , John W. Hartzell
IPC分类号： H01L21/332
CPC分类号： H01L21/02164 , C23C16/24 , C23C16/45523 , C23C16/509 , H01L21/022 , H01L21/02274 , H01L21/02323 , H01L21/0234 , H01L21/02381 , H01L21/0242 , H01L21/02422 , H01L21/0245 , H01L21/02532 , H01L21/28194 , H01L21/28211 , H01L21/3003 , H01L21/31612 , H01L29/4908 , H01L29/513 , H01L29/78609
摘要： A high-density plasma hydrogenation method is provided. Generally, the method comprises: forming a silicon (Si)/oxide stack layer; plasma oxidizing the Si/oxide stack at a temperature of less than 400° C., using a high density plasma source, such as an inductively coupled plasma (ICP) source; introducing an atmosphere including H2 at a system pressure up to 500 milliTorr; hydrogenating the stack at a temperature of less than 400 degrees C., using the high density plasma source; and forming an electrode overlying the oxide. The electrode may be formed either before or after the hydrogenation. The Si/oxide stack may be formed in a number of ways. In one aspect, a Si layer is formed, and the silicon layer is plasma oxidized at a temperature of less than 400 degrees C., using an ICP source. The oxide formation, additional oxidation, and hydrogenation steps can be conducted in-situ in a common chamber.
摘要翻译：提供了高密度等离子体加氢方法。通常，该方法包括：形成硅（Si）/氧化物堆叠层; 使用诸如电感耦合等离子体（ICP）源的高密度等离子体源，在小于400℃的温度下等离子体氧化Si /氧化物堆叠; 在系统压力高达500毫托的地方引入包括H2的气氛; 使用高密度等离子体源在小于400摄氏度的温度下对叠层进行氢化; 并形成覆盖氧化物的电极。电极可以在氢化之前或之后形成。 Si /氧化物堆叠可以以多种方式形成。在一个方面，使用ICP源形成Si层，并且在低于400℃的温度下对硅层进行等离子体氧化。氧化物形成，附加氧化和氢化步骤可以在公共室中原位进行。

69. 发明申请

US20080224205A1 Vertical Thin-Film Transistor with Enhanced Gate Oxide 有权
标题翻译：具有增强型栅极氧化物的垂直薄膜晶体管
公开(公告)号：US20080224205A1
公开(公告)日：2008-09-18
申请号：US12108333
申请日：2008-04-23
申请人： Pooran Chandra Joshi , Apostolos T. Voutsas , John W. Hartzell
发明人： Pooran Chandra Joshi , Apostolos T. Voutsas , John W. Hartzell
IPC分类号： H01L29/786 , H01L29/41
CPC分类号： H01L29/78642 , C23C16/24 , C23C16/45523 , C23C16/509 , H01L21/02164 , H01L21/0234 , H01L21/049 , H01L21/31612 , H01L29/66666 , H01L29/6675
摘要： A method is provided for forming a low-temperature vertical gate insulator in a vertical thin-film transistor (V-TFT) fabrication process. The method comprises: forming a gate, having vertical sidewalls and a top surface, overlying a substrate insulation layer; depositing a silicon oxide thin-film gate insulator overlying the gate; plasma oxidizing the gate insulator at a temperature of less than 400° C., using a high-density plasma source; forming a first source/drain region overlying the gate top surface; forming a second source/drain region overlying the substrate insulation layer, adjacent a first gate sidewall; and, forming a channel region overlying the first gate sidewall, in the gate insulator interposed between the first and second source/drain regions. When the silicon oxide thin-film gate insulator is deposited overlying the gate a Si oxide layer, a low temperature deposition process can be used, so that a step-coverage of greater than 65% can be obtained.
摘要翻译：提供一种用于在垂直薄膜晶体管（V-TFT）制造工艺中形成低温垂直栅极绝缘体的方法。该方法包括：形成具有垂直侧壁和顶表面的栅极，覆盖衬底绝缘层; 沉积覆盖栅极的氧化硅薄膜栅极绝缘体; 使用高密度等离子体源在低于400℃的温度下等离子体氧化栅极绝缘体; 形成覆盖所述栅极顶表面的第一源极/漏极区域; 在第一栅极侧壁附近形成覆盖衬底绝缘层的第二源极/漏极区域; 以及在位于第一和第二源极/漏极区之间的栅极绝缘体中形成覆盖第一栅极侧壁的沟道区。当氧化硅薄膜栅极绝缘体沉积在栅极上覆盖Si氧化物层时，可以使用低温沉积工艺，从而可以获得大于65％的阶梯覆盖率。

70. 发明授权

US06995053B2 Vertical thin film transistor 失效
标题翻译：垂直薄膜晶体管
公开(公告)号：US06995053B2
公开(公告)日：2006-02-07
申请号：US10831424
申请日：2004-04-23
申请人： Paul J. Schuele , Apostolos T. Voutsas
发明人： Paul J. Schuele , Apostolos T. Voutsas
IPC分类号： H01L27/01
CPC分类号： H01L27/12 , H01L29/78624 , H01L29/78642 , H01L29/78648 , H01L29/78675
摘要： A vertical thin-film transistor (V-TFT) is provided along with a method for forming the V-TFT. The method comprises: providing a substrate made from a material such as Si, quartz, glass, or plastic; conformally depositing an insulating layer overlying the substrate; forming a gate, having sidewalls and a thickness, overlying a substrate insulation layer; forming a gate oxide layer overlying the gate sidewalls, and a gate insulation layer overlying the gate top surface; etching the exposed substrate insulation layer; forming a first source/drain region overlying the gate insulation layer; forming a second source/drain region overlying the substrate insulation layer, adjacent a first gate sidewall; and, forming a channel region overlying the first gate sidewall with a channel length about equal to the thickness of the gate, interposed between the first and second source/drain regions.
摘要翻译：提供垂直薄膜晶体管（V-TFT）以及用于形成V-TFT的方法。该方法包括：提供由诸如Si，石英，玻璃或塑料的材料制成的衬底; 保形地沉积覆盖衬底的绝缘层; 形成具有覆盖衬底绝缘层的侧壁和厚度的栅极; 形成覆盖所述栅极侧壁的栅极氧化层，以及覆盖所述栅极顶表面的栅极绝缘层; 蚀刻暴露的基板绝缘层; 形成覆盖所述栅极绝缘层的第一源极/漏极区域; 在第一栅极侧壁附近形成覆盖衬底绝缘层的第二源极/漏极区域; 并且在第一和第二源极/漏极区域之间形成沟槽区域，该沟道区域覆盖具有大约等于栅极厚度的沟道长度的第一栅极侧壁。

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